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aarch64: simplify calls to __libc_arm_za_disable in assembly

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There is no functional change in this patch.

We remove stores and loads to stack, return address signing, and redundant
CFI directives before and after call to __libc_arm_za_disable().

The __libc_arm_za_disable implementation follows special calling convention
that allows to avoid most of the operations that would be necessary for a
call to a normal function (see [1] for details).

First, we rely on __libc_arm_za_disable() not clobbering certain registers,
and we put return address into one of these registers. Now we don't need
to store it on stack, so we don't need to sign return address using PAC.

Second, as a result of the above, we don't need to update the CFI offset.

This patch provides small optimisation avoiding unnecessary store and load
on stack also simplifies assembly code and CFI directives.

[1]: https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst

Reviewed-by: Adhemerval Zanella  <adhemerval.zanella@linaro.org>
This commit is contained in:
Yury Khrustalev
2025-06-16 10:01:22 +01:00
parent eeedfc2f74
commit c0f0db2d59
3 changed files with 27 additions and 42 deletions
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23
sysdeps/unix/sysv/linux/aarch64/setcontext.S
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@ -48,21 +48,16 @@ ENTRY (__setcontext)
cbz x0, 1f
b C_SYMBOL_NAME (__syscall_error)
1:
/* Disable ZA of SME. */
paciasp
cfi_negate_ra_state
stp x29, x30, [sp, -16]!
cfi_adjust_cfa_offset (16)
cfi_rel_offset (x29, 0)
cfi_rel_offset (x30, 8)
mov x29, sp
/* Clear ZA state of SME. */
/* The calling convention of __libc_arm_za_disable allows to do
this thus allowing to avoid saving to and reading from stack.
As a result we also don't need to sign the return address and
check it after returning because it is not stored to stack. */
mov x13, x30
cfi_register (x30, x13)
bl __libc_arm_za_disable
ldp x29, x30, [sp], 16
cfi_adjust_cfa_offset (-16)
cfi_restore (x29)
cfi_restore (x30)
autiasp
cfi_negate_ra_state
mov x30, x13
cfi_register (x13, x30)
/* Restore the general purpose registers. */
mov x0, x9
cfi_def_cfa (x0, 0)