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x86: Handle unknown Intel processor with default tuning

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Enable default tuning for unknown Intel processor.

Tested on x86, no regression.

Co-Authored-By: H.J. Lu <hjl.tools@gmail.com>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
This commit is contained in:
Sunil K Pandey
2025-04-11 08:52:52 -07:00
parent d18213c699
commit 9f0deff558
1 changed files with 142 additions and 143 deletions
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113
sysdeps/x86/cpu-features.c
View File

@@ -502,8 +502,8 @@ _Static_assert (((index_arch_Fast_Unaligned_Load
"Incorrect index_arch_Fast_Unaligned_Load");
/* Intel Family-6 microarch list. */
enum
/* Intel microarch list. */
enum intel_microarch
{
/* Atom processors. */
INTEL_ATOM_BONNELL,
@@ -555,7 +555,7 @@ enum
INTEL_UNKNOWN,
};
static unsigned int
static enum intel_microarch
intel_get_fam6_microarch (unsigned int model,
__attribute__ ((unused)) unsigned int stepping)
{
@@ -764,11 +764,59 @@ init_cpu_features (struct cpu_features *cpu_features)
cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
&= ~bit_arch_Avoid_Non_Temporal_Memset;
enum intel_microarch microarch = INTEL_UNKNOWN;
if (family == 0x06)
{
model += extended_model;
unsigned int microarch
= intel_get_fam6_microarch (model, stepping);
microarch = intel_get_fam6_microarch (model, stepping);
/* Disable TSX on some processors to avoid TSX on kernels that
weren't updated with the latest microcode package (which
disables broken feature by default). */
switch (microarch)
{
default:
break;
case INTEL_BIGCORE_SKYLAKE_AVX512:
/* 0x55 (Skylake-avx512) && stepping <= 5 disable TSX. */
if (stepping <= 5)
goto disable_tsx;
break;
case INTEL_BIGCORE_KABYLAKE:
/* NB: Although the errata documents that for model == 0x8e
(kabylake skylake client), only 0xb stepping or lower are
impacted, the intention of the errata was to disable TSX on
all client processors on all steppings. Include 0xc
stepping which is an Intel Core i7-8665U, a client mobile
processor. */
if (stepping > 0xc)
break;
/* Fall through. */
case INTEL_BIGCORE_SKYLAKE:
/* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
processors listed in:
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
*/
disable_tsx:
CPU_FEATURE_UNSET (cpu_features, HLE);
CPU_FEATURE_UNSET (cpu_features, RTM);
CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT);
break;
case INTEL_BIGCORE_HASWELL:
/* Xeon E7 v3 (model == 0x3f) with stepping >= 4 has working
TSX. Haswell also includes other model numbers that have
working TSX. */
if (model == 0x3f && stepping >= 4)
break;
CPU_FEATURE_UNSET (cpu_features, RTM);
break;
}
}
switch (microarch)
{
@@ -822,8 +870,8 @@ init_cpu_features (struct cpu_features *cpu_features)
/* Bigcore/Default Tuning. */
default:
default_tuning:
/* Unknown family 0x06 processors. Assuming this is one
of Core i3/i5/i7 processors if AVX is available. */
/* Unknown Intel processors. Assuming this is one of Core
i3/i5/i7 processors if AVX is available. */
if (!CPU_FEATURES_CPU_P (cpu_features, AVX))
break;
@@ -858,7 +906,7 @@ init_cpu_features (struct cpu_features *cpu_features)
case INTEL_BIGCORE_CANNONLAKE:
/* Benchmarks indicate non-temporal memset is not
necessarily profitable on SKX (and in some cases much
worse). This is likely unique to SKX due its it unique
worse). This is likely unique to SKX due to its unique
mesh interconnect (not present on ICX or BWD). Disable
non-temporal on all Skylake servers. */
cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
@@ -878,9 +926,6 @@ init_cpu_features (struct cpu_features *cpu_features)
case INTEL_BIGCORE_SAPPHIRERAPIDS:
case INTEL_BIGCORE_EMERALDRAPIDS:
case INTEL_BIGCORE_GRANITERAPIDS:
cpu_features->cachesize_non_temporal_divisor = 2;
goto default_tuning;
/* Default tuned Mixed (bigcore + atom SOC). */
case INTEL_MIXED_LAKEFIELD:
case INTEL_MIXED_ALDERLAKE:
@@ -888,52 +933,6 @@ init_cpu_features (struct cpu_features *cpu_features)
goto default_tuning;
}
/* Disable TSX on some processors to avoid TSX on kernels that
weren't updated with the latest microcode package (which
disables broken feature by default). */
switch (microarch)
{
case INTEL_BIGCORE_SKYLAKE_AVX512:
/* 0x55 (Skylake-avx512) && stepping <= 5 disable TSX. */
if (stepping <= 5)
goto disable_tsx;
break;
case INTEL_BIGCORE_KABYLAKE:
/* NB: Although the errata documents that for model == 0x8e
(kabylake skylake client), only 0xb stepping or lower are
impacted, the intention of the errata was to disable TSX on
all client processors on all steppings. Include 0xc
stepping which is an Intel Core i7-8665U, a client mobile
processor. */
if (stepping > 0xc)
break;
/* Fall through. */
case INTEL_BIGCORE_SKYLAKE:
/* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
processors listed in:
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
*/
disable_tsx:
CPU_FEATURE_UNSET (cpu_features, HLE);
CPU_FEATURE_UNSET (cpu_features, RTM);
CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT);
break;
case INTEL_BIGCORE_HASWELL:
/* Xeon E7 v3 (model == 0x3f) with stepping >= 4 has working
TSX. Haswell also include other model numbers that have
working TSX. */
if (model == 0x3f && stepping >= 4)
break;
CPU_FEATURE_UNSET (cpu_features, RTM);
break;
}
}
/* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
if AVX512ER is available. Don't use AVX512 to avoid lower CPU
frequency if AVX512ER isn't available. */