mirror of
https://sourceware.org/git/glibc.git
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x86: Handle unknown Intel processor with default tuning
Enable default tuning for unknown Intel processor. Tested on x86, no regression. Co-Authored-By: H.J. Lu <hjl.tools@gmail.com> Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
This commit is contained in:
Sunil K Pandey
@@ -502,8 +502,8 @@ _Static_assert (((index_arch_Fast_Unaligned_Load
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"Incorrect index_arch_Fast_Unaligned_Load");
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"Incorrect index_arch_Fast_Unaligned_Load");
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/* Intel Family-6 microarch list. */
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/* Intel microarch list. */
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enum
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enum intel_microarch
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{
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{
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/* Atom processors. */
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/* Atom processors. */
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INTEL_ATOM_BONNELL,
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INTEL_ATOM_BONNELL,
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@@ -555,7 +555,7 @@ enum
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INTEL_UNKNOWN,
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INTEL_UNKNOWN,
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};
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};
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static unsigned int
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static enum intel_microarch
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intel_get_fam6_microarch (unsigned int model,
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intel_get_fam6_microarch (unsigned int model,
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__attribute__ ((unused)) unsigned int stepping)
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__attribute__ ((unused)) unsigned int stepping)
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{
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{
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@@ -764,135 +764,20 @@ init_cpu_features (struct cpu_features *cpu_features)
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cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
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cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
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&= ~bit_arch_Avoid_Non_Temporal_Memset;
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&= ~bit_arch_Avoid_Non_Temporal_Memset;
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enum intel_microarch microarch = INTEL_UNKNOWN;
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if (family == 0x06)
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if (family == 0x06)
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{
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{
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model += extended_model;
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model += extended_model;
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unsigned int microarch
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microarch = intel_get_fam6_microarch (model, stepping);
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= intel_get_fam6_microarch (model, stepping);
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/* Disable TSX on some processors to avoid TSX on kernels that
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weren't updated with the latest microcode package (which
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disables broken feature by default). */
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switch (microarch)
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switch (microarch)
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{
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{
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/* Atom / KNL tuning. */
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case INTEL_ATOM_BONNELL:
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/* BSF is slow on Bonnell. */
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cpu_features->preferred[index_arch_Slow_BSF]
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|= bit_arch_Slow_BSF;
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break;
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/* Unaligned load versions are faster than SSSE3
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on Airmont, Silvermont, Goldmont, and Goldmont Plus. */
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case INTEL_ATOM_AIRMONT:
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case INTEL_ATOM_SILVERMONT:
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case INTEL_ATOM_GOLDMONT:
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case INTEL_ATOM_GOLDMONT_PLUS:
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/* Knights Landing. Enable Silvermont optimizations. */
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case INTEL_KNIGHTS_LANDING:
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cpu_features->preferred[index_arch_Fast_Unaligned_Load]
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|= (bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop
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| bit_arch_Slow_SSE4_2);
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break;
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case INTEL_ATOM_TREMONT:
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/* Enable rep string instructions, unaligned load, unaligned
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copy, pminub and avoid SSE 4.2 on Tremont. */
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cpu_features->preferred[index_arch_Fast_Rep_String]
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|= (bit_arch_Fast_Rep_String
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| bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop
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| bit_arch_Slow_SSE4_2);
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break;
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/*
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Default tuned Knights microarch.
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case INTEL_KNIGHTS_MILL:
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*/
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/*
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Default tuned atom microarch.
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case INTEL_ATOM_SIERRAFOREST:
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case INTEL_ATOM_GRANDRIDGE:
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case INTEL_ATOM_CLEARWATERFOREST:
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*/
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/* Bigcore/Default Tuning. */
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default:
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default:
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default_tuning:
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/* Unknown family 0x06 processors. Assuming this is one
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of Core i3/i5/i7 processors if AVX is available. */
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if (!CPU_FEATURES_CPU_P (cpu_features, AVX))
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break;
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enable_modern_features:
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/* Rep string instructions, unaligned load, unaligned copy,
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and pminub are fast on Intel Core i3, i5 and i7. */
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cpu_features->preferred[index_arch_Fast_Rep_String]
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|= (bit_arch_Fast_Rep_String
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| bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop);
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break;
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break;
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case INTEL_BIGCORE_NEHALEM:
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case INTEL_BIGCORE_WESTMERE:
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/* Older CPUs prefer non-temporal stores at lower threshold. */
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cpu_features->cachesize_non_temporal_divisor = 8;
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goto enable_modern_features;
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/* Older Bigcore microarch (smaller non-temporal store
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threshold). */
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case INTEL_BIGCORE_SANDYBRIDGE:
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case INTEL_BIGCORE_IVYBRIDGE:
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case INTEL_BIGCORE_HASWELL:
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case INTEL_BIGCORE_BROADWELL:
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cpu_features->cachesize_non_temporal_divisor = 8;
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goto default_tuning;
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/* Newer Bigcore microarch (larger non-temporal store
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threshold). */
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case INTEL_BIGCORE_SKYLAKE_AVX512:
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case INTEL_BIGCORE_CANNONLAKE:
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/* Benchmarks indicate non-temporal memset is not
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necessarily profitable on SKX (and in some cases much
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worse). This is likely unique to SKX due its it unique
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mesh interconnect (not present on ICX or BWD). Disable
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non-temporal on all Skylake servers. */
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cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
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|= bit_arch_Avoid_Non_Temporal_Memset;
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/* fallthrough */
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case INTEL_BIGCORE_COMETLAKE:
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case INTEL_BIGCORE_SKYLAKE:
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case INTEL_BIGCORE_KABYLAKE:
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case INTEL_BIGCORE_ICELAKE:
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case INTEL_BIGCORE_TIGERLAKE:
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case INTEL_BIGCORE_ROCKETLAKE:
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case INTEL_BIGCORE_RAPTORLAKE:
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case INTEL_BIGCORE_METEORLAKE:
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case INTEL_BIGCORE_LUNARLAKE:
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case INTEL_BIGCORE_ARROWLAKE:
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case INTEL_BIGCORE_PANTHERLAKE:
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case INTEL_BIGCORE_SAPPHIRERAPIDS:
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case INTEL_BIGCORE_EMERALDRAPIDS:
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case INTEL_BIGCORE_GRANITERAPIDS:
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cpu_features->cachesize_non_temporal_divisor = 2;
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goto default_tuning;
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/* Default tuned Mixed (bigcore + atom SOC). */
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case INTEL_MIXED_LAKEFIELD:
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case INTEL_MIXED_ALDERLAKE:
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cpu_features->cachesize_non_temporal_divisor = 2;
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goto default_tuning;
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}
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/* Disable TSX on some processors to avoid TSX on kernels that
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weren't updated with the latest microcode package (which
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disables broken feature by default). */
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switch (microarch)
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{
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case INTEL_BIGCORE_SKYLAKE_AVX512:
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case INTEL_BIGCORE_SKYLAKE_AVX512:
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/* 0x55 (Skylake-avx512) && stepping <= 5 disable TSX. */
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/* 0x55 (Skylake-avx512) && stepping <= 5 disable TSX. */
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if (stepping <= 5)
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if (stepping <= 5)
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@@ -901,38 +786,152 @@ init_cpu_features (struct cpu_features *cpu_features)
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case INTEL_BIGCORE_KABYLAKE:
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case INTEL_BIGCORE_KABYLAKE:
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/* NB: Although the errata documents that for model == 0x8e
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/* NB: Although the errata documents that for model == 0x8e
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(kabylake skylake client), only 0xb stepping or lower are
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(kabylake skylake client), only 0xb stepping or lower are
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impacted, the intention of the errata was to disable TSX on
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impacted, the intention of the errata was to disable TSX on
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all client processors on all steppings. Include 0xc
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all client processors on all steppings. Include 0xc
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stepping which is an Intel Core i7-8665U, a client mobile
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stepping which is an Intel Core i7-8665U, a client mobile
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processor. */
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processor. */
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if (stepping > 0xc)
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if (stepping > 0xc)
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break;
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break;
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/* Fall through. */
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/* Fall through. */
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case INTEL_BIGCORE_SKYLAKE:
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case INTEL_BIGCORE_SKYLAKE:
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/* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
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/* Disable Intel TSX and enable RTM_ALWAYS_ABORT for
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processors listed in:
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processors listed in:
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https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
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https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
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*/
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*/
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disable_tsx:
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disable_tsx:
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CPU_FEATURE_UNSET (cpu_features, HLE);
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CPU_FEATURE_UNSET (cpu_features, HLE);
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CPU_FEATURE_UNSET (cpu_features, RTM);
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CPU_FEATURE_UNSET (cpu_features, RTM);
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CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT);
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CPU_FEATURE_SET (cpu_features, RTM_ALWAYS_ABORT);
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break;
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break;
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case INTEL_BIGCORE_HASWELL:
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case INTEL_BIGCORE_HASWELL:
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/* Xeon E7 v3 (model == 0x3f) with stepping >= 4 has working
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/* Xeon E7 v3 (model == 0x3f) with stepping >= 4 has working
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TSX. Haswell also include other model numbers that have
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TSX. Haswell also includes other model numbers that have
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working TSX. */
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working TSX. */
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if (model == 0x3f && stepping >= 4)
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if (model == 0x3f && stepping >= 4)
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break;
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break;
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CPU_FEATURE_UNSET (cpu_features, RTM);
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CPU_FEATURE_UNSET (cpu_features, RTM);
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break;
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break;
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}
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}
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}
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}
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switch (microarch)
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{
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/* Atom / KNL tuning. */
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case INTEL_ATOM_BONNELL:
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/* BSF is slow on Bonnell. */
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cpu_features->preferred[index_arch_Slow_BSF]
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|= bit_arch_Slow_BSF;
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break;
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/* Unaligned load versions are faster than SSSE3
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on Airmont, Silvermont, Goldmont, and Goldmont Plus. */
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case INTEL_ATOM_AIRMONT:
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case INTEL_ATOM_SILVERMONT:
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case INTEL_ATOM_GOLDMONT:
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case INTEL_ATOM_GOLDMONT_PLUS:
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/* Knights Landing. Enable Silvermont optimizations. */
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case INTEL_KNIGHTS_LANDING:
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cpu_features->preferred[index_arch_Fast_Unaligned_Load]
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|= (bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop
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| bit_arch_Slow_SSE4_2);
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break;
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case INTEL_ATOM_TREMONT:
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/* Enable rep string instructions, unaligned load, unaligned
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copy, pminub and avoid SSE 4.2 on Tremont. */
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cpu_features->preferred[index_arch_Fast_Rep_String]
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|= (bit_arch_Fast_Rep_String
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| bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop
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| bit_arch_Slow_SSE4_2);
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break;
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/*
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Default tuned Knights microarch.
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case INTEL_KNIGHTS_MILL:
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*/
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/*
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Default tuned atom microarch.
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case INTEL_ATOM_SIERRAFOREST:
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case INTEL_ATOM_GRANDRIDGE:
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case INTEL_ATOM_CLEARWATERFOREST:
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*/
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/* Bigcore/Default Tuning. */
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default:
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default_tuning:
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/* Unknown Intel processors. Assuming this is one of Core
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i3/i5/i7 processors if AVX is available. */
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if (!CPU_FEATURES_CPU_P (cpu_features, AVX))
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break;
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enable_modern_features:
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/* Rep string instructions, unaligned load, unaligned copy,
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and pminub are fast on Intel Core i3, i5 and i7. */
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cpu_features->preferred[index_arch_Fast_Rep_String]
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|= (bit_arch_Fast_Rep_String
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| bit_arch_Fast_Unaligned_Load
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| bit_arch_Fast_Unaligned_Copy
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| bit_arch_Prefer_PMINUB_for_stringop);
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break;
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case INTEL_BIGCORE_NEHALEM:
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case INTEL_BIGCORE_WESTMERE:
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/* Older CPUs prefer non-temporal stores at lower threshold. */
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cpu_features->cachesize_non_temporal_divisor = 8;
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goto enable_modern_features;
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/* Older Bigcore microarch (smaller non-temporal store
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threshold). */
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case INTEL_BIGCORE_SANDYBRIDGE:
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case INTEL_BIGCORE_IVYBRIDGE:
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case INTEL_BIGCORE_HASWELL:
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case INTEL_BIGCORE_BROADWELL:
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cpu_features->cachesize_non_temporal_divisor = 8;
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goto default_tuning;
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/* Newer Bigcore microarch (larger non-temporal store
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threshold). */
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case INTEL_BIGCORE_SKYLAKE_AVX512:
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case INTEL_BIGCORE_CANNONLAKE:
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/* Benchmarks indicate non-temporal memset is not
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necessarily profitable on SKX (and in some cases much
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worse). This is likely unique to SKX due to its unique
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mesh interconnect (not present on ICX or BWD). Disable
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non-temporal on all Skylake servers. */
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cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
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|= bit_arch_Avoid_Non_Temporal_Memset;
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/* fallthrough */
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case INTEL_BIGCORE_COMETLAKE:
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case INTEL_BIGCORE_SKYLAKE:
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case INTEL_BIGCORE_KABYLAKE:
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case INTEL_BIGCORE_ICELAKE:
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case INTEL_BIGCORE_TIGERLAKE:
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case INTEL_BIGCORE_ROCKETLAKE:
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case INTEL_BIGCORE_RAPTORLAKE:
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case INTEL_BIGCORE_METEORLAKE:
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case INTEL_BIGCORE_LUNARLAKE:
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case INTEL_BIGCORE_ARROWLAKE:
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case INTEL_BIGCORE_PANTHERLAKE:
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case INTEL_BIGCORE_SAPPHIRERAPIDS:
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case INTEL_BIGCORE_EMERALDRAPIDS:
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case INTEL_BIGCORE_GRANITERAPIDS:
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/* Default tuned Mixed (bigcore + atom SOC). */
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case INTEL_MIXED_LAKEFIELD:
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case INTEL_MIXED_ALDERLAKE:
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cpu_features->cachesize_non_temporal_divisor = 2;
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goto default_tuning;
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}
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/* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
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/* Since AVX512ER is unique to Xeon Phi, set Prefer_No_VZEROUPPER
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if AVX512ER is available. Don't use AVX512 to avoid lower CPU
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if AVX512ER is available. Don't use AVX512 to avoid lower CPU
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Block a user