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Remove trailing whitespace.

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This commit is contained in:
Joseph Myers
2013-06-05 20:44:03 +00:00
parent 5556231db2
commit 9c84384cc1
192 changed files with 1185 additions and 991 deletions
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4
sysdeps/unix/sysv/linux/powerpc/powerpc32/setcontext.S
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@@ -51,8 +51,8 @@ versioned_symbol (libc, __setcontext, setcontext, GLIBC_2_3_4)
#if SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4)
compat_text_section
# undef __CONTEXT_FUNC_NAME
# undef __CONTEXT_FUNC_NAME
# define __CONTEXT_FUNC_NAME __novec_setcontext
# undef __CONTEXT_ENABLE_VRS

4
sysdeps/unix/sysv/linux/powerpc/powerpc32/swapcontext.S
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@@ -49,8 +49,8 @@ versioned_symbol (libc, __swapcontext, swapcontext, GLIBC_2_3_4)
#if SHLIB_COMPAT (libc, GLIBC_2_3_3, GLIBC_2_3_4)
compat_text_section
# undef __CONTEXT_FUNC_NAME
# undef __CONTEXT_FUNC_NAME
# define __CONTEXT_FUNC_NAME __novec_swapcontext
# undef __CONTEXT_ENABLE_VRS

4
sysdeps/unix/sysv/linux/powerpc/powerpc64/Versions
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@@ -12,11 +12,11 @@ libc {
readdir64; readdir64_r;
# s*
scandir64;
scandir64;
}
GLIBC_2.3.4 {
getcontext;
setcontext;
setcontext;
swapcontext;
}
GLIBC_2.17 {

6
sysdeps/unix/sysv/linux/powerpc/sys/procfs.h
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@@ -31,9 +31,9 @@
__BEGIN_DECLS
/* These definitions are normally provided by ucontext.h via
asm/sigcontext.h, asm/ptrace.h, and asm/elf.h. Otherwise we define
them here. */
/* These definitions are normally provided by ucontext.h via
asm/sigcontext.h, asm/ptrace.h, and asm/elf.h. Otherwise we define
them here. */
#if !defined __PPC64_ELF_H && !defined _ASM_POWERPC_ELF_H
#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
#define ELF_NFPREG 33 /* includes fpscr */

40
sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
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@@ -61,14 +61,14 @@ typedef struct
#else
/* For 64-bit kernels with Altivec support, a machine context is exactly
* a sigcontext. For older kernel (without Altivec) the sigcontext matches
* the mcontext upto but not including the v_regs field. For kernels that
* don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the
/* For 64-bit kernels with Altivec support, a machine context is exactly
* a sigcontext. For older kernel (without Altivec) the sigcontext matches
* the mcontext upto but not including the v_regs field. For kernels that
* don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the
* v_regs field may not exit and should not be referenced. The v_regd field
* can be refernced safely only after verifying that PPC_FEATURE_HAS_ALTIVEC
* is set in AT_HWCAP. */
/* Number of general registers. */
# define NGREG 48 /* includes r0-r31, nip, msr, lr, etc. */
# define NFPREG 33 /* includes fp0-fp31 &fpscr. */
@@ -78,7 +78,7 @@ typedef unsigned long gregset_t[NGREG];
typedef double fpregset_t[NFPREG];
/* Container for Altivec/VMX Vector Status and Control Register. Only 32-bits
but can only be copied to/from a 128-bit vector register. So we allocated
but can only be copied to/from a 128-bit vector register. So we allocated
a whole quadword speedup save/restore. */
typedef struct _libc_vscr
{
@@ -106,22 +106,22 @@ typedef struct {
gregset_t gp_regs;
fpregset_t fp_regs;
/*
* To maintain compatibility with current implementations the sigcontext is
* extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
* followed by an unstructured (vmx_reserve) field of 69 doublewords. This
* allows the array of vector registers to be quadword aligned independent of
* the alignment of the containing sigcontext or ucontext. It is the
* responsibility of the code setting the sigcontext to set this pointer to
* either NULL (if this processor does not support the VMX feature) or the
* To maintain compatibility with current implementations the sigcontext is
* extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
* followed by an unstructured (vmx_reserve) field of 69 doublewords. This
* allows the array of vector registers to be quadword aligned independent of
* the alignment of the containing sigcontext or ucontext. It is the
* responsibility of the code setting the sigcontext to set this pointer to
* either NULL (if this processor does not support the VMX feature) or the
* address of the first quadword within the allocated (vmx_reserve) area.
*
* The pointer (v_regs) of vector type (elf_vrreg_t) is essentually
* an array of 34 quadword entries. The entries with
* indexes 0-31 contain the corresponding vector registers. The entry with
* index 32 contains the vscr as the last word (offset 12) within the
* quadword. This allows the vscr to be stored as either a quadword (since
* it must be copied via a vector register to/from storage) or as a word.
* The entry with index 33 contains the vrsave as the first word (offset 0)
* The pointer (v_regs) of vector type (elf_vrreg_t) is essentually
* an array of 34 quadword entries. The entries with
* indexes 0-31 contain the corresponding vector registers. The entry with
* index 32 contains the vscr as the last word (offset 12) within the
* quadword. This allows the vscr to be stored as either a quadword (since
* it must be copied via a vector register to/from storage) or as a word.
* The entry with index 33 contains the vrsave as the first word (offset 0)
* within the quadword.
*/
vrregset_t *v_regs;