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Revert __HAVE_64B_ATOMICS configure check
The 53807741fb added a configure check
for 64-bit atomic operations that were not previously enabled on some
32-bit ABIs.
However, the NPTL semaphore code casts a sem_t to a new_sem and issues
a 64-bit atomic operation for __HAVE_64B_ATOMICS. Since sem_t has
32-bit alignment on 32-bit architectures, this prevents the use of
64-bit atomics even if the ABI supports them.
Assume 64-bit atomic support from __WORDSIZE, which maps to how glibc
defines it before the broken change. Also rename __HAVE_64B_ATOMICS
to USE_64B_ATOMICS to define better the flag meaning.
Checked on x86_64-linux-gnu and i686-linux-gnu.
Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
This commit is contained in:
@@ -117,11 +117,6 @@
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#endif
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/* This is equal to 1 iff the architecture supports 64b atomic operations. */
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#ifndef __HAVE_64B_ATOMICS
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#error Unable to determine if 64-bit atomics are present.
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#endif
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/* The following functions are a subset of the atomic operations provided by
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C11. Usually, a function named atomic_OP_MO(args) is equivalent to C11's
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atomic_OP_explicit(args, memory_order_MO); exceptions noted below. */
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@@ -129,7 +124,7 @@
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/* We require 32b atomic operations; some archs also support 64b atomic
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operations. */
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void __atomic_link_error (void);
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# if __HAVE_64B_ATOMICS == 1
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# if USE_64B_ATOMICS == 1
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# define __atomic_check_size(mem) \
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if ((sizeof (*mem) != 4) && (sizeof (*mem) != 8)) \
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__atomic_link_error ();
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@@ -142,7 +137,7 @@ void __atomic_link_error (void);
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need other atomic operations of such sizes, and restricting the support to
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loads and stores makes this easier for archs that do not have native
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support for atomic operations to less-than-word-sized data. */
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# if __HAVE_64B_ATOMICS == 1
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# if USE_64B_ATOMICS == 1
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# define __atomic_check_size_ls(mem) \
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if ((sizeof (*mem) != 1) && (sizeof (*mem) != 2) && (sizeof (*mem) != 4) \
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&& (sizeof (*mem) != 8)) \
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@@ -22,7 +22,7 @@
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#include <atomic.h>
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#include <bits/atomic_wide_counter.h>
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#if __HAVE_64B_ATOMICS
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#if USE_64B_ATOMICS
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static inline uint64_t
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__atomic_wide_counter_load_relaxed (__atomic_wide_counter *c)
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@@ -65,7 +65,7 @@ __atomic_wide_counter_fetch_xor_release (__atomic_wide_counter *c,
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return atomic_fetch_xor_release (&c->__value64, val);
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}
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#else /* !__HAVE_64B_ATOMICS */
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#else /* !USE_64B_ATOMICS */
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uint64_t __atomic_wide_counter_load_relaxed (__atomic_wide_counter *c)
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attribute_hidden;
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@@ -98,6 +98,6 @@ __atomic_wide_counter_add_relaxed (__atomic_wide_counter *c,
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__atomic_wide_counter_fetch_add_relaxed (c, val);
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}
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#endif /* !__HAVE_64B_ATOMICS */
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#endif /* !USE_64B_ATOMICS */
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#endif /* _ATOMIC_WIDE_COUNTER_H */
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