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Check the HTT bit before counting logical threads

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Skip counting logical threads for Intel processors if the HTT bit is 0
which indicates there is only a single logical processor.

	* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
	logical threads if the HTT bit is 0.
	* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
	(index_cpu_HTT): Likewise.
	(reg_HTT): Likewise.
This commit is contained in:
H.J. Lu
2016-05-19 09:09:00 -07:00
parent eb2c88c7c8
commit 7c08d791ee
3 changed files with 93 additions and 76 deletions
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8
ChangeLog
View File

@ -1,3 +1,11 @@
2016-05-19 H.J. Lu <hongjiu.lu@intel.com>
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
logical threads if the HTT bit is 0.
* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
(index_cpu_HTT): Likewise.
(reg_HTT): Likewise.
2016-05-19 H.J. Lu <hongjiu.lu@intel.com> 2016-05-19 H.J. Lu <hongjiu.lu@intel.com>
[BZ #20115] [BZ #20115]

10
sysdeps/x86/cacheinfo.c
View File

@ -506,6 +506,10 @@ init_cacheinfo (void)
shared = core; shared = core;
} }
/* A value of 0 for the HTT bit indicates there is only a single
logical processor. */
if (HAS_CPU_FEATURE (HTT))
{
/* Figure out the number of logical threads that share the /* Figure out the number of logical threads that share the
highest cache level. */ highest cache level. */
if (max_cpuid >= 4) if (max_cpuid >= 4)
@ -586,8 +590,9 @@ init_cacheinfo (void)
} }
else else
{ {
intel_bug_no_cache_info: intel_bug_no_cache_info:
/* Assume that all logical threads share the highest cache level. */ /* Assume that all logical threads share the highest cache
level. */
threads threads
= ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx = ((GLRO(dl_x86_cpu_features).cpuid[COMMON_CPUID_INDEX_1].ebx
@ -598,6 +603,7 @@ init_cacheinfo (void)
threads. */ threads. */
if (shared > 0 && threads > 0) if (shared > 0 && threads > 0)
shared /= threads; shared /= threads;
}
/* Account for non-inclusive L2 and L3 caches. */ /* Account for non-inclusive L2 and L3 caches. */
if (level == 3 && !inclusive_cache) if (level == 3 && !inclusive_cache)

3
sysdeps/x86/cpu-features.h
View File

@ -51,6 +51,7 @@
#define bit_cpu_POPCOUNT (1 << 23) #define bit_cpu_POPCOUNT (1 << 23)
#define bit_cpu_FMA (1 << 12) #define bit_cpu_FMA (1 << 12)
#define bit_cpu_FMA4 (1 << 16) #define bit_cpu_FMA4 (1 << 16)
#define bit_cpu_HTT (1 << 28)
/* COMMON_CPUID_INDEX_7. */ /* COMMON_CPUID_INDEX_7. */
#define bit_cpu_ERMS (1 << 9) #define bit_cpu_ERMS (1 << 9)
@ -235,6 +236,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001 # define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001
# define index_cpu_POPCOUNT COMMON_CPUID_INDEX_1 # define index_cpu_POPCOUNT COMMON_CPUID_INDEX_1
# define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1 # define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1
# define index_cpu_HTT COMMON_CPUID_INDEX_1
# define reg_CX8 edx # define reg_CX8 edx
# define reg_CMOV edx # define reg_CMOV edx
@ -252,6 +254,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define reg_FMA4 ecx # define reg_FMA4 ecx
# define reg_POPCOUNT ecx # define reg_POPCOUNT ecx
# define reg_OSXSAVE ecx # define reg_OSXSAVE ecx
# define reg_HTT edx
# define index_arch_Fast_Rep_String FEATURE_INDEX_1 # define index_arch_Fast_Rep_String FEATURE_INDEX_1
# define index_arch_Fast_Copy_Backward FEATURE_INDEX_1 # define index_arch_Fast_Copy_Backward FEATURE_INDEX_1