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arm: Consolidate atomic-machine.h and Remove ununsed atomic macros

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The libgcc provides the required support to calling the kernel
auxiliary routines for !__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4.

Reviewed-by: Wilco Dijkstra  <Wilco.Dijkstra@arm.com>
This commit is contained in:
Adhemerval Zanella
2025-09-11 10:49:35 -03:00
parent fd27081d8e
commit 5a7a9a57c2
2 changed files with 1 additions and 232 deletions
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118
sysdeps/arm/atomic-machine.h
View File

@@ -17,122 +17,6 @@
<https://www.gnu.org/licenses/>. */ <https://www.gnu.org/licenses/>. */
#define __HAVE_64B_ATOMICS 0 #define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 1
#define ATOMIC_EXCHANGE_USES_CAS 1 #define ATOMIC_EXCHANGE_USES_CAS 1
void __arm_link_error (void); #define atomic_full_barrier() __sync_synchronize ()
#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
# define atomic_full_barrier() __sync_synchronize ()
#else
# define atomic_full_barrier() __arm_assisted_full_barrier ()
#endif
/* An OS-specific atomic-machine.h file will define this macro if
the OS can provide something. If not, we'll fail to build
with a compiler that doesn't supply the operation. */
#ifndef __arm_assisted_full_barrier
# define __arm_assisted_full_barrier() __arm_link_error()
#endif
/* Use the atomic builtins provided by GCC in case the backend provides
a pattern to do this efficiently. */
#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
# define atomic_exchange_acq(mem, value) \
__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_ACQUIRE)
# define atomic_exchange_rel(mem, value) \
__atomic_val_bysize (__arch_exchange, int, mem, value, __ATOMIC_RELEASE)
/* Atomic exchange (without compare). */
# define __arch_exchange_8_int(mem, newval, model) \
(__arm_link_error (), (typeof (*mem)) 0)
# define __arch_exchange_16_int(mem, newval, model) \
(__arm_link_error (), (typeof (*mem)) 0)
# define __arch_exchange_32_int(mem, newval, model) \
__atomic_exchange_n (mem, newval, model)
# define __arch_exchange_64_int(mem, newval, model) \
(__arm_link_error (), (typeof (*mem)) 0)
/* Compare and exchange with "acquire" semantics, ie barrier after. */
# define atomic_compare_and_exchange_bool_acq(mem, new, old) \
__atomic_bool_bysize (__arch_compare_and_exchange_bool, int, \
mem, new, old, __ATOMIC_ACQUIRE)
# define atomic_compare_and_exchange_val_acq(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, __ATOMIC_ACQUIRE)
/* Compare and exchange with "release" semantics, ie barrier before. */
# define atomic_compare_and_exchange_val_rel(mem, new, old) \
__atomic_val_bysize (__arch_compare_and_exchange_val, int, \
mem, new, old, __ATOMIC_RELEASE)
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange successful. */
# define __arch_compare_and_exchange_bool_8_int(mem, newval, oldval, model) \
({__arm_link_error (); 0; })
# define __arch_compare_and_exchange_bool_16_int(mem, newval, oldval, model) \
({__arm_link_error (); 0; })
# define __arch_compare_and_exchange_bool_32_int(mem, newval, oldval, model) \
({ \
typeof (*mem) __oldval = (oldval); \
!__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
model, __ATOMIC_RELAXED); \
})
# define __arch_compare_and_exchange_bool_64_int(mem, newval, oldval, model) \
({__arm_link_error (); 0; })
# define __arch_compare_and_exchange_val_8_int(mem, newval, oldval, model) \
({__arm_link_error (); oldval; })
# define __arch_compare_and_exchange_val_16_int(mem, newval, oldval, model) \
({__arm_link_error (); oldval; })
# define __arch_compare_and_exchange_val_32_int(mem, newval, oldval, model) \
({ \
typeof (*mem) __oldval = (oldval); \
__atomic_compare_exchange_n (mem, (void *) &__oldval, newval, 0, \
model, __ATOMIC_RELAXED); \
__oldval; \
})
# define __arch_compare_and_exchange_val_64_int(mem, newval, oldval, model) \
({__arm_link_error (); oldval; })
#else
# define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
__arm_assisted_compare_and_exchange_val_32_acq ((mem), (newval), (oldval))
#endif
#ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
/* We don't support atomic operations on any non-word types.
So make them link errors. */
# define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
({ __arm_link_error (); oldval; })
# define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
({ __arm_link_error (); oldval; })
# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
({ __arm_link_error (); oldval; })
#endif
/* An OS-specific atomic-machine.h file will define this macro if
the OS can provide something. If not, we'll fail to build
with a compiler that doesn't supply the operation. */
#ifndef __arm_assisted_compare_and_exchange_val_32_acq
# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ __arm_link_error (); oldval; })
#endif

115
sysdeps/unix/sysv/linux/arm/atomic-machine.h
View File

@@ -1,115 +0,0 @@
/* Atomic operations. ARM/Linux version.
Copyright (C) 2002-2025 Free Software Foundation, Inc.
This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library. If not, see
<https://www.gnu.org/licenses/>. */
#include <stdint.h>
/* If the compiler doesn't provide a primitive, we'll use this macro
to get assistance from the kernel. */
#ifdef __thumb2__
# define __arm_assisted_full_barrier() \
__asm__ __volatile__ \
("movw\tip, #0x0fa0\n\t" \
"movt\tip, #0xffff\n\t" \
"blx\tip" \
: : : "ip", "lr", "cc", "memory");
#else
# define __arm_assisted_full_barrier() \
__asm__ __volatile__ \
("mov\tip, #0xffff0fff\n\t" \
"mov\tlr, pc\n\t" \
"add\tpc, ip, #(0xffff0fa0 - 0xffff0fff)" \
: : : "ip", "lr", "cc", "memory");
#endif
/* Atomic compare and exchange. This sequence relies on the kernel to
provide a compare and exchange operation which is atomic on the
current architecture, either via cleverness on pre-ARMv6 or via
ldrex / strex on ARMv6.
It doesn't matter what register is used for a_oldval2, but we must
specify one to work around GCC PR rtl-optimization/21223. Otherwise
it may cause a_oldval or a_tmp to be moved to a different register.
We use the union trick rather than simply using __typeof (...) in the
declarations of A_OLDVAL et al because when NEWVAL or OLDVAL is of the
form *PTR and PTR has a 'volatile ... *' type, then __typeof (*PTR) has
a 'volatile ...' type and this triggers -Wvolatile-register-var to
complain about 'register volatile ... asm ("reg")'.
We use the same union trick in the declaration of A_PTR because when
MEM is of the from *PTR and PTR has a 'const ... *' type, then __typeof
(*PTR) has a 'const ...' type and this enables the compiler to substitute
the variable with its initializer in asm statements, which may cause the
corresponding operand to appear in a different register. */
#ifdef __thumb2__
/* Thumb-2 has ldrex/strex. However it does not have barrier instructions,
so we still need to use the kernel helper. */
# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ union { __typeof (mem) a; uint32_t v; } mem_arg = { .a = (mem) }; \
union { __typeof (oldval) a; uint32_t v; } oldval_arg = { .a = (oldval) };\
union { __typeof (newval) a; uint32_t v; } newval_arg = { .a = (newval) };\
register uint32_t a_oldval asm ("r0"); \
register uint32_t a_newval asm ("r1") = newval_arg.v; \
register uint32_t a_ptr asm ("r2") = mem_arg.v; \
register uint32_t a_tmp asm ("r3"); \
register uint32_t a_oldval2 asm ("r4") = oldval_arg.v; \
__asm__ __volatile__ \
("0:\tldr\t%[tmp],[%[ptr]]\n\t" \
"cmp\t%[tmp], %[old2]\n\t" \
"bne\t1f\n\t" \
"mov\t%[old], %[old2]\n\t" \
"movw\t%[tmp], #0x0fc0\n\t" \
"movt\t%[tmp], #0xffff\n\t" \
"blx\t%[tmp]\n\t" \
"bcc\t0b\n\t" \
"mov\t%[tmp], %[old2]\n\t" \
"1:" \
: [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp) \
: [new] "r" (a_newval), [ptr] "r" (a_ptr), \
[old2] "r" (a_oldval2) \
: "ip", "lr", "cc", "memory"); \
(__typeof (oldval)) a_tmp; })
#else
# define __arm_assisted_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ union { __typeof (mem) a; uint32_t v; } mem_arg = { .a = (mem) }; \
union { __typeof (oldval) a; uint32_t v; } oldval_arg = { .a = (oldval) };\
union { __typeof (newval) a; uint32_t v; } newval_arg = { .a = (newval) };\
register uint32_t a_oldval asm ("r0"); \
register uint32_t a_newval asm ("r1") = newval_arg.v; \
register uint32_t a_ptr asm ("r2") = mem_arg.v; \
register uint32_t a_tmp asm ("r3"); \
register uint32_t a_oldval2 asm ("r4") = oldval_arg.v; \
__asm__ __volatile__ \
("0:\tldr\t%[tmp],[%[ptr]]\n\t" \
"cmp\t%[tmp], %[old2]\n\t" \
"bne\t1f\n\t" \
"mov\t%[old], %[old2]\n\t" \
"mov\t%[tmp], #0xffff0fff\n\t" \
"mov\tlr, pc\n\t" \
"add\tpc, %[tmp], #(0xffff0fc0 - 0xffff0fff)\n\t" \
"bcc\t0b\n\t" \
"mov\t%[tmp], %[old2]\n\t" \
"1:" \
: [old] "=&r" (a_oldval), [tmp] "=&r" (a_tmp) \
: [new] "r" (a_newval), [ptr] "r" (a_ptr), \
[old2] "r" (a_oldval2) \
: "ip", "lr", "cc", "memory"); \
(__typeof (oldval)) a_tmp; })
#endif
#include <sysdeps/arm/atomic-machine.h>