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PowerPC floating point little-endian [8 of 15]

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http://sourceware.org/ml/libc-alpha/2013-07/msg00199.html

Corrects floating-point environment code for little-endian.

	* sysdeps/powerpc/fpu/fenv_libc.h (fenv_union_t): Replace int
	array with long long.
	* sysdeps/powerpc/fpu/e_sqrt.c (__slow_ieee754_sqrt): Adjust.
	* sysdeps/powerpc/fpu/e_sqrtf.c (__slow_ieee754_sqrtf): Adjust.
	* sysdeps/powerpc/fpu/fclrexcpt.c (__feclearexcept): Adjust.
	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Adjust.
	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Adjust.
	* sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Adjust.
	* sysdeps/powerpc/fpu/feholdexcpt.c (feholdexcept): Adjust.
	* sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Adjust.
	* sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Adjust.
	* sysdeps/powerpc/fpu/fgetexcptflg.c (__fegetexceptflag): Adjust.
	* sysdeps/powerpc/fpu/fraiseexcpt.c (__feraiseexcept): Adjust.
	* sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Adjust.
	* sysdeps/powerpc/fpu/ftestexcept.c (fetestexcept): Adjust.
This commit is contained in:
Anton Blanchard
2013-08-17 18:28:55 +09:30
committed by Alan Modra
parent 2ca85d2bbb
commit 4a28b3ca4b
15 changed files with 57 additions and 40 deletions
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6
sysdeps/powerpc/fpu/feupdateenv.c
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@@ -34,20 +34,20 @@ __feupdateenv (const fenv_t *envp)
/* Restore rounding mode and exception enable from *envp and merge
exceptions. Leave fraction rounded/inexact and FP result/CC bits
unchanged. */
new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF);
new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff);
/* If the old env has no enabled exceptions and the new env has any enabled
exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put
the hardware into "precise mode" and may cause the FPU to run slower on
some hardware. */
if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0)
(void)__fe_nomask_env ();
/* If the old env had any enabled exceptions and the new env has no enabled
exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the
FPU to run faster because it always takes the default action and can not
generate SIGFPE. */
if ((old.l[1] & _FPU_MASK_ALL) != 0 && (new.l[1] & _FPU_MASK_ALL) == 0)
if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0)
(void)__fe_mask_env ();
/* Atomically enable and raise (if appropriate) exceptions set in `new'. */