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powerpc: Enforce compiler barriers on hardware transactions

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Work around a GCC behavior with hardware transactional memory built-ins.
GCC doesn't treat the PowerPC transactional built-ins as compiler
barriers, moving instructions past the transaction boundaries and
altering their atomicity.
This commit is contained in:
Tulio Magno Quites Machado Filho
2015-12-28 12:24:43 -02:00
parent bc49a7afd3
commit 42bf1c8971
7 changed files with 58 additions and 15 deletions
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39
sysdeps/unix/sysv/linux/powerpc/htm.h
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@ -118,13 +118,44 @@
__ret; \
})
#define __builtin_tbegin(tdb) _tbegin ()
#define __builtin_tend(nested) _tend ()
#define __builtin_tabort(abortcode) _tabort (abortcode)
#define __builtin_get_texasru() _texasru ()
#define __libc_tbegin(tdb) _tbegin ()
#define __libc_tend(nested) _tend ()
#define __libc_tabort(abortcode) _tabort (abortcode)
#define __builtin_get_texasru() _texasru ()
#else
# include <htmintrin.h>
# ifdef __TM_FENCE__
/* New GCC behavior. */
# define __libc_tbegin(R) __builtin_tbegin (R);
# define __libc_tend(R) __builtin_tend (R);
# define __libc_tabort(R) __builtin_tabort (R);
# else
/* Workaround an old GCC behavior. Earlier releases of GCC 4.9 and 5.0,
didn't use to treat __builtin_tbegin, __builtin_tend and
__builtin_tabort as compiler barriers, moving instructions into and
out the transaction.
Remove this when glibc drops support for GCC 5.0. */
# define __libc_tbegin(R) \
({ __asm__ volatile("" ::: "memory"); \
unsigned int __ret = __builtin_tbegin (R); \
__asm__ volatile("" ::: "memory"); \
__ret; \
})
# define __libc_tabort(R) \
({ __asm__ volatile("" ::: "memory"); \
unsigned int __ret = __builtin_tabort (R); \
__asm__ volatile("" ::: "memory"); \
__ret; \
})
# define __libc_tend(R) \
({ __asm__ volatile("" ::: "memory"); \
unsigned int __ret = __builtin_tend (R); \
__asm__ volatile("" ::: "memory"); \
__ret; \
})
# endif /* __TM_FENCE__ */
#endif /* __HTM__ */
#endif /* __ASSEMBLER__ */