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Update.
1998-09-13 18:04 Geoff Keating <geoffk@ozemail.com.au> * sysdeps/powerpc/dl-machine.c (PPC_DCBST,PPC_SYNC,PPC_ISYNC,PPC_ICBI): Don't mark asm `volatile'. (__elf_machine_runtime_setup): Clear the last partial block in the PLT from the data cache too. Assume it isn't in the instruction cache yet. (__elf_machine_fixup_plt): Clear the modified address from the caches.
This commit is contained in:
@ -1,3 +1,11 @@
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1998-09-13 18:04 Geoff Keating <geoffk@ozemail.com.au>
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* sysdeps/powerpc/dl-machine.c (PPC_DCBST,PPC_SYNC,PPC_ISYNC,PPC_ICBI):
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Don't mark asm `volatile'.
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(__elf_machine_runtime_setup): Clear the last partial block in the PLT
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from the data cache too. Assume it isn't in the instruction cache yet.
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(__elf_machine_fixup_plt): Clear the modified address from the caches.
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1998-09-12 Mark Kettenis <kettenis@phys.uva.nl>
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1998-09-12 Mark Kettenis <kettenis@phys.uva.nl>
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* sysdeps/generic/segfault.c (install_handler): Install signal
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* sysdeps/generic/segfault.c (install_handler): Install signal
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@ -63,10 +63,10 @@
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#define OPCODE_SLWI(ra,rs,sh) OPCODE_RLWINM(ra,rs,sh,0,31-sh)
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#define OPCODE_SLWI(ra,rs,sh) OPCODE_RLWINM(ra,rs,sh,0,31-sh)
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#define PPC_DCBST(where) asm volatile ("dcbst 0,%0" : : "r"(where))
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#define PPC_DCBST(where) asm ("dcbst 0,%0" : : "r"(where) : "memory")
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#define PPC_SYNC asm volatile ("sync")
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#define PPC_SYNC asm ("sync" : : : "memory")
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#define PPC_ISYNC asm volatile ("sync; isync")
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#define PPC_ISYNC asm volatile ("sync; isync" : : : "memory")
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#define PPC_ICBI(where) asm volatile ("icbi 0,%0" : : "r"(where))
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#define PPC_ICBI(where) asm ("icbi 0,%0" : : "r"(where) : "memory")
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#define PPC_DIE asm volatile ("tweq 0,0")
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#define PPC_DIE asm volatile ("tweq 0,0")
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/* Use this when you've modified some code, but it won't be in the
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/* Use this when you've modified some code, but it won't be in the
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@ -242,7 +242,9 @@ __elf_machine_runtime_setup (struct link_map *map, int lazy, int profile)
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need to write the changes from the data cache to a
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need to write the changes from the data cache to a
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second-level unified cache, then make sure that stale data in
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second-level unified cache, then make sure that stale data in
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the instruction cache is removed. (In a multiprocessor
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the instruction cache is removed. (In a multiprocessor
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system, the effect is more complex.)
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system, the effect is more complex.) Most of the PLT shouldn't
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be in the instruction cache, but there may be a little overlap
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at the start and the end.
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Assumes the cache line size is at least 32 bytes, or at least
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Assumes the cache line size is at least 32 bytes, or at least
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that dcbst and icbi apply to 32-byte lines. At present, all
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that dcbst and icbi apply to 32-byte lines. At present, all
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@ -251,9 +253,10 @@ __elf_machine_runtime_setup (struct link_map *map, int lazy, int profile)
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size_modified = lazy ? rel_offset_words : PLT_INITIAL_ENTRY_WORDS;
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size_modified = lazy ? rel_offset_words : PLT_INITIAL_ENTRY_WORDS;
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for (i = 0; i < size_modified; i+=8)
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for (i = 0; i < size_modified; i+=8)
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PPC_DCBST (plt + i);
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PPC_DCBST (plt + i);
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PPC_DCBST (plt + size_modified-1);
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PPC_SYNC;
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PPC_SYNC;
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for (i = 0; i < size_modified; i+=8)
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PPC_ICBI (plt);
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PPC_ICBI (plt + i);
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PPC_ICBI (plt + size_modified-1);
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PPC_ISYNC;
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PPC_ISYNC;
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}
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}
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@ -319,6 +322,7 @@ __elf_machine_fixup_plt(struct link_map *map, const Elf32_Rela *reloc,
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+ 1
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+ 1
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- PLT_LONGBRANCH_ENTRY_WORDS
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- PLT_LONGBRANCH_ENTRY_WORDS
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+ PLT_INITIAL_ENTRY_WORDS)));
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+ PLT_INITIAL_ENTRY_WORDS)));
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reloc_addr += 1; /* This is the modified address. */
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}
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}
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}
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}
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MODIFIED_CODE (reloc_addr);
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MODIFIED_CODE (reloc_addr);
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