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[AArch64] Add ifunc support for Ares

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Add Ares to the midr_el0 list and support ifunc dispatch.  Since Ares
supports 2 128-bit loads/stores, use Neon registers for memcpy by
selecting __memcpy_falkor by default (we should rename this to
__memcpy_simd or similar).

	* manual/tunables.texi (glibc.cpu.name): Add ares tunable.
	* sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
	__memcpy_falkor for ares.
	* sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
	Add new define.
	* sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
	Add ares cpu.
This commit is contained in:
Wilco Dijkstra
2018-12-19 18:28:24 +00:00
committed by Szabolcs Nagy
parent 69da3c9e87
commit 02f440c1ef
5 changed files with 15 additions and 2 deletions
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10
ChangeLog
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@ -1,3 +1,13 @@
2019-01-09 Wilco Dijkstra <wdijkstr@arm.com>
* manual/tunables.texi (glibc.cpu.name): Add ares tunable.
* sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
__memcpy_falkor for ares.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
Add new define.
* sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
Add ares cpu.
2019-01-07 H.J. Lu <hongjiu.lu@intel.com> 2019-01-07 H.J. Lu <hongjiu.lu@intel.com>
[BZ #24066] [BZ #24066]

2
manual/tunables.texi
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@ -360,7 +360,7 @@ This tunable is specific to powerpc, powerpc64 and powerpc64le.
The @code{glibc.cpu.name=xxx} tunable allows the user to tell @theglibc{} to The @code{glibc.cpu.name=xxx} tunable allows the user to tell @theglibc{} to
assume that the CPU is @code{xxx} where xxx may have one of these values: assume that the CPU is @code{xxx} where xxx may have one of these values:
@code{generic}, @code{falkor}, @code{thunderxt88}, @code{thunderx2t99}, @code{generic}, @code{falkor}, @code{thunderxt88}, @code{thunderx2t99},
@code{thunderx2t99p1}. @code{thunderx2t99p1}, @code{ares}.
This tunable is specific to aarch64. This tunable is specific to aarch64.
@end deftp @end deftp

2
sysdeps/aarch64/multiarch/memcpy.c
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@ -36,7 +36,7 @@ extern __typeof (__redirect_memcpy) __memcpy_falkor attribute_hidden;
libc_ifunc (__libc_memcpy, libc_ifunc (__libc_memcpy,
(IS_THUNDERX (midr) (IS_THUNDERX (midr)
? __memcpy_thunderx ? __memcpy_thunderx
: (IS_FALKOR (midr) || IS_PHECDA (midr) : (IS_FALKOR (midr) || IS_PHECDA (midr) || IS_ARES (midr)
? __memcpy_falkor ? __memcpy_falkor
: (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr) : (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr)
? __memcpy_thunderx2 ? __memcpy_thunderx2

1
sysdeps/unix/sysv/linux/aarch64/cpu-features.c
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@ -36,6 +36,7 @@ static struct cpu_list cpu_list[] = {
{"thunderx2t99", 0x431F0AF0}, {"thunderx2t99", 0x431F0AF0},
{"thunderx2t99p1", 0x420F5160}, {"thunderx2t99p1", 0x420F5160},
{"phecda", 0x680F0000}, {"phecda", 0x680F0000},
{"ares", 0x411FD0C0},
{"generic", 0x0} {"generic", 0x0}
}; };

2
sysdeps/unix/sysv/linux/aarch64/cpu-features.h
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@ -51,6 +51,8 @@
#define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \ #define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \
&& MIDR_PARTNUM(midr) == 0x000) && MIDR_PARTNUM(midr) == 0x000)
#define IS_ARES(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
&& MIDR_PARTNUM(midr) == 0xd0c)
struct cpu_features struct cpu_features
{ {