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[AArch64] Add ifunc support for Ares

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Add Ares to the midr_el0 list and support ifunc dispatch.  Since Ares
supports 2 128-bit loads/stores, use Neon registers for memcpy by
selecting __memcpy_falkor by default (we should rename this to
__memcpy_simd or similar).

	* manual/tunables.texi (glibc.cpu.name): Add ares tunable.
	* sysdeps/aarch64/multiarch/memcpy.c (__libc_memcpy): Use
	__memcpy_falkor for ares.
	* sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_ARES):
	Add new define.
	* sysdeps/unix/sysv/linux/aarch64/cpu-features.c (cpu_list):
	Add ares cpu.
This commit is contained in:
Wilco Dijkstra
2018-12-19 18:28:24 +00:00
committed by Szabolcs Nagy
parent 69da3c9e87
commit 02f440c1ef
5 changed files with 15 additions and 2 deletions
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1
sysdeps/unix/sysv/linux/aarch64/cpu-features.c
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@ -36,6 +36,7 @@ static struct cpu_list cpu_list[] = {
{"thunderx2t99", 0x431F0AF0},
{"thunderx2t99p1", 0x420F5160},
{"phecda", 0x680F0000},
{"ares", 0x411FD0C0},
{"generic", 0x0}
};

2
sysdeps/unix/sysv/linux/aarch64/cpu-features.h
View File

@ -51,6 +51,8 @@
#define IS_PHECDA(midr) (MIDR_IMPLEMENTOR(midr) == 'h' \
&& MIDR_PARTNUM(midr) == 0x000)
#define IS_ARES(midr) (MIDR_IMPLEMENTOR(midr) == 'A' \
&& MIDR_PARTNUM(midr) == 0xd0c)
struct cpu_features
{