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Fix a minor performance regression from check-in [401c9d30e06191d9]

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FossilOrigin-Name: 76f54ee86777cbf530654323c953388ef64d0608516722d2522be6c859fa1382
This commit is contained in:
drh
2019-12-24 21:42:22 +00:00
parent c7a5ff45b9
commit b44fec68a5
3 changed files with 11 additions and 14 deletions
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10
src/vdbe.c
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@@ -2052,11 +2052,9 @@ case OP_Ge: { /* same as TK_GE, jump, in1, in3 */
sqlite3VdbeMemStringify(pIn1, encoding, 1);
testcase( (flags1&MEM_Dyn) != (pIn1->flags&MEM_Dyn) );
flags1 = (pIn1->flags & ~MEM_TypeMask) | (flags1 & MEM_TypeMask);
if( pIn1==pIn3 ) flags3 = flags1 | MEM_Str;
}
if( (flags3 & MEM_Str)==0
&& (flags3&(MEM_Int|MEM_Real|MEM_IntReal))!=0
&& pIn1!=pIn3
){
if( (flags3 & MEM_Str)==0 && (flags3&(MEM_Int|MEM_Real|MEM_IntReal))!=0 ){
testcase( pIn3->flags & MEM_Int );
testcase( pIn3->flags & MEM_Real );
testcase( pIn3->flags & MEM_IntReal );
@@ -2089,10 +2087,10 @@ compare_op:
}
/* Undo any changes made by applyAffinity() to the input registers. */
assert( (pIn1->flags & MEM_Dyn) == (flags1 & MEM_Dyn) );
pIn1->flags = flags1;
assert( (pIn3->flags & MEM_Dyn) == (flags3 & MEM_Dyn) );
pIn3->flags = flags3;
assert( (pIn1->flags & MEM_Dyn) == (flags1 & MEM_Dyn) );
pIn1->flags = flags1;
if( pOp->p5 & SQLITE_STOREP2 ){
pOut = &aMem[pOp->p2];