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83aadbeb96
Previously we had a fallback implementation that made a harmless system
call, based on the assumption that system calls must contain a memory
barrier. That shouldn't be reached on any current system, and it seems
highly likely that we can easily find out how to request explicit memory
barriers, if we've already had to find out how to do atomics on a
hypothetical new system.
Removed comments and a function name referred to a spinlock used for
fallback memory barriers, but that changed in 1b468a13, which left some
misleading words behind in a few places.
Reviewed-by: Heikki Linnakangas <hlinnaka@iki.fi>
Suggested-by: Andres Freund <andres@anarazel.de>
Discussion: https://postgr.es/m/721bf39a-ed8a-44b0-8b8e-be3bd81db748%40technowledgy.de
Discussion: https://postgr.es/m/3351991.1697728588%40sss.pgh.pa.us
74 lines
1.8 KiB
C
74 lines
1.8 KiB
C
/*-------------------------------------------------------------------------
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*
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* atomics.c
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* Non-Inline parts of the atomics implementation
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*
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* Portions Copyright (c) 2013-2024, PostgreSQL Global Development Group
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*
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*
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* IDENTIFICATION
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* src/backend/port/atomics.c
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*
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*-------------------------------------------------------------------------
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*/
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#include "postgres.h"
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#include "miscadmin.h"
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#include "port/atomics.h"
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#include "storage/spin.h"
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#ifdef PG_HAVE_ATOMIC_U64_SIMULATION
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void
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pg_atomic_init_u64_impl(volatile pg_atomic_uint64 *ptr, uint64 val_)
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{
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StaticAssertDecl(sizeof(ptr->sema) >= sizeof(slock_t),
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"size mismatch of atomic_uint64 vs slock_t");
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SpinLockInit((slock_t *) &ptr->sema);
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ptr->value = val_;
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}
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bool
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pg_atomic_compare_exchange_u64_impl(volatile pg_atomic_uint64 *ptr,
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uint64 *expected, uint64 newval)
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{
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bool ret;
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/*
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* Do atomic op under a spinlock. It might look like we could just skip
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* the cmpxchg if the lock isn't available, but that'd just emulate a
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* 'weak' compare and swap. I.e. one that allows spurious failures. Since
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* several algorithms rely on a strong variant and that is efficiently
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* implementable on most major architectures let's emulate it here as
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* well.
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*/
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SpinLockAcquire((slock_t *) &ptr->sema);
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/* perform compare/exchange logic */
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ret = ptr->value == *expected;
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*expected = ptr->value;
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if (ret)
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ptr->value = newval;
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/* and release lock */
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SpinLockRelease((slock_t *) &ptr->sema);
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return ret;
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}
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uint64
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pg_atomic_fetch_add_u64_impl(volatile pg_atomic_uint64 *ptr, int64 add_)
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{
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uint64 oldval;
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SpinLockAcquire((slock_t *) &ptr->sema);
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oldval = ptr->value;
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ptr->value += add_;
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SpinLockRelease((slock_t *) &ptr->sema);
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return oldval;
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}
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#endif /* PG_HAVE_ATOMIC_U64_SIMULATION */
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