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pgindent run for 9.5
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@@ -15,7 +15,7 @@
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/*
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* We want the functions below to be inline; but if the compiler doesn't
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* support that, fall back on providing them as regular functions. See
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* support that, fall back on providing them as regular functions. See
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* STATIC_IF_INLINE in c.h.
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*/
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#define ATOMICS_INCLUDE_DEFINITIONS
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@@ -50,6 +50,7 @@ pg_atomic_init_flag_impl(volatile pg_atomic_flag *ptr)
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"size mismatch of atomic_flag vs slock_t");
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#ifndef HAVE_SPINLOCKS
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/*
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* NB: If we're using semaphore based TAS emulation, be careful to use a
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* separate set of semaphores. Otherwise we'd get in trouble if an atomic
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@@ -73,7 +74,7 @@ pg_atomic_clear_flag_impl(volatile pg_atomic_flag *ptr)
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S_UNLOCK((slock_t *) &ptr->sema);
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}
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#endif /* PG_HAVE_ATOMIC_FLAG_SIMULATION */
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#endif /* PG_HAVE_ATOMIC_FLAG_SIMULATION */
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#ifdef PG_HAVE_ATOMIC_U32_SIMULATION
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void
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@@ -98,7 +99,8 @@ bool
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pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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uint32 *expected, uint32 newval)
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{
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bool ret;
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bool ret;
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/*
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* Do atomic op under a spinlock. It might look like we could just skip
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* the cmpxchg if the lock isn't available, but that'd just emulate a
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@@ -109,7 +111,7 @@ pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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*/
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SpinLockAcquire((slock_t *) &ptr->sema);
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/* perform compare/exchange logic*/
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/* perform compare/exchange logic */
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ret = ptr->value == *expected;
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*expected = ptr->value;
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if (ret)
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@@ -124,7 +126,8 @@ pg_atomic_compare_exchange_u32_impl(volatile pg_atomic_uint32 *ptr,
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uint32
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pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
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{
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uint32 oldval;
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uint32 oldval;
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SpinLockAcquire((slock_t *) &ptr->sema);
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oldval = ptr->value;
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ptr->value += add_;
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@@ -132,4 +135,4 @@ pg_atomic_fetch_add_u32_impl(volatile pg_atomic_uint32 *ptr, int32 add_)
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return oldval;
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}
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#endif /* PG_HAVE_ATOMIC_U32_SIMULATION */
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#endif /* PG_HAVE_ATOMIC_U32_SIMULATION */
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