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Minor modernization for README.barrier.

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Itanium is very uncommon and being discontinued.  ARM is everywhere.
Prefer ARM as an example of an architecture with weak memory ordering.
This commit is contained in:
Thomas Munro
2021-03-12 15:24:28 +13:00
parent 7bb97211a5
commit 43c6662496
1 changed files with 1 additions and 1 deletions
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src/backend/storage/lmgr/README.barrier
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@ -38,7 +38,7 @@ Surprisingly, however, the second backend could also end up with foo = 0
and bar = 1. The compiler might swap the order of the two stores performed
by the first backend, or the two loads performed by the second backend.
Even if it doesn't, on a machine with weak memory ordering (such as PowerPC
or Itanium) the CPU might choose to execute either the loads or the stores
or ARM) the CPU might choose to execute either the loads or the stores
out of order. This surprising result can lead to bugs.
A common pattern where this actually does result in a bug is when adding items