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Use a non-locking initial test in TAS_SPIN on AArch64.

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Our testing showed that this is helpful at sufficiently high
contention levels and doesn't hurt performance on smaller machines.
The new TAS_SPIN macro for AArch64 is identical to the ones added
for PPC and x86_64 (see commits bc2a050d40 and b03d196be0).

Reported-by: Salvatore Dipietro
Reviewed-by: Jingtang Zhang, Andres Freund
Tested-by: Tom Lane
Discussion: https://postgr.es/m/ZxgDEb_VpWyNZKB_%40nathan
This commit is contained in:
Nathan Bossart
2025-01-10 13:18:04 -06:00
parent 28e7a9968e
commit 3d0b4b1068
1 changed files with 11 additions and 5 deletions
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16
src/include/storage/s_lock.h
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@@ -263,18 +263,24 @@ tas(volatile slock_t *lock)
#define S_UNLOCK(lock) __sync_lock_release(lock) #define S_UNLOCK(lock) __sync_lock_release(lock)
/*
* Using an ISB instruction to delay in spinlock loops appears beneficial on
* high-core-count ARM64 processors. It seems mostly a wash for smaller gear,
* and ISB doesn't exist at all on pre-v7 ARM chips.
*/
#if defined(__aarch64__) #if defined(__aarch64__)
/*
* On ARM64, it's a win to use a non-locking test before the TAS proper. It
* may be a win on 32-bit ARM, too, but nobody's tested it yet.
*/
#define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
#define SPIN_DELAY() spin_delay() #define SPIN_DELAY() spin_delay()
static __inline__ void static __inline__ void
spin_delay(void) spin_delay(void)
{ {
/*
* Using an ISB instruction to delay in spinlock loops appears beneficial
* on high-core-count ARM64 processors. It seems mostly a wash for smaller
* gear, and ISB doesn't exist at all on pre-v7 ARM chips.
*/
__asm__ __volatile__( __asm__ __volatile__(
" isb; \n"); " isb; \n");
} }