Marko Mäkelä 709f0510e3 MDEV-19845: Adjust for Skylake based on benchmarks ...

Even though the PAUSE instruction latency was increased from
about 10 to 140 clock cycles in the Intel Skylake microarchitecture,
it seems to be optimal to reduce the amount of subsequently executed
PAUSE instructions not to 1/14, but to 1/2.

2019-07-02 17:44:05 +03:00

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