mirror of
https://github.com/esp8266/Arduino.git
synced 2025-04-21 10:26:06 +03:00
7356cd1ef1
* Heap init code improvements and updates Moved secondary heap init code to flash. External -24 IRAM, +32 IROM IRAM -76 IRAM, +64 IROM General updates to umm_init call path and DEFINES to better align with upstream. Name changes: UMM_INIT_HEAP with UMM_CHECK_INITIALIZED, umm_init_stage_2 with _umm_init_heap, and umm_init_common with umm_init_heap. Add file umm_cfgport.h to hold port-specific values. Stay focused on heap initialization only move-related defines. Improved comments. Created a wrapper function for running pre-SDK code from flash. Updated hwdt_app_entry to use it. Update umm_init with option to run from ICACHE. Added build define UMM_INIT_USE_ICACHE to move umm_init call path to flash. When used frees up 160 bytes of IRAM at a cost of 208 bytes of IROM Defaults to no change, umm_init call path will be in IRAM. * Changed default to use IROM for umm_init() and option to revert back to UMM_INIT_USE_IRAM.
294 lines
9.2 KiB
C
294 lines
9.2 KiB
C
/*
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* Copyright 2020 M Hightower
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __MMU_IRAM_H
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#define __MMU_IRAM_H
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#include <stdint.h>
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#include <c_types.h>
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#include <assert.h>
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#include <esp8266_undocumented.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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// This turns on range checking.
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#ifdef DEBUG_ESP_CORE
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#define DEBUG_ESP_MMU
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#endif
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#if defined(CORE_MOCK)
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#define ets_uart_printf(...) do {} while(false)
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#define XCHAL_INSTRAM0_VADDR 0x40000000
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#define XCHAL_INSTRAM1_VADDR 0x40100000
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#define XCHAL_INSTROM0_VADDR 0x40200000
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#else
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#include <sys/config.h> // For config/core-isa.h
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/*
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Cautiously use XCHAL_..._VADDR values where possible.
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While XCHAL_..._VADDR values in core-isa.h may define the Xtensa processor
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CONFIG options, they are not always an indication of DRAM, IRAM, or ROM
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size or position in the address space.
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*/
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#endif
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/*
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* DEV_DEBUG_PRINT:
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* Debug printing macros for printing before before, during, and after
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* NONOS SDK initializes. May or maynot be safe during NONOS SDK
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* initialization. As in printing from functions called on by the SDK
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* during the SDK initialization.
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*
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#define DEV_DEBUG_PRINT
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*/
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#if defined(DEV_DEBUG_PRINT) || defined(DEBUG_ESP_MMU)
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#include <esp8266_peri.h>
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#define DBG_MMU_FLUSH(a) while((USS(a) >> USTXC) & 0xff) {}
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#if defined(DEV_DEBUG_PRINT)
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extern void set_pll(void);
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extern void dbg_set_pll(void);
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#define DBG_MMU_PRINTF(fmt, ...) \
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set_pll(); \
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uart_buff_switch(0); \
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ets_uart_printf(fmt, ##__VA_ARGS__); \
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DBG_MMU_FLUSH(0)
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#else // ! defined(DEV_DEBUG_PRINT)
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#define DBG_MMU_PRINTF(fmt, ...) ets_uart_printf(fmt, ##__VA_ARGS__)
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#endif
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#else // ! defined(DEV_DEBUG_PRINT) || defined(DEBUG_ESP_MMU)
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#define DBG_MMU_FLUSH(...) do {} while(false)
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#define DBG_MMU_PRINTF(...) do {} while(false)
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#endif // defined(DEV_DEBUG_PRINT) || defined(DEBUG_ESP_MMU)
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/*
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* This wrapper is for running code from IROM (flash) before the SDK starts.
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*
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* Wraps a `void fn(void)` call with calls to enable and disable iCACHE.
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* Allows a function that resides in IROM to run before the SDK starts.
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*
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* Do not use once the SDK has started.
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*
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* Because the SDK initialization code has not run, nearly all the SDK functions
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* are not safe to call.
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*
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* Note printing at this early stage is complicated. To gain more insight,
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* review DEV_DEBUG_PRINT build path in mmu_iram.cpp. To handle strings stored
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* in IROM, review printing method and comments in hwdt_app_entry.cpp.
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*
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*/
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void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void));
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static inline __attribute__((always_inline))
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bool mmu_is_iram(const void *addr) {
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const uintptr_t iram_start = (uintptr_t)XCHAL_INSTRAM1_VADDR;
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#ifndef MMU_IRAM_SIZE
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#if defined(__GNUC__) && !defined(CORE_MOCK)
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#warning "MMU_IRAM_SIZE was undefined, setting to 0x8000UL!"
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#endif
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#define MMU_IRAM_SIZE 0x8000ul
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#endif
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const uintptr_t iram_end = iram_start + MMU_IRAM_SIZE;
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return (iram_start <= (uintptr_t)addr && iram_end > (uintptr_t)addr);
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}
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static inline __attribute__((always_inline))
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bool mmu_is_dram(const void *addr) {
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const uintptr_t dram_start = 0x3FFE8000ul;
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// The start of the Boot ROM sits at the end of DRAM. 0x40000000ul;
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const uintptr_t dram_end = (uintptr_t)XCHAL_INSTRAM0_VADDR;
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return (dram_start <= (uintptr_t)addr && dram_end > (uintptr_t)addr);
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}
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static inline __attribute__((always_inline))
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bool mmu_is_icache(const void *addr) {
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extern void _irom0_text_end(void);
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const uintptr_t icache_start = (uintptr_t)XCHAL_INSTROM0_VADDR;
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const uintptr_t icache_end = (uintptr_t)_irom0_text_end;
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return (icache_start <= (uintptr_t)addr && icache_end > (uintptr_t)addr);
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}
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#ifdef DEBUG_ESP_MMU
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#define ASSERT_RANGE_TEST_WRITE(a) \
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if (mmu_is_iram(a) || mmu_is_dram(a)) { \
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} else { \
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DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \
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assert(("Outside of Range - Write" && false)); \
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}
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#define ASSERT_RANGE_TEST_READ(a) \
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if (mmu_is_iram(a) || mmu_is_dram(a) || mmu_is_icache(a)) { \
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} else { \
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DBG_MMU_PRINTF("\nexcvaddr: %p\n", a); \
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assert(("Outside of Range - Read" && false)); \
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}
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#else
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#define ASSERT_RANGE_TEST_WRITE(a) do {} while(false)
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#define ASSERT_RANGE_TEST_READ(a) do {} while(false)
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#endif
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/*
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* Some inlines to allow faster random access to non32bit access of iRAM or
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* iCACHE data elements. These remove the extra time and stack space that would
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* have occurred by relying on exception processing.
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*/
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static inline __attribute__((always_inline))
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uint8_t mmu_get_uint8(const void *p8) {
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ASSERT_RANGE_TEST_READ(p8);
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// https://gist.github.com/shafik/848ae25ee209f698763cffee272a58f8#how-do-we-type-pun-correctly
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// Comply with strict-aliasing rules. Using memcpy is a Standards suggested
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// method for type punning. The compiler optimizer will replace the memcpy
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// with an `l32i` instruction. Using __builtin_memcpy to ensure we get the
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// effects of the compiler optimization and not some #define version of
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// memcpy.
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void *v32 = (void *)((uintptr_t)p8 & ~(uintptr_t)3u);
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uint32_t val;
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__builtin_memcpy(&val, v32, sizeof(uint32_t));
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// Use an empty ASM to reference the 32-bit value. This will block the
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// compiler from immediately optimizing to an 8-bit or 16-bit load instruction
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// against IRAM memory. (This approach was inspired by
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// https://github.com/esp8266/Arduino/pull/7780#discussion_r548303374)
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// This issue was seen when using a constant address with the GCC 10.3
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// compiler.
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// As a general practice, I think referencing by way of Extended ASM R/W
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// output register will stop the the compiler from reloading the value later
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// as 8-bit load from IRAM.
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asm volatile ("" :"+r"(val)); // inject 32-bit dependency
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uint32_t pos = ((uintptr_t)p8 & 3u) * 8u;
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val >>= pos;
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return (uint8_t)val;
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}
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static inline __attribute__((always_inline))
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uint16_t mmu_get_uint16(const uint16_t *p16) {
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ASSERT_RANGE_TEST_READ(p16);
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void *v32 = (void *)((uintptr_t)p16 & ~(uintptr_t)0x3u);
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uint32_t val;
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__builtin_memcpy(&val, v32, sizeof(uint32_t));
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asm volatile ("" :"+r"(val));
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uint32_t pos = ((uintptr_t)p16 & 3u) * 8u;
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val >>= pos;
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return (uint16_t)val;
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}
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static inline __attribute__((always_inline))
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int16_t mmu_get_int16(const int16_t *p16) {
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ASSERT_RANGE_TEST_READ(p16);
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void *v32 = (void *)((uintptr_t)p16 & ~(uintptr_t)3u);
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uint32_t val;
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__builtin_memcpy(&val, v32, sizeof(uint32_t));
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asm volatile ("" :"+r"(val));
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uint32_t pos = ((uintptr_t)p16 & 3u) * 8u;
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val >>= pos;
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return (int16_t)val;
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}
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static inline __attribute__((always_inline))
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uint8_t mmu_set_uint8(void *p8, const uint8_t val) {
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ASSERT_RANGE_TEST_WRITE(p8);
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uint32_t pos = ((uintptr_t)p8 & 3u) * 8u;
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uint32_t sval = val << pos;
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uint32_t valmask = 0x0FFu << pos;
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void *v32 = (void *)((uintptr_t)p8 & ~(uintptr_t)3u);
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uint32_t ival;
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__builtin_memcpy(&ival, v32, sizeof(uint32_t));
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asm volatile ("" :"+r"(ival));
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ival &= (~valmask);
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ival |= sval;
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/*
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This 32-bit dependency injection does not appear to be needed with the
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current GCC 10.3; however, that could change in the future versions. Or, I
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may not have the right test for it to fail.
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*/
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asm volatile ("" :"+r"(ival));
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__builtin_memcpy(v32, &ival, sizeof(uint32_t));
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return val;
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}
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static inline __attribute__((always_inline))
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uint16_t mmu_set_uint16(uint16_t *p16, const uint16_t val) {
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ASSERT_RANGE_TEST_WRITE(p16);
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uint32_t pos = ((uintptr_t)p16 & 3u) * 8u;
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uint32_t sval = val << pos;
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uint32_t valmask = 0x0FFFFu << pos;
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void *v32 = (void *)((uintptr_t)p16 & ~(uintptr_t)3u);
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uint32_t ival;
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__builtin_memcpy(&ival, v32, sizeof(uint32_t));
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asm volatile ("" :"+r"(ival));
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ival &= (~valmask);
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ival |= sval;
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asm volatile ("" :"+r"(ival));
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__builtin_memcpy(v32, &ival, sizeof(uint32_t));
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return val;
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}
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static inline __attribute__((always_inline))
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int16_t mmu_set_int16(int16_t *p16, const int16_t val) {
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ASSERT_RANGE_TEST_WRITE(p16);
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uint32_t sval = (uint16_t)val;
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uint32_t pos = ((uintptr_t)p16 & 3u) * 8u;
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sval <<= pos;
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uint32_t valmask = 0x0FFFFu << pos;
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void *v32 = (void *)((uintptr_t)p16 & ~(uintptr_t)3u);
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uint32_t ival;
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__builtin_memcpy(&ival, v32, sizeof(uint32_t));
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asm volatile ("" :"+r"(ival));
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ival &= (~valmask);
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ival |= sval;
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asm volatile ("" :"+r"(ival));
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__builtin_memcpy(v32, &ival, sizeof(uint32_t));
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return val;
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}
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#if (MMU_IRAM_SIZE > 32*1024) && !defined(MMU_SEC_HEAP)
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#define MMU_SEC_HEAP mmu_sec_heap()
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#define MMU_SEC_HEAP_SIZE mmu_sec_heap_size()
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static inline __attribute__((always_inline))
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void *mmu_sec_heap(void) {
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extern void _text_end(void);
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uintptr_t sec_heap = (uintptr_t)_text_end + (uintptr_t)32u;
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return (void *)(sec_heap &= ~(uintptr_t)7u);
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}
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static inline __attribute__((always_inline))
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size_t mmu_sec_heap_size(void) {
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return (size_t)0xC000ul - ((uintptr_t)mmu_sec_heap() - (uintptr_t)XCHAL_INSTRAM1_VADDR);
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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