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bd5b5d35f0
zero buffers so they are mute in case of underflow add non-blocking write (returns false if DMA was full) add checks for full and empty DMA add some comments to the header
246 lines
8.5 KiB
C
246 lines
8.5 KiB
C
/*
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i2s.c - Software I2S library for esp8266
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Code taken and reworked from espessif's I2S example
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Copyright (c) 2015 Hristo Gochkov. All rights reserved.
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This file is part of the esp8266 core for Arduino environment.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "Arduino.h"
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#include "osapi.h"
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#include "ets_sys.h"
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#include "i2s_reg.h"
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#include "i2s.h"
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extern void ets_wdt_enable(void);
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extern void ets_wdt_disable(void);
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#define SLC_BUF_CNT (8) //Number of buffers in the I2S circular buffer
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#define SLC_BUF_LEN (64) //Length of one buffer, in 32-bit words.
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//We use a queue to keep track of the DMA buffers that are empty. The ISR will push buffers to the back of the queue,
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//the mp3 decode will pull them from the front and fill them. For ease, the queue will contain *pointers* to the DMA
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//buffers, not the data itself. The queue depth is one smaller than the amount of buffers we have, because there's
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//always a buffer that is being used by the DMA subsystem *right now* and we don't want to be able to write to that
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//simultaneously.
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struct slc_queue_item {
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uint32 blocksize:12;
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uint32 datalen:12;
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uint32 unused:5;
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uint32 sub_sof:1;
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uint32 eof:1;
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uint32 owner:1;
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uint32 buf_ptr;
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uint32 next_link_ptr;
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};
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static uint32_t i2s_slc_queue[SLC_BUF_CNT-1];
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static uint8_t i2s_slc_queue_len;
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static uint32_t *i2s_slc_buf_pntr[SLC_BUF_CNT]; //Pointer to the I2S DMA buffer data
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static struct slc_queue_item i2s_slc_items[SLC_BUF_CNT]; //I2S DMA buffer descriptors
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static uint32_t *i2s_curr_slc_buf=NULL;//current buffer for writing
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static int i2s_curr_slc_buf_pos=0; //position in the current buffer
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bool ICACHE_FLASH_ATTR i2s_is_full(){
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return (i2s_curr_slc_buf_pos==SLC_BUF_LEN || i2s_curr_slc_buf==NULL) && (i2s_slc_queue_len == 0);
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}
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bool ICACHE_FLASH_ATTR i2s_is_empty(){
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return (i2s_slc_queue_len >= SLC_BUF_CNT-1);
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}
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uint32_t ICACHE_FLASH_ATTR i2s_slc_queue_next_item(){ //pop the top off the queue
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uint8_t i;
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uint32_t item = i2s_slc_queue[0];
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i2s_slc_queue_len--;
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for(i=0;i<i2s_slc_queue_len;i++)
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i2s_slc_queue[i] = i2s_slc_queue[i+1];
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return item;
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}
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//This routine is called as soon as the DMA routine has something to tell us. All we
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//handle here is the RX_EOF_INT status, which indicate the DMA has sent a buffer whose
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//descriptor has the 'EOF' field set to 1.
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void ICACHE_FLASH_ATTR i2s_slc_isr(void) {
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uint32_t slc_intr_status = SLCIS;
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SLCIC = 0xFFFFFFFF;
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if (slc_intr_status & SLCIRXEOF) {
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ETS_SLC_INTR_DISABLE();
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struct slc_queue_item *finished_item = (struct slc_queue_item*)SLCRXEDA;
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memset((void *)finished_item->buf_ptr, 0x00, SLC_BUF_LEN * 4);//zero the buffer so it is mute in case of underflow
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if (i2s_slc_queue_len >= SLC_BUF_CNT-1) { //All buffers are empty. This means we have an underflow
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i2s_slc_queue_next_item(); //free space for finished_item
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}
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i2s_slc_queue[i2s_slc_queue_len++] = finished_item->buf_ptr;
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ETS_SLC_INTR_ENABLE();
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}
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}
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void ICACHE_FLASH_ATTR i2s_slc_begin(){
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i2s_slc_queue_len = 0;
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int x, y;
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for (x=0; x<SLC_BUF_CNT; x++) {
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i2s_slc_buf_pntr[x] = malloc(SLC_BUF_LEN*4);
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for (y=0; y<SLC_BUF_LEN; y++) i2s_slc_buf_pntr[x][y] = 0;
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i2s_slc_items[x].unused = 0;
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i2s_slc_items[x].owner = 1;
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i2s_slc_items[x].eof = 1;
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i2s_slc_items[x].sub_sof = 0;
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i2s_slc_items[x].datalen = SLC_BUF_LEN*4;
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i2s_slc_items[x].blocksize = SLC_BUF_LEN*4;
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i2s_slc_items[x].buf_ptr = (uint32_t)&i2s_slc_buf_pntr[x][0];
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i2s_slc_items[x].next_link_ptr = (int)((x<(SLC_BUF_CNT-1))?(&i2s_slc_items[x+1]):(&i2s_slc_items[0]));
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}
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ETS_SLC_INTR_DISABLE();
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SLCC0 |= SLCRXLR | SLCTXLR;
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SLCC0 &= ~(SLCRXLR | SLCTXLR);
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SLCIC = 0xFFFFFFFF;
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//Configure DMA
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SLCC0 &= ~(SLCMM << SLCM); //clear DMA MODE
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SLCC0 |= (1 << SLCM); //set DMA MODE to 1
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SLCRXDC |= SLCBINR | SLCBTNR; //enable INFOR_NO_REPLACE and TOKEN_NO_REPLACE
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SLCRXDC &= ~(SLCBRXFE | SLCBRXEM | SLCBRXFM); //disable RX_FILL, RX_EOF_MODE and RX_FILL_MODE
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//Feed DMA the 1st buffer desc addr
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//To send data to the I2S subsystem, counter-intuitively we use the RXLINK part, not the TXLINK as you might
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//expect. The TXLINK part still needs a valid DMA descriptor, even if it's unused: the DMA engine will throw
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//an error at us otherwise. Just feed it any random descriptor.
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SLCTXL &= ~(SLCTXLAM << SLCTXLA); // clear TX descriptor address
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SLCTXL |= (uint32)&i2s_slc_items[1] << SLCTXLA; //set TX descriptor address. any random desc is OK, we don't use TX but it needs to be valid
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SLCRXL &= ~(SLCRXLAM << SLCRXLA); // clear RX descriptor address
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SLCRXL |= (uint32)&i2s_slc_items[0] << SLCRXLA; //set RX descriptor address
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ETS_SLC_INTR_ATTACH(i2s_slc_isr, NULL);
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SLCIE = SLCIRXEOF; //Enable only for RX EOF interrupt
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ETS_SLC_INTR_ENABLE();
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//Start transmission
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SLCTXL |= SLCTXLS;
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SLCRXL |= SLCRXLS;
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}
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void ICACHE_FLASH_ATTR i2s_slc_end(){
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ETS_SLC_INTR_DISABLE();
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SLCIC = 0xFFFFFFFF;
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SLCIE = 0;
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SLCTXL &= ~(SLCTXLAM << SLCTXLA); // clear TX descriptor address
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SLCRXL &= ~(SLCRXLAM << SLCRXLA); // clear RX descriptor address
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}
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//This routine pushes a single, 32-bit sample to the I2S buffers. Call this at (on average)
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//at least the current sample rate. You can also call it quicker: it will suspend the calling
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//thread if the buffer is full and resume when there's room again.
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bool ICACHE_FLASH_ATTR i2s_write_sample(uint32_t sample) {
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if (i2s_curr_slc_buf_pos==SLC_BUF_LEN || i2s_curr_slc_buf==NULL) {
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if(i2s_slc_queue_len == 0){
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while(1){
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if(i2s_slc_queue_len > 0){
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break;
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} else {
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ets_wdt_disable();
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ets_wdt_enable();
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}
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}
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}
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ETS_SLC_INTR_DISABLE();
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i2s_curr_slc_buf = (uint32_t *)i2s_slc_queue_next_item();
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ETS_SLC_INTR_ENABLE();
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i2s_curr_slc_buf_pos=0;
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}
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i2s_curr_slc_buf[i2s_curr_slc_buf_pos++]=sample;
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return true;
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}
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bool ICACHE_FLASH_ATTR i2s_write_sample_nb(uint32_t sample) {
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if (i2s_curr_slc_buf_pos==SLC_BUF_LEN || i2s_curr_slc_buf==NULL) {
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if(i2s_slc_queue_len == 0){
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return false;
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}
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ETS_SLC_INTR_DISABLE();
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i2s_curr_slc_buf = (uint32_t *)i2s_slc_queue_next_item();
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ETS_SLC_INTR_ENABLE();
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i2s_curr_slc_buf_pos=0;
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}
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i2s_curr_slc_buf[i2s_curr_slc_buf_pos++]=sample;
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return true;
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}
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bool ICACHE_FLASH_ATTR i2s_write_lr(int16_t left, int16_t right){
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int sample = right & 0xFFFF;
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sample = sample << 16;
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sample |= left & 0xFFFF;
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return i2s_write_sample(sample);
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}
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// END DMA
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// =========
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// START I2S
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static uint32_t _i2s_sample_rate;
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void ICACHE_FLASH_ATTR i2s_set_rate(uint32_t rate){ //Rate in HZ
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if(rate == _i2s_sample_rate) return;
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_i2s_sample_rate = rate;
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uint32_t i2s_clock_div = (I2SBASEFREQ/(_i2s_sample_rate*32)) & I2SCDM;
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uint8_t i2s_bck_div = (I2SBASEFREQ/(_i2s_sample_rate*i2s_clock_div*2)) & I2SBDM;
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//os_printf("Rate %u Div %u Bck %u Frq %u\n", _i2s_sample_rate, i2s_clock_div, i2s_bck_div, I2SBASEFREQ/(i2s_clock_div*i2s_bck_div*2));
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//!trans master, !bits mod, rece slave mod, rece msb shift, right first, msb right
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I2SC &= ~(I2STSM | (I2SBMM << I2SBM) | (I2SBDM << I2SBD) | (I2SCDM << I2SCD));
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I2SC |= I2SRF | I2SMR | I2SRSM | I2SRMS | ((i2s_bck_div-1) << I2SBD) | ((i2s_clock_div-1) << I2SCD);
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}
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void ICACHE_FLASH_ATTR i2s_begin(){
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_i2s_sample_rate = 0;
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i2s_slc_begin();
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pinMode(2, FUNCTION_1); //I2SO_WS (LRCK)
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pinMode(3, FUNCTION_1); //I2SO_DATA (SDIN)
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pinMode(15, FUNCTION_1); //I2SO_BCK (SCLK)
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I2S_CLK_ENABLE();
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I2SIC = 0x3F;
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I2SIE = 0;
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//Reset I2S
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I2SC &= ~(I2SRST);
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I2SC |= I2SRST;
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I2SC &= ~(I2SRST);
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I2SFC &= ~(I2SDE | (I2STXFMM << I2STXFM) | (I2SRXFMM << I2SRXFM)); //Set RX/TX FIFO_MOD=0 and disable DMA (FIFO only)
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I2SFC |= I2SDE; //Enable DMA
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I2SCC &= ~((I2STXCMM << I2STXCM) | (I2SRXCMM << I2SRXCM)); //Set RX/TX CHAN_MOD=0
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i2s_set_rate(44100);
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I2SC |= I2STXS; //Start transmission
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}
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void ICACHE_FLASH_ATTR i2s_end(){
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i2s_slc_end();
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pinMode(2, INPUT);
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pinMode(3, INPUT);
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pinMode(15, INPUT);
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}
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