Christopher Pascoe cc0a8ead55 Always arm the "TX FIFO Empty" interrupt after we write into _tx_buffer. ...

This avoids a race where the interrupt handler detects an empty _tx_buffer
just before we write data into it.

Note that commit d6f62943d4b511e7d5fe6147096c8979890416f5 works around
this race when data is continually added to _tx_buffer in the hung state.
We revert that change here as the race should no longer occur.

Testing performed:
 - set UART_CONF1.txfifo_empty_thrhd=0x70 (which exacerbates the issue)
 - generate a ~240 byte burst of data, sent in back-to-back Serial1.write(, 4)
   calls, optionally followed by a Serial1.flush()
Test results:
 - before this change, observe occasional unsent data and hang in flush()
   (if used).
 - after this change, data is sent as expected.

2015-12-06 21:03:05 -08:00

..

esp8266

Always arm the "TX FIFO Empty" interrupt after we write into _tx_buffer.

2015-12-06 21:03:05 -08:00