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* Allow unaligned input/output to SPI::transferBytes Fixes #4967 Support any alignment of input and output pointers and transfer lengths in SPI::transferBytes. Use 32-bit transfers and FIFO as much as possible. * Refactor misaligned transfer, avoid RMW to FIFO The SPI FIFO can't properly do RMW (i.e. bytewise updates) because when you read the FIFO you are actually reading the SPI read data, not what was written into the write FIFO. Refactor the transferBytes to take account of this. For aligned input and outputs, perform as before (but handle non-x4 sizes properly). For misaligned inputs, if it's unidirectional then do bytewise until the direction data pointer is aligned and then do 32b accesses. Fod bidirectional and misaligned inputs, copy the output data to an aligned buffer, do the transfer, then copy the read back data from temp aligned buffer to the real input buffer. * Fix comments, clean condition checks, save stack Add more comments and adjust naming to be more informative in transferBytes_ and *aligned_. Save 64bytes of stack in double misaligned case. * Optimize misaligned transfers, reduce code size On any misaligned input or output, always use a temp buffer. No need for special casing and bytewise ::transfer(). This should be faster as bytewise ::transfer involves a significant number of IO register accesses and setup. Thanks to @devyte for the suggestion.