mirror of
https://github.com/esp8266/Arduino.git
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126 lines
3.3 KiB
C++
126 lines
3.3 KiB
C++
/*
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core_esp8266_features.h - list of features integrated in to ESP8266 core
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Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.
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This file is part of the esp8266 core for Arduino environment.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CORE_ESP8266_FEATURES_H
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#define CORE_ESP8266_FEATURES_H
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#define CORE_HAS_LIBB64
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#define CORE_HAS_BASE64_CLASS
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#define CORE_HAS_CXA_GUARD
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#define CORE_HAS_UMM
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#define WIFI_HAS_EVENT_CALLBACK
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#include <stdlib.h> // malloc()
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#include <stddef.h> // size_t
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#include <stdint.h>
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#ifndef __STRINGIFY
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#define __STRINGIFY(a) #a
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#endif
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// these low level routines provide a replacement for SREG interrupt save that AVR uses
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// but are esp8266 specific. A normal use pattern is like
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//
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//{
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// uint32_t savedPS = xt_rsil(1); // this routine will allow level 2 and above
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// // do work here
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// xt_wsr_ps(savedPS); // restore the state
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//}
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//
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// level (0-15), interrupts of the given level and above will be active
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// level 15 will disable ALL interrupts,
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// level 0 will enable ALL interrupts,
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//
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#ifndef CORE_MOCK
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#define xt_rsil(level) (__extension__({uint32_t state; __asm__ __volatile__("rsil %0," __STRINGIFY(level) : "=a" (state) :: "memory"); state;}))
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#define xt_wsr_ps(state) __asm__ __volatile__("wsr %0,ps; isync" :: "a" (state) : "memory")
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inline uint32_t esp_get_cycle_count() __attribute__((always_inline));
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inline uint32_t esp_get_cycle_count() {
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uint32_t ccount;
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__asm__ __volatile__("rsr %0,ccount":"=a"(ccount));
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return ccount;
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}
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inline uint32_t esp_get_program_counter() __attribute__((always_inline));
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inline uint32_t esp_get_program_counter() {
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uint32_t pc;
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__asm__ __volatile__("movi %0, ." : "=r" (pc) : : ); // ©earlephilhower
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return pc;
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}
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#else // CORE_MOCK
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inline uint32_t esp_get_program_counter() { return 0; }
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#endif // CORE_MOCK
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// Tools for preloading code into the flash cache
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#define PRECACHE_ATTR __attribute__((optimize("no-reorder-blocks"))) \
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__attribute__((noinline))
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#define PRECACHE_START(tag) \
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precache(NULL,(uint8_t *)&&_precache_end_##tag - (uint8_t*)&&_precache_start_##tag); \
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_precache_start_##tag:
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#define PRECACHE_END(tag) \
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_precache_end_##tag:
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#ifdef __cplusplus
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extern "C" {
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#endif
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void precache(void *f, uint32_t bytes);
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unsigned long millis(void);
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unsigned long micros(void);
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uint64_t micros64(void);
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void delay(unsigned long);
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void delayMicroseconds(unsigned int us);
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#if defined(F_CPU) || defined(CORE_MOCK)
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#ifdef __cplusplus
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constexpr
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#else
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inline
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#endif
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int esp_get_cpu_freq_mhz()
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{
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return F_CPU / 1000000L;
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}
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#else
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inline int esp_get_cpu_freq_mhz()
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{
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return system_get_cpu_freq();
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif // CORE_ESP8266_FEATURES_H
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