Maurice Ribble 7f0b9d1be9 Rx fifo latency fix (#4328) ...

* Flush the rx fifo when checking available bytes in fifo.  This gives a more correct result rather than waiting until either the fifo is full or until a serial rx timeout occurs.

* When rx_avaiable is checked return rx_buffer plus rx_fifo.  Then during rx_read and rx_peek functions copy over the data in the fifo as needed.

* Clean up early out case.

* Set the rx full fifo ISR to trigger a little sooner.  This makes the uart rx isr more robust in cases where the ISR can't trigger very fast

2018-03-08 12:16:14 -03:00

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esp8266

Rx fifo latency fix (#4328)

2018-03-08 12:16:14 -03:00