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65579d2908
No need to issue a MEMW instrunction per load from each cache line.
Only once after the last load is sufficient.
MEMW ensures that all previous load, store, acquire, release, prefetch,
and cache instructions perform before performing any subsequent load,
store, acquire, release, prefetch, or cache instructions.
-- MEMW (Memory Wait), 6. Instruction Descriptions,
Xtensa ISA Reference Manual (p.409)
67 lines
2.3 KiB
C++
67 lines
2.3 KiB
C++
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/*
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core_esp8266_features.cpp
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Copyright (c) 2019 Mike Nix. All rights reserved.
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This file is part of the esp8266 core for Arduino environment.
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This library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
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version 2.1 of the License, or (at your option) any later version.
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This library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
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License along with this library; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <eagle_soc.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* precache()
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* pre-loads flash data into the flash cache
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* if f==0, preloads instructions starting at the address we were called from.
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* otherwise preloads flash at the given address.
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* All preloads are word aligned.
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*/
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void precache(void *f, uint32_t bytes) {
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// Size of a cache page in bytes. We only need to read one word per
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// page (ie 1 word in 8) for this to work.
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#define CACHE_PAGE_SIZE 32
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uint32_t lines = (bytes / CACHE_PAGE_SIZE) + 2;
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uint32_t *p = (uint32_t*)((uint32_t)(f ? f : __builtin_return_address(0)) & ~0x03);
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do {
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__asm__ volatile ("" : : "r"(*p)); // guarantee that the value of *p will be in some register (forced load)
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p += CACHE_PAGE_SIZE / sizeof(uint32_t);
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} while (--lines);
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__sync_synchronize(); // full memory barrier, mapped to MEMW in Xtensa
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}
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/** based on efuse data, we could determine what type of chip this is
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* - https://github.com/espressif/esptool/blob/f04d34bcab29ace798d2d3800ba87020cccbbfdd/esptool.py#L1060-L1070
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* - https://github.com/espressif/ESP8266_RTOS_SDK/blob/3c055779e9793e5f082afff63a011d6615e73639/components/esp8266/include/esp8266/efuse_register.h#L20-L21
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*/
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bool esp_is_8285() {
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const uint32_t data[] {
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READ_PERI_REG(0x3ff00050), // aka MAC0
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READ_PERI_REG(0x3ff00058), // aka CHIPID
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};
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return ((data[0] & (1 << 4)) > 0)
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|| ((data[1] & (1 << 16)) > 0);
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}
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#ifdef __cplusplus
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}
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#endif
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