mirror of
https://github.com/esp8266/Arduino.git
synced 2025-07-24 19:42:27 +03:00
f2c7256539
* Add flash for vtable destination, make it default Add an option for placing vtables in flash to complement the existing iram and heap options. "make flash" Now that there is a way to change it, move to vtables in flash as default as only users with interrupts which use vtables require the vtable to be in RAM. For those users, if the tables are small enough they can put them in IRAM and save heap space for their app. If not, then the vtables can be placed in HEAP which supports much larger tables. * Add VTable menu, FLASH as default, remove Makefile Convert from manual "make" operated app.ld creation to runtime creation whose options are selected from the build menu. Use a prelink recipe to create the output app.ld file each run, without need for any special tools. Update the boards.txt.py script to generate this new config.
191 lines
5.0 KiB
C
191 lines
5.0 KiB
C
/* This linker script generated from xt-genldscripts.tpp for LSP . */
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/* Linker Script for ld -N */
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PHDRS
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{
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dport0_0_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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dram0_0_bss_phdr PT_LOAD;
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iram1_0_phdr PT_LOAD;
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irom0_0_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(call_user_start)
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EXTERN(_DebugExceptionVector)
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EXTERN(_DoubleExceptionVector)
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EXTERN(_KernelExceptionVector)
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EXTERN(_NMIExceptionVector)
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EXTERN(_UserExceptionVector)
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EXTERN(core_version)
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PROVIDE(_memmap_vecbase_reset = 0x40000000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00000110;
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_memmap_cacheattr_wt_base = 0x00000110;
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_memmap_cacheattr_bp_base = 0x00000220;
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_memmap_cacheattr_unused_mask = 0xFFFFF00F;
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_memmap_cacheattr_wb_trapnull = 0x2222211F;
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_memmap_cacheattr_wba_trapnull = 0x2222211F;
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_memmap_cacheattr_wbna_trapnull = 0x2222211F;
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_memmap_cacheattr_wt_trapnull = 0x2222211F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFFFFF11F;
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_memmap_cacheattr_wt_strict = 0xFFFFF11F;
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_memmap_cacheattr_bp_strict = 0xFFFFF22F;
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_memmap_cacheattr_wb_allvalid = 0x22222112;
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_memmap_cacheattr_wt_allvalid = 0x22222112;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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SECTIONS
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{
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.dport0.rodata : ALIGN(4)
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{
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_dport0_rodata_start = ABSOLUTE(.);
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*(.dport0.rodata)
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*(.dport.rodata)
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_dport0_rodata_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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.dport0.literal : ALIGN(4)
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{
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_dport0_literal_start = ABSOLUTE(.);
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*(.dport0.literal)
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*(.dport.literal)
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_dport0_literal_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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.dport0.data : ALIGN(4)
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{
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_dport0_data_start = ABSOLUTE(.);
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*(.dport0.data)
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*(.dport.data)
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_dport0_data_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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.data : ALIGN(4)
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{
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_data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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. = ALIGN(4);
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_Pri_3_HandlerAddress = ABSOLUTE(.);
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_data_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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#ifdef VTABLES_IN_DRAM
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#include "eagle.app.v6.common.ld.vtables.h"
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#endif
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.irom0.text : ALIGN(4)
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{
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_irom0_text_start = ABSOLUTE(.);
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*(.ver_number)
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*.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, EXCLUDE_FILE (umm_malloc.c.o) .text* )
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*.cpp.o(.literal*, .text*)
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#ifdef VTABLES_IN_FLASH
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*(.rodata._ZTV*) /* C++ vtables */
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#endif
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*libc.a:(.literal .text .literal.* .text.*)
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*libm.a:(.literal .text .literal.* .text.*)
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*libgcc.a:_umoddi3.o(.literal .text)
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*libgcc.a:_udivdi3.o(.literal .text)
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*libsmartconfig.a:(.literal .text .literal.* .text.*)
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*libstdc++.a:(.literal .text .literal.* .text.*)
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*liblwip_gcc.a:(.literal .text .literal.* .text.*)
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*liblwip_src.a:(.literal .text .literal.* .text.*)
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*liblwip2.a:(.literal .text .literal.* .text.*)
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*liblwip2_1460.a:(.literal .text .literal.* .text.*)
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*libaxtls.a:(.literal .text .literal.* .text.*)
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*libat.a:(.literal.* .text.*)
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*libcrypto.a:(.literal.* .text.*)
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*libespnow.a:(.literal.* .text.*)
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*libjson.a:(.literal.* .text.*)
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*liblwip.a:(.literal.* .text.*)
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*libmesh.a:(.literal.* .text.*)
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*libnet80211.a:(.literal.* .text.*)
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*libsmartconfig.a:(.literal.* .text.*)
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*libssl.a:(.literal.* .text.*)
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*libupgrade.a:(.literal.* .text.*)
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*libwpa.a:(.literal.* .text.*)
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*libwpa2.a:(.literal.* .text.*)
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*libwps.a:(.literal.* .text.*)
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*(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text .irom.text.*)
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_irom0_text_end = ABSOLUTE(.);
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_flash_code_end = ABSOLUTE(.);
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} >irom0_0_seg :irom0_0_phdr
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.text : ALIGN(4)
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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*(.UserEnter.text)
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. = ALIGN(16);
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*(.DebugExceptionVector.text)
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. = ALIGN(16);
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*(.NMIExceptionVector.text)
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. = ALIGN(16);
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*(.KernelExceptionVector.text)
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LONG(0)
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LONG(0)
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LONG(0)
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LONG(0)
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. = ALIGN(16);
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*(.UserExceptionVector.text)
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LONG(0)
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LONG(0)
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LONG(0)
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LONG(0)
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. = ALIGN(16);
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*(.DoubleExceptionVector.text)
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LONG(0)
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LONG(0)
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LONG(0)
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LONG(0)
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. = ALIGN (16);
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*(.entry.text)
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*(.init.literal)
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*(.init)
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*.cpp.o(.iram.text)
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*.c.o(.iram.text)
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#ifdef VTABLES_IN_IRAM
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*(.rodata._ZTV*) /* C++ vtables */
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#endif
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_text_end = ABSOLUTE(.);
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_etext = .;
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} >iram1_0_seg :iram1_0_phdr
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#if defined(VTABLES_IN_IRAM) || defined(VTABLES_IN_FLASH)
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#include "eagle.app.v6.common.ld.vtables.h"
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#endif
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.lit4 : ALIGN(4)
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{
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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} >iram1_0_seg :iram1_0_phdr
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}
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/* get ROM code address */
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INCLUDE "../ld/eagle.rom.addr.v6.ld"
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