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0203dea024
Added replacement for the Boot ROM `_xtos_set_exception_handler` to handle installing our replacement `_xtos_c_wrapper_handler`. Simplified install in the non 32-bit exception module to make use of the improved `_xtos_set_exception_handler` Reorganized and improved comments.
214 lines
7.3 KiB
ArmAsm
214 lines
7.3 KiB
ArmAsm
// exc-c-wrapper-handler.S, this is a reduced version of the original file at
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// https://github.com/qca/open-ath9k-htc-firmware/blob/master/sboot/magpie_1_1/sboot/athos/src/xtos/exc-c-wrapper-handler.S#L62-L67
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//
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// exc-c-wrapper-handler.S - General Exception Handler that Dispatches C Handlers
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// Copyright (c) 2002-2004, 2006-2007, 2010 Tensilica Inc.
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//
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// Permission is hereby granted, free of charge, to any person obtaining
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// a copy of this software and associated documentation files (the
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// "Software"), to deal in the Software without restriction, including
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// without limitation the rights to use, copy, modify, merge, publish,
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// distribute, sublicense, and/or sell copies of the Software, and to
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// permit persons to whom the Software is furnished to do so, subject to
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// the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/specreg.h>
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// #include "xtos-internal.h"
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// #ifdef SIMULATOR
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// #include <xtensa/simcall.h>
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// #endif
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#include "xtruntime-frames.h"
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/////////////////////////////////////////////////////////////////////////////
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//
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// Verified that the ASM generated UEXC_xxx values match, the corresponding
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// values in `struct __exception_frame` used in the "C" code.
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//
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#include "esp8266_undocumented.h"
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.if (UEXC_pc != VERIFY_UEXC_pc)
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.err
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.endif
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.if (UEXC_ps != VERIFY_UEXC_ps)
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.err
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.endif
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.if (UEXC_sar != VERIFY_UEXC_sar)
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.err
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.endif
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.if (UEXC_vpri != VERIFY_UEXC_vpri)
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.err
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.endif
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.if (UEXC_a0 != VERIFY_UEXC_a0)
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.err
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.endif
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.if (UEXC_a2 != VERIFY_UEXC_a2)
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.err
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.endif
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.if (UEXC_a3 != VERIFY_UEXC_a3)
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.err
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.endif
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.if (UEXC_a4 != VERIFY_UEXC_a4)
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.err
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.endif
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.if (UEXC_a5 != VERIFY_UEXC_a5)
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.err
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.endif
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.if (UEXC_a6 != VERIFY_UEXC_a6)
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.err
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.endif
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.if (UEXC_a7 != VERIFY_UEXC_a7)
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.err
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.endif
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.if (UEXC_a8 != VERIFY_UEXC_a8)
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.err
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.endif
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.if (UEXC_a9 != VERIFY_UEXC_a9)
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.err
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.endif
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.if (UEXC_a10 != VERIFY_UEXC_a10)
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.err
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.endif
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.if (UEXC_a11 != VERIFY_UEXC_a11)
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.err
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.endif
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.if (UEXC_a12 != VERIFY_UEXC_a12)
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.err
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.endif
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.if (UEXC_a13 != VERIFY_UEXC_a13)
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.err
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.endif
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.if (UEXC_a14 != VERIFY_UEXC_a14)
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.err
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.endif
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.if (UEXC_a15 != VERIFY_UEXC_a15)
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.err
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.endif
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.if (UEXC_exccause != VERIFY_UEXC_exccause)
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.err
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.endif
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.if (UserFrameSize != VERIFY_UserFrameSize)
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.err
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.endif
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.if (UserFrameTotalSize != VERIFY_UserFrameTotalSize)
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.err
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.endif
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///////////////////////////////////////////////////////////////////////////////
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/*
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* This is the general exception assembly-level handler that dispatches C handlers.
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*/
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.section .iram.text
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.align 4
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.literal_position
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.global _xtos_c_wrapper_handler
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_xtos_c_wrapper_handler:
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// HERE: a2, a3, a4 have been saved to exception stack frame allocated with a1 (sp).
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// a2 contains EXCCAUSE.
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s32i a5, a1, UEXC_a5 // a5 will get clobbered by ENTRY after the pseudo-CALL4
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// (a4..a15 spilled as needed; save if modified)
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//NOTA: Possible future improvement:
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// keep interrupts disabled until we get into the handler, such that
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// we don't have to save other critical state such as EXCVADDR here.
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// @mhightower83 - This promise was broken by an "rsil a13, 0" below.
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//rsr a3, EXCVADDR
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s32i a2, a1, UEXC_exccause
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//s32i a3, a1, UEXC_excvaddr
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// Set PS fields:
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// EXCM = 0
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// WOE = __XTENSA_CALL0_ABI__ ? 0 : 1
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// UM = 1
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// INTLEVEL = EXCM_LEVEL = 1
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// CALLINC = __XTENSA_CALL0_ABI__ ? 0 : 1
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// OWB = 0 (really, a dont care if !__XTENSA_CALL0_ABI__)
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// movi a2, 0x23 // 0x21, PS_UM|PS_INTLEVEL(XCHAL_EXCM_LEVEL)
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// @mhightower83 - use INTLEVEL 15 instead of 3 for Arduino like interrupt support??
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movi a2, 0x2F // 0x21, PS_UM|PS_INTLEVEL(15)
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rsr a3, EPC_1
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// @mhightower83 - I assume PS.EXCM was set and now is being cleared, thus
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// allowing new exceptions and interrupts within PS_INTLEVEL to be possible.
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// We have set INTLEVEL to 15 to block any possible interrupts.
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xsr a2, PS
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// HERE: window overflows enabled, but NOT SAFE because we're not quite
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// in a valid windowed context (haven't restored a1 yet...);
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// so don't cause any (keep to a0..a3) until we've saved critical state and restored a1:
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// NOTE: MUST SAVE EPC1 before causing any overflows, because overflows corrupt EPC1.
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s32i a3, a1, UEXC_pc
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s32i a2, a1, UEXC_ps
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s32i a0, a1, UEXC_a0 // save the rest of the registers
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s32i a6, a1, UEXC_a6
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s32i a7, a1, UEXC_a7
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s32i a8, a1, UEXC_a8
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s32i a9, a1, UEXC_a9
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s32i a10, a1, UEXC_a10
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s32i a11, a1, UEXC_a11
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s32i a12, a1, UEXC_a12
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s32i a13, a1, UEXC_a13
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s32i a14, a1, UEXC_a14
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s32i a15, a1, UEXC_a15
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rsync // wait for WSR to PS to complete
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rsr a12, SAR
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// @mhightower83 - I think, after the next instruction, we have the potential of
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// losing UEXC_excvaddr. Which the earlier comment said we need to preserve for
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// the exception handler. We keep interrupts off when calling the "C" exception
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// handler. For the use cases that I am looking at, this is a must. If there are
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// future use cases that need interrupts enabled, those "C" exception handlers
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// can turn them on.
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//
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// rsil a13, 0
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movi a13, _xtos_c_handler_table // &table
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l32i a15, a1, UEXC_exccause // arg2: exccause
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s32i a12, a1, UEXC_sar
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addx4 a12, a15, a13 // a12 = table[exccause]
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l32i a12, a12, 0 // ...
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mov a2, a1 // arg1: exception parameters
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mov a3, a15 // arg2: exccause
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beqz a12, 1f // null handler => skip call
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callx0 a12 // call C exception handler for this exception
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1:
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// Now exit the handler.
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// Restore special registers
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l32i a14, a1, UEXC_sar
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// load early - saves two cycles - @mhightower83
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movi a0, _xtos_return_from_exc
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// @mhightower83 - For compatibility with Arduino interrupt architecture, we
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// keep interrupts 100% disabled.
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// /*
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// * Disable interrupts while returning from the pseudo-CALL setup above,
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// * for the same reason they were disabled while doing the pseudo-CALL:
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// * this sequence restores SP such that it doesn't reflect the allocation
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// * of the exception stack frame, which we still need to return from
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// * the exception.
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// */
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// rsil a12, 1 // XCHAL_EXCM_LEVEL
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rsil a12, 15 // All levels blocked.
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wsr a14, SAR
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jx a0
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/* FIXME: what about _GeneralException ? */
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.size _xtos_c_wrapper_handler, . - _xtos_c_wrapper_handler
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