Richard Allen 00815f2db4 Manually manage FIFO volatility ...

Replace volatile with properly placed __sync_synchronize

SPI1W0 is volatile, but when writing multiple words
to the FIFO (which is really just a piece of SRAM),
we don't need to worry about write ordering. We only
need worry about write ordering such that all FIFO
words are written completely before HSPI is told to
use FIFO by setting SPI1CMD |= SPIBUSY;

2017-06-06 23:23:09 -05:00

..

keywords.txt

Add WIP SPI library

2015-01-21 04:19:04 +03:00

library.properties

Add libraries categories

2015-11-02 19:23:26 +01:00

SPI.cpp

Manually manage FIFO volatility

2017-06-06 23:23:09 -05:00

SPI.h

Issue #1062: Implement support for HSPI overlap mode.

2017-05-08 03:04:11 -05:00