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9 Commits

Author SHA1 Message Date
twischer
83f5f29cfd Support to reboot into UART download mode (#7854)
without any external wiring.

This patch introduces the new method
Esp.rebootIntoUartDownloadMode()

When the user calls this method the ESP8266 reboots into the UART
download mode. In this mode the user can use esptool.py to flash a new
firmware file. The following command was used to test it:
$ esptool.py --before no_reset --after soft_reset --chip esp8266 \
    --port /dev/ttyUSB0 --baud 460800 write_flash 0x0 firmware.bin

The implementation is based on the original implementation in the
boot ROM. Some parts of the original implementation can be found in
[1]. This patch is a squashed and simplified version of [2]. The non
squashed version might be helpful in case of debugging issues.

[1] https://github.com/twischer/xtensa-subjects/blob/master/reversed/bootrom.c
[2] https://github.com/twischer/Arduino/tree/reboot_uart_download_full

Signed-off-by: Timo Wischer <twischer@freenet.de>
2021-02-17 08:25:52 -08:00
M Hightower
8b662ed3b3 PoC cache configuration control (#7060)
* PoC cache configuration control

Expaned boards.txt.py to allow new MMU options and create revised .ld's
Updated eboot to pass 48K IRAM segments.
Added Cache_Read_Enable intercept to modify call for 16K ICACHE
Update platform.txt to pass new mmu options through to compiler and linker preprocessor.
Added quick example: esp8266/MMU48K

* Style corrections
Added MMU_ qualifier to new defines.
Moved changes into their own file.
Don't know how to fix platformio issue.

* Added detailed description for Cache_Read_Enable.
Updated tools/sizes.py to report correct IRAM size and indicate ICACHE size.
Merged in earlephilhower's work on unaligned exception. Refactored and added
support for store operations and changed the name to be more closely aligned
with its function. Improved crash reporting path.

* Style and MMU_SEC_HEAP corrections.

* Improved asm register usage.
Added some inline functions to aid in byte and short access to iRAM.
 * only byte read has been tested
Updated .ld file to work better with platform.io; however, I am still
missing some steps, so platformio will still fail.

* Interesting glitch in boards.txt after github merge. A new board in
master was missing new additions added by boards.txt.py in the PR.
Which the CI flags when it rebuilds boards.txt.

* Support for 2nd Heap, excess IRAM, through umm_malloc.

Adapted changes to umm_malloc, Esp.cpp, StackThunk.cpp,
WiFiClientSecureBearSSL.cpp, and virtualmem.ino to irammem.ino from
@earlephilhower PR #6994.

Reworked umm_malloc to use context pointers instead of copy context.
umm_malloc now supports allocations from IRAM. Added class
HeapSelectIram, ... to aid in selecting alternate heaps,
modeled after class InterruptLock.
Restrict alloc request from ISRs to DRAM.

Never ending improvements to debug printing.

Sec Heap option now pulls in free IRAM left over in the 1st 32K block.
Managed through umm_malloc with HeapSelectIram.

Updated examples.

* Post push CI cleanup.

* Cleanup part II

* Cleanup part III

* Updates to support platformio, maybe.

* Added exception C wrapper replacement.

* CI Cleanup

* CI Cleanup II

Don't know what to do with platformio it doesn't like my .S file.
ifdef out USE_ISR_SAFE_EXC_WRAPPER to block the new assemlby module
from building on platformio only.

* Changes to exc-c-wrapper-handler.S to assemble under platformio.

* For platformio, Correction to toolchain-xtensa include path.
@mcspr, Thankyou!

* Temporarily added --print-memory-usage to ld parameters for cross-checking IRAM size.

* undo change to platform.txt

* correct merge conflict. take 1

* Fixed #if... for building umm_get_oom_count. It was not building when UMM_STATS_FULL was used.

* Commented out XMC support. Compatibility issues with PoC when using 16K ICACHE.

* Corrected size.py, DRAM bracketing changed to not include ICACHE with DRAM total.

* Added additional _context for support of use of UMM_INLINE_METRICS.
Corrected some UMM_POSION missed edits.

* Changes to clear errors and warnings from toolchain 10.1

Several fixes and improvements to example MMU48K.

With the improved optimization in toolchain 10.1 The example divide by 0
exception was failing with a HWDT event instead of its exception handler.
The compiler saw the obscured divide by 0 and replaced it with a break point.

* Isolated incompatable definitions related to _xtos_set_exception_handler.
GDBSTUB definitions are different from the BootROM's.

* Update tools/platformio-build.py

Co-authored-by: Max Prokhorov <prokhorov.max@outlook.com>

* Requested changes

Changed mmu related usages of ETS_... defines to DBG_MMU_...

Cleanup in example MMU48K.ino. Removed stale memory reference macro
and mmu_status print statement. Cleanup printf '\n' to be '\r\n'.

Improved issolation of development debug prints from the rest of the debug prints.

* Corrected comment. And added missing include.

* Improve comment.

* style and comment correction

* Added draft mmu.rst file and updated index.
Updated example HeapMetric.ino to also illustrate use of IRAM
Improved comments in exc-c-wrapper-handler.S. Added insurance IRQ disable.

* Updated mmu.rst

Improved function name uniqueness for is_iram, is_dram, and is_icache by
adding prefix mmu_. Also, made them available outside of a debug build.
Made pointer precision width more specific.

Made some of the static inline functions in mmu_irm.h safe for ISRs by
setting then for always inline.

* Add a default MMU_IRAM_SIZE value for a new CI test to pass.

Extended use 'umm_heap_context_t *_context' argument in ..._core functions
and expanded its usage to reduce unnecessary repeated calls to
umm_info(NULL, false), also removed recursion from umm_info(NULL, true).

Fixed stack buffer length in umm_info_safe_printf_P and heap.cpp.

Added example for creating an IRAM reserve section.

Updated mmu.rst. Grammar and spelling corrections.

* CI appeasement

* CI appeasement with comment correction.

* Ensure SYS always runs with DRAM Heap selected.

* Add/move heap stack overflow/underflow check to Esp.cpp where the event was discarded.

* Improved comment clarity of purpose for IramReserve.ino. Clean up MMU48K.ino

* Added missing #include

* Corrected usage of warning

* CI appeasement and use #message not #pragma message

* Updated git version of eboot.elf to match build version.
Good test catch.

* Remove conditional build option USE_ISR_SAFE_EXC_WRAPPER, always install.

Use the replacement wrapper on non32xfer_exception_handler install.

Added comments to code describing some exception handling issues.

* Updated mmu.rst

* Expanded and clarified comments.

Limited access to some detailed typdefs/prototypes to .cpp
modules, to avoid future build conflicts.

Completed TODO for verifing that the "C" structure struct __exception_frame
matches the ASM version.

Fixed some typo's, code rot, and added some more cases in examaple irammem.ino.
Refactored a little and reordered printing to ease comparison between methods.

Corrected `#ifdef __cplusplus` coverage area. Cleaned up `extern "C" ...` usage.
Fixes issues with including mmu_iram.h or esp8266_undocumented.h in .c files.

* Style fixes and more cleanup

* Style fix

* Remove unnessasary IRAM_ATTR from install_non32xfer_exception_handler

Some comment tuning.

In the context of _xtos_set_exception_handler and the functions it registers,
changed to type int for exception cause type. This is also the type used by gdbstub
and some other Xtensa files I found.
2020-12-06 14:15:42 +01:00
M Hightower
831d6431bc Add typedef for putc1, fn_putc1_t. (#6550)
* Add typedef for putc1, fn_putc1_t.
Replaced relevant usage of `(void *)` with `fn_putc1_t`.
Correct usage of `ets_putc()`, returning 0, in libc_replacement.cpp
This PR assumes PR https://github.com/esp8266/Arduino/pull/6489#issue-315018841 has merged and removes `uart_buff_switch` from `umm_performance.cpp`
Updated method of defining `_rom_putc1` to be more acceptable (I hope) to the new compiler.

* Use PROVIDE to expose ROM function entry point, ets_uart_putc1.
Added comments to ets_putc() and ets_uart_putc1() to explain their
differences. Change prototype of ets_putc() to conform with fp_putc_t.
Updated _isr_safe_printf_P to use new definition, ets_uart_putc1.
2019-09-27 14:23:16 -07:00
Mike Nix
d8531cb2c4 Ets intr lock nest (#6484)
* Replace the SDK's use of ets_intr_lock/unlock with nestable versions

Testing has shown that there are several paths in the SDK that result in nested
calls to ets_intr_lock() / ets_intr_unlock() which may be a problem.

These functions also do not preserve the enabled interrupt level and may
result in code running with interrupts enabled when that is not intended.
This issue has recently been fixed in the Arduino code by using
xt_rsil() / xt_wsr_ps() but still exists in the Espressif SDK code.

This commit is intended to fix that and should be used in addition to the above.

The maximum nesting I have seen is 2 and lock/unlock calls appear to be balanced.
A max of 7 levels of nesting leaves plenty of room for that to change.

* make ets_intr_lock_stack uint16_t and behave like the original on over/underflow

The PS register is 15 bits, we should store the whole thing as xt_wsr_ps()
writes the whole thing.

Also if there is an underflow, we should make sure interrupts are enabled.
Same goes for overflow making sure interrupts are disabled, although this
is less important.

* Rename ets_intr_(un)lock_nest to ets_intr_(un)lock

This saves having to modify libmain.a, libpp.a and libnet80211.a to use the
nested versions.
Adjusts fix_sdk_libs.sh accordingly.

* Remove ets_intr_(un)lock from the rom .ld as we no longer use them

* ets_post() wrapper to preserve interrupt state

Add a wrapper around the ets_post code in rom to preserve the interrupt enable state.

Rather than modifying the SDK libs, rename ets_post in the .ld file and call the
wrapper "ets_post" to replace it.

As far as I can establish, ets_post is the only rom function in use by our code or
the SDK libs we use that causes calls to ets_intr_(un)lock.

* Add IRAM_ATTR to ets_intr_(un)lock and ets_post wrappers.

* Throw in a few comments and make ets_intr_lock_stack* static.
2019-09-10 23:59:07 -03:00
Earle F. Philhower, III
48fc8aff20 Support PIO Wl-T and Arduino -T linking properly (#6095)
The interrupt vectors in IRAM are omitted when there is a PROVIDE
statement in the linker control files when using the PIO method of
-Wl,-T<linkfile>.

Drop the PROVIDES (they're in RAM anyway and not ROM related), and
add the required "-u"s to the PIO build script.

Should have no impact on the Arduino side.

Fixes #6087
2019-05-18 12:51:27 -07:00
Ivan Grokhotkov
e04903225e sdk: update to v2.1.0-10-g509eae8 2017-10-15 01:40:10 -05:00
Ivan Grokhotkov
ae13809c81 Update SDK to 2.0.0
- Update SDK header files and libraries to SDK 2.0.0 plus 2.0.0_16_08_09
  patch
- Remove mem_manager.o from libmain.a (replaced with umm_malloc)
- Disable switch from DIO to QIO mode for certain flash chips (saves
  IRAM space)
- Add user_rf_cal_sector_set; it points to rf_init_data sector.
- Change the way rf_init_data is spoofed.
  This is now done by wrapping spi_flash_read and returning the data we
  need during startup sequence.
- Place lwip library into flash using linker script instead of section
  attributes (saves IRAM space)
2017-02-03 04:21:20 +03:00
Ivan Grokhotkov
70cf3c36ef Add missing AES table pointers (#1271, #1256) 2015-12-22 07:59:54 +03:00
Ivan Grokhotkov
870b8b9478 Move tools to platform directory 2015-05-18 16:04:30 +03:00