* Remove unnecessary XMC support from eboot
eboot is always run with the flash access speed set to 20MHz, so
there is no need for special treatment of XMC chips.
* After eboot copies the new firmware into place, verify the copy.
If the data written to flash is as expected, the line cmp:0 will be displayed
after the usual @cp:0 from eboot.
* Disable interrupts during the precached part of _SPICommand()
For some reason this was an issue during the reboot after an OTA update.
* Move the spi vendor list from Esp.h to its own header in eboot.
* Fix ifdef issue with spi_vendors.h
* Add initFlashQuirks() for any chip specific flash initialization.
Called from user_init().
* namespace experimental for initFlashQuirks()
* Slow down flash access during eboot firmware copy
Part 1 - still some work to do
* Slow down flash access during eboot firmware copy on XMC chips
Part 2 - Identify the chip type.
Note: there may still be issues with the access speed change.
This is very much experimental.
* Commit eboot.elf
Co-authored-by: Develo <deveyes@gmail.com>
Co-authored-by: Earle F. Philhower, III <earlephilhower@yahoo.com>
* Add a CRC32 over progmem and ESP.checkFlashCRC
Automatically embed a CRC32 of the program memory (including bootloader
but excluding any filesystems) in all images in unused space in the
bootloader block.
Add a call, ESP.checkFlashCRC() which returns false if the calculated
CRC doesn't match the one stored in the image (i.e. flash corruption).
Fixes#4165
* Add example that corrupts itself, comments
Show CRC checking catch a 1-bit error in program code by corrupting a
large array, and then return it to clean and verify the CRC matches once
again.
Add comments to the CRC check routine
Clean up pylint complaints on crc32bin.py
* Check linker script for CRC space in bootsector
Add an assertion in the eboot linker file to guarantee that we have at
least 8 bytes of unused space at the end of the boot sector to patch in
the CRC. If not, the eboot link will fail.
* Add note about what to do if CRC check fails
Per discussion with @d-a-v.
When the CRC check fails, you could *try* to do certain things (but may
not succeed since there is known flash corruption at that point). List
a few ideas for application authors.
* Only single, flash/ram friendly crc32() function
* Combine the CRC calc and bin generation in 1 step
Per discussion w/@mcspr, combine the CRC calculation with the binary
generation, removing the additional build step.
* Add documentation for compressed OTA, fix bug
Fixes#6923
Documents the user steps needed to do a compressed upload, and notes the
2-step process needed for deploying compressed uploads to the field for
the first time.
Fixes a bug in serial output formatting discovered by @AdrianEddy.
Adds additional contributors for uzlib, per @pfalcon.
* Update README for esptool.py, too
* Allow GZIP compressed flash updates
Modified the bootloader to be able to take stored updates in compressed
GZIP format (i.e. the output of "gzip -9 xxx.bin") and decompress them
on-the-fly to their final destination. This can work for apps and for
filesystems (when used with the 2-step update option).
Allow eboot to be built using -Os/2 optimizations by fixing some portions
which failed when any optimizations were used. Add -Wall and use data
and function sections to reduce size. Use -Os to minimize size.
Remove obsolete esptool-ck calls to build a .ROM image, we don't use it.
Move all uninitted variables to RAM from IRAM, allowing 8-bit access.
Hook in @d-a-v and @pfalcon's uzlib port to actually do the
decompression. Do not use any CRC checking which saves space. Since we
have overwritten all of flash by the time we know id the CRC matches,
there's nothing we could have done anyway.
Adjust the Updater class to support GZIP files and not attempt to patch
them.
Bootloader builds to 0xd90 out of 0xfff bytes.
* Add @d-a-v's patch for httpupdate
https://github.com/esp8266/Arduino/pull/6820#pullrequestreview-326541014
* Update uzlib to point to pfalcon++
For now, because there are some self-test failures with @d-a-v's esp8266
branch (whose cool new features we don't actually use in eboot now)
start with pfalcon's 2.9 release and add the 2 patches (clcidx to code
from IRAM/RODATA, and the Windows test file renaming) needed to build
and run successfully.
* Add (c) notice for uzlib to README
The eboot command was cleared from the rtc mem before the firmware copy
making it possible for a power failure during an OTA update to brick the
esp until the firmware was loaded via USB because of a partial firmware
copy that would never be restarted.
Moving the eboot_command_clear to after the copy ensures that any partial
copy is restarted at next power on.
