mirror of
https://github.com/esp8266/Arduino.git
synced 2025-07-29 05:21:37 +03:00
Importing my changes
This commit is contained in:
ficeto
@ -1,94 +0,0 @@
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#include "include/HSPI.h"
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#include "include/spi_register.h"
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#define __min(a,b) ((a > b) ? (b):(a))
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void HSPI::begin()
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||||
{
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spi_fifo = (uint32_t*)SPI_FLASH_C0(hspi_port);
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//bit9 of PERIPHS_IO_MUX should be cleared when HSPI clock doesn't equal CPU clock
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WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105);
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, FUNC_HSPIQ_MISO); // gpio12
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_HSPID_MOSI); // gpio13
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, FUNC_HSPI_CLK); // gpio14
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// SPI clock=CPU clock/8
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WRITE_PERI_REG(SPI_FLASH_CLOCK(hspi_port),
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((1&SPI_CLKDIV_PRE)<<SPI_CLKDIV_PRE_S)|
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((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
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((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
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((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
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uint32_t regvalue = SPI_FLASH_DOUT;
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regvalue |= SPI_DOUTDIN | SPI_CK_I_EDGE;
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regvalue &= ~(BIT2 | SPI_FLASH_USR_ADDR | SPI_FLASH_USR_DUMMY | SPI_FLASH_USR_DIN | SPI_USR_COMMAND);
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WRITE_PERI_REG(SPI_FLASH_USER(hspi_port), regvalue);
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WRITE_PERI_REG(SPI_FLASH_CTRL1(hspi_port), 0);
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}
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void HSPI::end()
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{
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}
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void HSPI::setDataMode(uint8_t dataMode)
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{
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}
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void HSPI::setBitOrder(uint8_t bitOrder)
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{
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if (!bitOrder)
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{
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WRITE_PERI_REG(SPI_FLASH_CTRL(hspi_port),
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READ_PERI_REG(SPI_FLASH_CTRL(hspi_port)) & (~(SPI_WR_BIT_ODER | SPI_RD_BIT_ODER)));
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}
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else
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{
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WRITE_PERI_REG(SPI_FLASH_CTRL(hspi_port),
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READ_PERI_REG(SPI_FLASH_CTRL(hspi_port)) | (SPI_WR_BIT_ODER | SPI_RD_BIT_ODER));
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}
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}
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void HSPI::setClockDivider(uint8_t clockDiv)
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{
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uint32_t clock_reg_val = (((clockDiv - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) |
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((1 & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
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((0 & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) |
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((1 & SPI_CLKCNT_L) << SPI_CLKCNT_L_S);
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WRITE_PERI_REG(SPI_FLASH_CLOCK(hspi_port), clock_reg_val);
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}
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uint8_t HSPI::transfer(uint8_t data)
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{
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hspi_wait_ready();
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hspi_prepare_txrx(1);
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*spi_fifo = data;
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hspi_start_tx();
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hspi_wait_ready();
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return *spi_fifo & 0xFF;
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}
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uint16_t HSPI::transfer16(uint16_t data)
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{
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hspi_wait_ready();
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hspi_prepare_txrx(2);
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*spi_fifo = data;
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hspi_start_tx();
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hspi_wait_ready();
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return *spi_fifo & 0xFFFF;
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}
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void HSPI::transfer(void *buf, size_t count)
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{
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uint32_t *_data = (uint32_t*)buf;
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uint8_t i;
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uint8_t words_to_send = __min((count + 3) / 4, hspi_fifo_size);
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hspi_prepare_tx(count);
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for(i = 0; i < words_to_send;i++)
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spi_fifo[i] = _data[i];
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hspi_start_tx();
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}
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@ -1,91 +1,78 @@
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/*
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* Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>
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* Copyright (c) 2014 by Paul Stoffregen <paul@pjrc.com> (Transaction API)
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* Copyright (c) 2014 by Matthijs Kooijman <matthijs@stdin.nl> (SPISettings AVR)
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* SPI Master library for arduino.
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||||
*
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||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of either the GNU General Public License version 2
|
||||
* or the GNU Lesser General Public License version 2.1, both as
|
||||
* published by the Free Software Foundation.
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||||
*/
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/*
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SPI.cpp - SPI library for esp8266
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Copyright (c) 2015 Hristo Gochkov. All rights reserved.
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This file is part of the esp8266 core for Arduino environment.
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||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
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#include "SPI.h"
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#include "include/HSPI.h"
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SPIClass SPI;
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SPIClass::SPIClass(){}
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SPIClass::SPIClass()
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: _impl(0)
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{
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void SPIClass::begin(){
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pinMode(SCK, SPECIAL);
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pinMode(MISO, SPECIAL);
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pinMode(MOSI, SPECIAL);
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GPMUX = 0x105;
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SPI1C = 0;
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SPI1CLK = SPI_CLOCK_DIV16;//1MHz
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SPI1U = SPIUMOSI | SPIUDUPLEX | SPIUSSE;
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SPI1U1 = (7 << SPILMOSI) | (7 << SPILMISO);
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SPI1C1 = 0;
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}
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void SPIClass::begin()
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{
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if (_impl)
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end();
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_impl = new HSPI;
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_impl->begin();
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void SPIClass::end() {
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pinMode(SCK, INPUT);
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pinMode(MISO, INPUT);
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pinMode(MOSI, INPUT);
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}
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void SPIClass::end()
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{
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if (!_impl)
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return;
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_impl->end();
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delete _impl;
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_impl = 0;
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void SPIClass::beginTransaction(SPISettings settings) {
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setClockDivider(settings._clock);
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setBitOrder(settings._bitOrder);
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setDataMode(settings._dataMode);
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}
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void SPIClass::beginTransaction(SPISettings settings)
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{
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if (!_impl)
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return;
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_impl->setBitOrder(settings._bitOrder);
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_impl->setDataMode(settings._dataMode);
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_impl->setClockDivider(settings._clock);
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void SPIClass::endTransaction() {}
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void SPIClass::setDataMode(uint8_t dataMode) {
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}
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uint8_t SPIClass::transfer(uint8_t data)
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{
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if (!_impl)
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return 0;
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return _impl->transfer(data);
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void SPIClass::setBitOrder(uint8_t bitOrder) {
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if (bitOrder == MSBFIRST){
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SPI1C &= ~(SPICWBO | SPICRBO);
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} else {
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SPI1C |= (SPICWBO | SPICRBO);
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}
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}
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uint16_t SPIClass::transfer16(uint16_t data)
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{
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if (!_impl)
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return 0;
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return _impl->transfer16(data);
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void SPIClass::setClockDivider(uint32_t clockDiv) {
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SPI1CLK = clockDiv;
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}
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void SPIClass::transfer(void *buf, size_t count)
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{
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if (!_impl)
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return;
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_impl->transfer(buf, count);
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}
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void SPIClass::setBitOrder(uint8_t bitOrder)
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{
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if (!_impl)
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return;
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_impl->setBitOrder(bitOrder);
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}
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void SPIClass::setDataMode(uint8_t dataMode)
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{
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if (!_impl)
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return;
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_impl->setDataMode(dataMode);
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}
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void SPIClass::setClockDivider(uint8_t clockDiv)
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{
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if (!_impl)
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return;
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_impl->setClockDivider(clockDiv);
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uint8_t SPIClass::transfer(uint8_t data) {
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while(SPI1CMD & SPIBUSY);
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SPI1W0 = data;
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SPI1CMD |= SPIBUSY;
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while(SPI1CMD & SPIBUSY);
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return (uint8_t)(SPI1W0 & 0xff);
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}
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@ -1,62 +1,86 @@
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/*
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* Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>
|
||||
* Copyright (c) 2014 by Paul Stoffregen <paul@pjrc.com> (Transaction API)
|
||||
* Copyright (c) 2014 by Matthijs Kooijman <matthijs@stdin.nl> (SPISettings AVR)
|
||||
* SPI Master library for arduino.
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of either the GNU General Public License version 2
|
||||
* or the GNU Lesser General Public License version 2.1, both as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/*
|
||||
SPI.h - SPI library for esp8266
|
||||
|
||||
Copyright (c) 2015 Hristo Gochkov. All rights reserved.
|
||||
This file is part of the esp8266 core for Arduino environment.
|
||||
|
||||
This library is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
This library is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with this library; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
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#ifndef _SPI_H_INCLUDED
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#define _SPI_H_INCLUDED
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#include <Arduino.h>
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#include <stdlib.h>
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#include "include/SPIdef.h"
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|
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#define FCPU80 80000000L
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|
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#if F_CPU == FCPU80
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#define SPI_CLOCK_DIV80M 0x80000000 //80 MHz
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#define SPI_CLOCK_DIV40M 0x00001001 //40 MHz
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#define SPI_CLOCK_DIV20M 0x00041001 //20 MHz
|
||||
#define SPI_CLOCK_DIV16M 0x000fffc0 //16 MHz
|
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#define SPI_CLOCK_DIV10M 0x000c1001 //10 MHz
|
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#define SPI_CLOCK_DIV2 0x00101001 //8 MHz
|
||||
#define SPI_CLOCK_DIV5M 0x001c1001 //5 MHz
|
||||
#define SPI_CLOCK_DIV4 0x00241001 //4 MHz
|
||||
#define SPI_CLOCK_DIV8 0x004c1001 //2 MHz
|
||||
#define SPI_CLOCK_DIV16 0x009c1001 //1 MHz
|
||||
#define SPI_CLOCK_DIV32 0x013c1001 //500 KHz
|
||||
#define SPI_CLOCK_DIV64 0x027c1001 //250 KHz
|
||||
#define SPI_CLOCK_DIV128 0x04fc1001 //125 KHz
|
||||
#else
|
||||
#define SPI_CLOCK_DIV160M 0x80000000 //160 MHz
|
||||
#define SPI_CLOCK_DIV80M 0x00001001 //80 MHz
|
||||
#define SPI_CLOCK_DIV40M 0x00041001 //40 MHz
|
||||
#define SPI_CLOCK_DIV32M 0x000fffc0 //32 MHz
|
||||
#define SPI_CLOCK_DIV20M 0x000c1001 //20 MHz
|
||||
#define SPI_CLOCK_DIV16M 0x00101001 //16 MHz
|
||||
#define SPI_CLOCK_DIV10M 0x001c1001 //10 MHz
|
||||
#define SPI_CLOCK_DIV2 0x00241001 //8 MHz
|
||||
#define SPI_CLOCK_DIV4 0x004c1001 //4 MHz
|
||||
#define SPI_CLOCK_DIV8 0x009c1001 //2 MHz
|
||||
#define SPI_CLOCK_DIV16 0x013c1001 //1 MHz
|
||||
#define SPI_CLOCK_DIV32 0x027c1001 //500 KHz
|
||||
#define SPI_CLOCK_DIV64 0x04fc1001 //250 KHz
|
||||
#endif
|
||||
|
||||
struct SPISettings
|
||||
{
|
||||
SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode)
|
||||
: _clock(clock)
|
||||
, _bitOrder(bitOrder)
|
||||
, _dataMode(dataMode)
|
||||
{
|
||||
}
|
||||
const uint8_t SPI_MODE0 = 0x00;
|
||||
const uint8_t SPI_MODE1 = 0x04;
|
||||
const uint8_t SPI_MODE2 = 0x08;
|
||||
const uint8_t SPI_MODE3 = 0x0C;
|
||||
|
||||
class SPISettings {
|
||||
public:
|
||||
SPISettings() :_clock(SPI_CLOCK_DIV16), _bitOrder(LSBFIRST), _dataMode(SPI_MODE0){}
|
||||
SPISettings(uint32_t clock, uint8_t bitOrder, uint8_t dataMode) :_clock(clock), _bitOrder(bitOrder), _dataMode(dataMode){}
|
||||
uint32_t _clock;
|
||||
uint8_t _bitOrder;
|
||||
uint8_t _dataMode;
|
||||
};
|
||||
|
||||
class SPIImpl;
|
||||
|
||||
class SPIClass
|
||||
{
|
||||
class SPIClass {
|
||||
public:
|
||||
SPIClass();
|
||||
|
||||
void begin();
|
||||
|
||||
// void usingInterrupt(uint8_t interruptNumber);
|
||||
void beginTransaction(SPISettings settings);
|
||||
uint8_t transfer(uint8_t data);
|
||||
uint16_t transfer16(uint16_t data);
|
||||
void transfer(void *buf, size_t count);
|
||||
void endTransaction(void);
|
||||
|
||||
void end();
|
||||
|
||||
void setBitOrder(uint8_t bitOrder);
|
||||
void setDataMode(uint8_t dataMode);
|
||||
void setClockDivider(uint8_t clockDiv);
|
||||
|
||||
private:
|
||||
SPIImpl* _impl;
|
||||
void setClockDivider(uint32_t clockDiv);
|
||||
void beginTransaction(SPISettings settings);
|
||||
uint8_t transfer(uint8_t data);
|
||||
void endTransaction(void);
|
||||
};
|
||||
|
||||
extern SPIClass SPI;
|
||||
|
||||
@ -1,51 +0,0 @@
|
||||
#ifndef HSPI_H
|
||||
#define HSPI_H
|
||||
|
||||
#include "SPIImpl.h"
|
||||
#include "SPIdef.h"
|
||||
|
||||
extern "C" {
|
||||
#include "spi_register.h"
|
||||
#include "ets_sys.h"
|
||||
#include "osapi.h"
|
||||
#include "os_type.h"
|
||||
}
|
||||
|
||||
class HSPI : public SPIImpl
|
||||
{
|
||||
public:
|
||||
virtual void begin();
|
||||
virtual void end();
|
||||
virtual void setBitOrder(uint8_t bitOrder);
|
||||
virtual void setDataMode(uint8_t dataMode);
|
||||
virtual void setClockDivider(uint8_t clockDiv);
|
||||
virtual uint8_t transfer(uint8_t data);
|
||||
virtual uint16_t transfer16(uint16_t data);
|
||||
virtual void transfer(void *buf, size_t count);
|
||||
|
||||
private:
|
||||
uint32_t _clkDiv;
|
||||
uint32_t *spi_fifo;
|
||||
const uint32_t hspi_port = 1;
|
||||
const uint32_t hspi_fifo_size = 16;
|
||||
|
||||
private:
|
||||
inline void hspi_wait_ready(void){while (READ_PERI_REG(SPI_FLASH_CMD(hspi_port))&SPI_FLASH_USR);}
|
||||
inline void hspi_start_tx(){SET_PERI_REG_MASK(SPI_FLASH_CMD(hspi_port), SPI_FLASH_USR);}
|
||||
inline void hspi_prepare_tx(uint32_t bytecount)
|
||||
{
|
||||
uint32_t bitcount = bytecount * 8 - 1;
|
||||
WRITE_PERI_REG(SPI_FLASH_USER1(hspi_port), (bitcount & SPI_USR_OUT_BITLEN) << SPI_USR_OUT_BITLEN_S);
|
||||
}
|
||||
inline void hspi_prepare_txrx(uint32_t bytecount)
|
||||
{
|
||||
uint32_t bitcount = bytecount * 8 - 1;
|
||||
WRITE_PERI_REG(SPI_FLASH_USER1(hspi_port), ((bitcount & SPI_USR_OUT_BITLEN) << SPI_USR_OUT_BITLEN_S) |
|
||||
((bitcount & SPI_USR_DIN_BITLEN) << SPI_USR_DIN_BITLEN_S));
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif//HSPI_H
|
||||
@ -1,21 +0,0 @@
|
||||
#ifndef SPIIMPL_H
|
||||
#define SPIIMPL_H
|
||||
|
||||
#include <cstdlib>
|
||||
#include <Arduino.h>
|
||||
class SPIImpl
|
||||
{
|
||||
public:
|
||||
virtual void begin() = 0;
|
||||
virtual uint8_t transfer(uint8_t data) = 0;
|
||||
virtual uint16_t transfer16(uint16_t data) = 0;
|
||||
virtual void transfer(void *buf, size_t count) = 0;
|
||||
virtual void end() = 0;
|
||||
|
||||
virtual void setBitOrder(uint8_t bitOrder) = 0;
|
||||
virtual void setDataMode(uint8_t dataMode) = 0;
|
||||
virtual void setClockDivider(uint8_t clockDiv) = 0;
|
||||
};
|
||||
|
||||
|
||||
#endif//SPIIMPL_H
|
||||
@ -1,28 +0,0 @@
|
||||
#ifndef SPIDEF_H
|
||||
#define SPIDEF_H
|
||||
|
||||
|
||||
#ifndef LSBFIRST
|
||||
#define LSBFIRST 0
|
||||
#endif
|
||||
#ifndef MSBFIRST
|
||||
#define MSBFIRST 1
|
||||
#endif
|
||||
|
||||
|
||||
// AVR compatibility definitions
|
||||
const uint8_t SPI_CLOCK_DIV4 = 4;
|
||||
const uint8_t SPI_CLOCK_DIV16 = 16;
|
||||
const uint8_t SPI_CLOCK_DIV64 = 64;
|
||||
const uint8_t SPI_CLOCK_DIV128 = 128;
|
||||
const uint8_t SPI_CLOCK_DIV2 = 2;
|
||||
const uint8_t SPI_CLOCK_DIV8 = 8;
|
||||
const uint8_t SPI_CLOCK_DIV32 = 32;
|
||||
|
||||
const uint8_t SPI_MODE0 = 0x00;
|
||||
const uint8_t SPI_MODE1 = 0x04;
|
||||
const uint8_t SPI_MODE2 = 0x08;
|
||||
const uint8_t SPI_MODE3 = 0x0C;
|
||||
|
||||
|
||||
#endif//SPIDEF_H
|
||||
@ -1,239 +0,0 @@
|
||||
//Generated at 2014-07-29 11:03:29
|
||||
/*
|
||||
* Copyright (c) 2010 - 2011 Espressif System
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef SPI_REGISTER_H_INCLUDED
|
||||
#define SPI_REGISTER_H_INCLUDED
|
||||
|
||||
#define REG_SPI_BASE(i) (0x60000200-i*0x100)
|
||||
|
||||
#define SPI_FLASH_CMD(i) (REG_SPI_BASE(i) + 0x0)
|
||||
#define SPI_FLASH_READ (BIT(31))
|
||||
#define SPI_FLASH_WREN (BIT(30))
|
||||
#define SPI_FLASH_WRDI (BIT(29))
|
||||
#define SPI_FLASH_RDID (BIT(28))
|
||||
#define SPI_FLASH_RDSR (BIT(27))
|
||||
#define SPI_FLASH_WRSR (BIT(26))
|
||||
#define SPI_FLASH_PP (BIT(25))
|
||||
#define SPI_FLASH_SE (BIT(24))
|
||||
#define SPI_FLASH_BE (BIT(23))
|
||||
#define SPI_FLASH_CE (BIT(22))
|
||||
#define SPI_FLASH_DP (BIT(21))
|
||||
#define SPI_FLASH_RES (BIT(20))
|
||||
#define SPI_FLASH_HPM (BIT(19))
|
||||
#define SPI_FLASH_USR (BIT(18))
|
||||
|
||||
#define SPI_FLASH_ADDR(i) (REG_SPI_BASE(i) + 0x4)
|
||||
|
||||
#define SPI_FLASH_CTRL(i) (REG_SPI_BASE(i) + 0x8)
|
||||
#define SPI_WR_BIT_ODER (BIT(26))
|
||||
#define SPI_RD_BIT_ODER (BIT(25))
|
||||
#define SPI_QIO_MODE (BIT(24))
|
||||
#define SPI_DIO_MODE (BIT(23))
|
||||
#define SPI_TWO_BYTE_STATUS_EN (BIT(22))
|
||||
#define SPI_WP_REG (BIT(21))
|
||||
#define SPI_QOUT_MODE (BIT(20))
|
||||
#define SPI_SHARE_BUS (BIT(19))
|
||||
#define SPI_HOLD_MODE (BIT(18))
|
||||
#define SPI_ENABLE_AHB (BIT(17))
|
||||
#define SPI_SST_AAI (BIT(16))
|
||||
#define SPI_RESANDRES (BIT(15))
|
||||
#define SPI_DOUT_MODE (BIT(14))
|
||||
#define SPI_FASTRD_MODE (BIT(13))
|
||||
|
||||
#define SPI_FLASH_CTRL1(i) (REG_SPI_BASE (i) + 0xC)
|
||||
#define SPI_T_CSH 0x0000000F
|
||||
#define SPI_T_CSH_S 28
|
||||
#define SPI_T_RES 0x00000FFF
|
||||
#define SPI_T_RES_S 16
|
||||
#define SPI_BUS_TIMER_LIMIT 0x0000FFFF
|
||||
#define SPI_BUS_TIMER_LIMIT_S 0
|
||||
|
||||
#define SPI_FLASH_STATUS(i) (REG_SPI_BASE(i) + 0x10)
|
||||
#define SPI_STATUS_EXT 0x000000FF
|
||||
#define SPI_STATUS_EXT_S 24
|
||||
#define SPI_WB_MODE 0x000000FF
|
||||
#define SPI_WB_MODE_S 16
|
||||
#define SPI_FLASH_STATUS_PRO_FLAG (BIT(7))
|
||||
#define SPI_FLASH_TOP_BOT_PRO_FLAG (BIT(5))
|
||||
#define SPI_FLASH_BP2 (BIT(4))
|
||||
#define SPI_FLASH_BP1 (BIT(3))
|
||||
#define SPI_FLASH_BP0 (BIT(2))
|
||||
#define SPI_FLASH_WRENABLE_FLAG (BIT(1))
|
||||
#define SPI_FLASH_BUSY_FLAG (BIT(0))
|
||||
|
||||
#define SPI_FLASH_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
|
||||
#define SPI_CS_DELAY_NUM 0x0000000F
|
||||
#define SPI_CS_DELAY_NUM_S 28
|
||||
#define SPI_CS_DELAY_MODE 0x00000003
|
||||
#define SPI_CS_DELAY_MODE_S 26
|
||||
#define SPI_MOSI_DELAY_NUM 0x00000007
|
||||
#define SPI_MOSI_DELAY_NUM_S 23
|
||||
#define SPI_MOSI_DELAY_MODE 0x00000003
|
||||
#define SPI_MOSI_DELAY_MODE_S 21
|
||||
#define SPI_MISO_DELAY_NUM 0x00000007
|
||||
#define SPI_MISO_DELAY_NUM_S 18
|
||||
#define SPI_MISO_DELAY_MODE 0x00000003
|
||||
#define SPI_MISO_DELAY_MODE_S 16
|
||||
#define SPI_CK_OUT_HIGH_MODE 0x0000000F
|
||||
#define SPI_CK_OUT_HIGH_MODE_S 12
|
||||
#define SPI_CK_OUT_LOW_MODE 0x0000000F
|
||||
#define SPI_CK_OUT_LOW_MODE_S 8
|
||||
#define SPI_HOLD_TIME 0x0000000F
|
||||
#define SPI_HOLD_TIME_S 4
|
||||
#define SPI_SETUP_TIME 0x0000000F
|
||||
#define SPI_SETUP_TIME_S 0
|
||||
|
||||
#define SPI_FLASH_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
|
||||
#define SPI_CLK_EQU_SYSCLK (BIT(31))
|
||||
#define SPI_CLKDIV_PRE 0x00001FFF
|
||||
#define SPI_CLKDIV_PRE_S 18
|
||||
#define SPI_CLKCNT_N 0x0000003F
|
||||
#define SPI_CLKCNT_N_S 12
|
||||
#define SPI_CLKCNT_H 0x0000003F
|
||||
#define SPI_CLKCNT_H_S 6
|
||||
#define SPI_CLKCNT_L 0x0000003F
|
||||
#define SPI_CLKCNT_L_S 0
|
||||
|
||||
#define SPI_FLASH_USER(i) (REG_SPI_BASE(i) + 0x1C)
|
||||
#define SPI_USR_COMMAND (BIT(31))
|
||||
#define SPI_FLASH_USR_ADDR (BIT(30))
|
||||
#define SPI_FLASH_USR_DUMMY (BIT(29))
|
||||
#define SPI_FLASH_USR_DIN (BIT(28))
|
||||
#define SPI_FLASH_DOUT (BIT(27))
|
||||
#define SPI_USR_DUMMY_IDLE (BIT(26))
|
||||
#define SPI_USR_DOUT_HIGHPART (BIT(25))
|
||||
#define SPI_USR_DIN_HIGHPART (BIT(24))
|
||||
#define SPI_USR_PREP_HOLD (BIT(23))
|
||||
#define SPI_USR_CMD_HOLD (BIT(22))
|
||||
#define SPI_USR_ADDR_HOLD (BIT(21))
|
||||
#define SPI_USR_DUMMY_HOLD (BIT(20))
|
||||
#define SPI_USR_DIN_HOLD (BIT(19))
|
||||
#define SPI_USR_DOUT_HOLD (BIT(18))
|
||||
#define SPI_USR_HOLD_POL (BIT(17))
|
||||
#define SPI_SIO (BIT(16))
|
||||
#define SPI_FWRITE_QIO (BIT(15))
|
||||
#define SPI_FWRITE_DIO (BIT(14))
|
||||
#define SPI_FWRITE_QUAD (BIT(13))
|
||||
#define SPI_FWRITE_DUAL (BIT(12))
|
||||
#define SPI_WR_BYTE_ORDER (BIT(11))
|
||||
#define SPI_RD_BYTE_ORDER (BIT(10))
|
||||
#define SPI_AHB_ENDIAN_MODE 0x00000003
|
||||
#define SPI_AHB_ENDIAN_MODE_S 8
|
||||
#define SPI_CK_OUT_EDGE (BIT(7))
|
||||
#define SPI_CK_I_EDGE (BIT(6))
|
||||
#define SPI_CS_SETUP (BIT(5))
|
||||
#define SPI_CS_HOLD (BIT(4))
|
||||
#define SPI_AHB_USR_COMMAND (BIT(3))
|
||||
#define SPI_AHB_USR_COMMAND_4BYTE (BIT(1))
|
||||
#define SPI_DOUTDIN (BIT(0))
|
||||
|
||||
#define SPI_FLASH_USER1(i) (REG_SPI_BASE(i) + 0x20)
|
||||
#define SPI_USR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_USR_ADDR_BITLEN_S 26
|
||||
#define SPI_USR_OUT_BITLEN 0x000001FF
|
||||
#define SPI_USR_OUT_BITLEN_S 17
|
||||
#define SPI_USR_DIN_BITLEN 0x000001FF
|
||||
#define SPI_USR_DIN_BITLEN_S 8
|
||||
#define SPI_USR_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_USR_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_FLASH_USER2(i) (REG_SPI_BASE(i) + 0x24)
|
||||
#define SPI_USR_COMMAND_BITLEN 0x0000000F
|
||||
#define SPI_USR_COMMAND_BITLEN_S 28
|
||||
#define SPI_USR_COMMAND_VALUE 0x0000FFFF
|
||||
#define SPI_USR_COMMAND_VALUE_S 0
|
||||
|
||||
#define SPI_FLASH_USER3(i) (REG_SPI_BASE(i) + 0x28)
|
||||
#define SPI_FLASH_PIN(i) (REG_SPI_BASE(i) + 0x2C)
|
||||
#define SPI_FLASH_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
|
||||
#define SPI_SYNC_RESET (BIT(31))
|
||||
#define SPI_SLAVE_MODE (BIT(30))
|
||||
#define SPI_SLV_WR_RD_BUF_EN (BIT(29))
|
||||
#define SPI_SLV_WR_RD_STA_EN (BIT(28))
|
||||
#define SPI_SLV_CMD_DEFINE (BIT(27))
|
||||
#define SPI_TRANS_CNT 0x0000000F
|
||||
#define SPI_TRANS_CNT_S 23
|
||||
#define SPI_SLV_LAST_STATE 0x00000007
|
||||
#define SPI_SLV_LAST_STATE_S 20
|
||||
#define SPI_SLV_LAST_COMMAND 0x00000007
|
||||
#define SPI_SLV_LAST_COMMAND_S 17
|
||||
#define SPI_CS_I_MODE 0x00000003
|
||||
#define SPI_CS_I_MODE_S 10
|
||||
#define SPI_INT_EN 0x0000001F
|
||||
#define SPI_INT_EN_S 5
|
||||
#define SPI_TRANS_DONE (BIT(4))
|
||||
#define SPI_SLV_WR_STA_DONE (BIT(3))
|
||||
#define SPI_SLV_RD_STA_DONE (BIT(2))
|
||||
#define SPI_SLV_WR_BUF_DONE (BIT(1))
|
||||
#define SPI_SLV_RD_BUF_DONE (BIT(0))
|
||||
|
||||
#define SPI_FLASH_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
|
||||
#define SPI_SLV_STATUS_BITLEN 0x0000001F
|
||||
#define SPI_SLV_STATUS_BITLEN_S 27
|
||||
#define SPI_SLV_STATUS_FAST_EN (BIT(26))
|
||||
#define SPI_SLV_STATUS_READBACK (BIT(25))
|
||||
#define SPI_SLV_BUF_BITLEN 0x000001FF
|
||||
#define SPI_SLV_BUF_BITLEN_S 16
|
||||
#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_RD_ADDR_BITLEN_S 10
|
||||
#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
|
||||
#define SPI_SLV_WR_ADDR_BITLEN_S 4
|
||||
#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
|
||||
#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
|
||||
#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
|
||||
#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
|
||||
|
||||
#define SPI_FLASH_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
|
||||
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8
|
||||
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF
|
||||
#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0
|
||||
|
||||
#define SPI_FLASH_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRSTA_CMD_VALUE_S 24
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDSTA_CMD_VALUE_S 16
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_WRBUF_CMD_VALUE_S 8
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
|
||||
#define SPI_SLV_RDBUF_CMD_VALUE_S 0
|
||||
|
||||
#define SPI_FLASH_C0(i) (REG_SPI_BASE(i) +0x40)
|
||||
#define SPI_FLASH_C1(i) (REG_SPI_BASE(i) +0x44)
|
||||
#define SPI_FLASH_C2(i) (REG_SPI_BASE(i) +0x48)
|
||||
#define SPI_FLASH_C3(i) (REG_SPI_BASE(i) +0x4C)
|
||||
#define SPI_FLASH_C4(i) (REG_SPI_BASE(i) +0x50)
|
||||
#define SPI_FLASH_C5(i) (REG_SPI_BASE(i) +0x54)
|
||||
#define SPI_FLASH_C6(i) (REG_SPI_BASE(i) +0x58)
|
||||
#define SPI_FLASH_C7(i) (REG_SPI_BASE(i) +0x5C)
|
||||
|
||||
#define SPI_FLASH_EXT0(i) (REG_SPI_BASE(i) + 0xF0)
|
||||
#define SPI_T_PP_ENA (BIT(31))
|
||||
#define SPI_T_PP_SHIFT 0x0000000F
|
||||
#define SPI_T_PP_SHIFT_S 16
|
||||
#define SPI_T_PP_TIME 0x00000FFF
|
||||
#define SPI_T_PP_TIME_S 0
|
||||
|
||||
#define SPI_FLASH_EXT1(i) (REG_SPI_BASE(i) + 0xF4)
|
||||
#define SPI_T_ERASE_ENA (BIT(31))
|
||||
#define SPI_T_ERASE_SHIFT 0x0000000F
|
||||
#define SPI_T_ERASE_SHIFT_S 16
|
||||
#define SPI_T_ERASE_TIME 0x00000FFF
|
||||
#define SPI_T_ERASE_TIME_S 0
|
||||
|
||||
#define SPI_FLASH_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
|
||||
#define SPI_ST 0x00000007
|
||||
#define SPI_ST_S 0
|
||||
|
||||
#define SPI_FLASH_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
|
||||
#define SPI_INT_HOLD_ENA 0x00000003
|
||||
#define SPI_INT_HOLD_ENA_S 0
|
||||
#endif // SPI_REGISTER_H_INCLUDED
|
||||
Reference in New Issue
Block a user