mirror of
https://github.com/esp8266/Arduino.git
synced 2025-06-12 01:53:07 +03:00
Add flash for vtable destination, make it default, and add build menu to control options (#4582)
* Add flash for vtable destination, make it default Add an option for placing vtables in flash to complement the existing iram and heap options. "make flash" Now that there is a way to change it, move to vtables in flash as default as only users with interrupts which use vtables require the vtable to be in RAM. For those users, if the tables are small enough they can put them in IRAM and save heap space for their app. If not, then the vtables can be placed in HEAP which supports much larger tables. * Add VTable menu, FLASH as default, remove Makefile Convert from manual "make" operated app.ld creation to runtime creation whose options are selected from the build menu. Use a prelink recipe to create the output app.ld file each run, without need for any special tools. Update the boards.txt.py script to generate this new config.
This commit is contained in:
Earle F. Philhower, III
committed by
david gauchard
david gauchard
parent
8ae553d99e
commit
f2c7256539
@ -757,6 +757,15 @@ macros = {
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( '.menu.CpuFrequency.160.build.f_cpu', '160000000L' ),
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]),
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'vtable_menu': collections.OrderedDict([
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( '.menu.VTable.flash', 'Flash'),
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( '.menu.VTable.flash.build.vtable_flags', '-DVTABLES_IN_FLASH'),
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( '.menu.VTable.heap', 'Heap'),
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( '.menu.VTable.heap.build.vtable_flags', '-DVTABLES_IN_DRAM'),
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( '.menu.VTable.iram', 'IRAM'),
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( '.menu.VTable.iram.build.vtable_flags', '-DVTABLES_IN_IRAM'),
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]),
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'crystalfreq_menu': collections.OrderedDict([
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( '.menu.CrystalFreq.26', '26 MHz' ),
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( '.menu.CrystalFreq.40', '40 MHz' ),
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@ -1147,6 +1156,7 @@ def all_boards ():
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print 'menu.Debug=Debug port'
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print 'menu.DebugLevel=Debug Level'
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print 'menu.LwIPVariant=lwIP Variant'
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print 'menu.VTable=VTables'
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print 'menu.led=Builtin Led'
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print 'menu.FlashErase=Erase Flash'
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print ''
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@ -1162,7 +1172,7 @@ def all_boards ():
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print id + optname + '=' + board['opts'][optname]
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# macros
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macrolist = [ 'defaults', 'cpufreq_menu', ]
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macrolist = [ 'defaults', 'cpufreq_menu', 'vtable_menu' ]
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if 'macro' in board:
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macrolist += board['macro']
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if lwip == 2:
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@ -1,17 +0,0 @@
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CPP = ../../../tools/xtensa-lx106-elf/bin/xtensa-lx106-elf-cpp
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COMMON = eagle.app.v6.common.ld
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WARN = "\/\* warning: AUTOGENERATED from $(COMMON)\*.h \*\/"
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all:
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@echo "available rules:"
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@echo " iram: move c++ vtables to iram (= default in git master repository)"
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@echo " heap: move c++ vtables to heap"
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heap:
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@(echo "$(WARN)"; $(CPP) -CC -E -DVTABLES_IN_DRAM $(COMMON).h | grep -v '^#') > $(COMMON)
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@echo "c++ vtables moved to heap"
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iram:
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@(echo "$(WARN)"; $(CPP) -CC -E -DVTABLES_IN_IRAM $(COMMON).h | grep -v '^#') > $(COMMON)
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@echo "c++ vtables moved to iram"
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@ -1,7 +1,5 @@
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/* warning: AUTOGENERATED from eagle.app.v6.common.ld*.h */
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/* This linker script generated from xt-genldscripts.tpp for LSP . */
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/* Linker Script for ld -N */
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PHDRS
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{
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dport0_0_phdr PT_LOAD;
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@ -10,8 +8,6 @@ PHDRS
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iram1_0_phdr PT_LOAD;
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irom0_0_phdr PT_LOAD;
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}
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/* Default entry point: */
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ENTRY(call_user_start)
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EXTERN(_DebugExceptionVector)
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@ -38,10 +34,8 @@ _memmap_cacheattr_wb_allvalid = 0x22222112;
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_memmap_cacheattr_wt_allvalid = 0x22222112;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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SECTIONS
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{
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.dport0.rodata : ALIGN(4)
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{
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_dport0_rodata_start = ABSOLUTE(.);
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@ -49,7 +43,6 @@ SECTIONS
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*(.dport.rodata)
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_dport0_rodata_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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.dport0.literal : ALIGN(4)
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{
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_dport0_literal_start = ABSOLUTE(.);
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@ -57,7 +50,6 @@ SECTIONS
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*(.dport.literal)
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_dport0_literal_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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.dport0.data : ALIGN(4)
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{
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_dport0_data_start = ABSOLUTE(.);
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@ -65,7 +57,6 @@ SECTIONS
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*(.dport.data)
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_dport0_data_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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.data : ALIGN(4)
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{
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_data_start = ABSOLUTE(.);
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@ -84,17 +75,13 @@ SECTIONS
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_Pri_3_HandlerAddress = ABSOLUTE(.);
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_data_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.irom0.text : ALIGN(4)
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{
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_irom0_text_start = ABSOLUTE(.);
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*(.ver_number)
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*.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, EXCLUDE_FILE (umm_malloc.c.o) .text* )
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*.cpp.o(.literal*, .text*)
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*(.rodata._ZTV*) /* C++ vtables */
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*libc.a:(.literal .text .literal.* .text.*)
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*libm.a:(.literal .text .literal.* .text.*)
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*libgcc.a:_umoddi3.o(.literal .text)
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@ -123,7 +110,6 @@ SECTIONS
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_irom0_text_end = ABSOLUTE(.);
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_flash_code_end = ABSOLUTE(.);
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} >irom0_0_seg :irom0_0_phdr
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.text : ALIGN(4)
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{
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_stext = .;
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@ -158,17 +144,12 @@ SECTIONS
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*.cpp.o(.iram.text)
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*.c.o(.iram.text)
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*(.rodata._ZTV*) /* C++ vtables */
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_text_end = ABSOLUTE(.);
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_etext = .;
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} >iram1_0_seg :iram1_0_phdr
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.rodata : ALIGN(4)
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{
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_rodata_start = ABSOLUTE(.);
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@ -210,7 +191,6 @@ SECTIONS
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_bss_table_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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.bss ALIGN(8) (NOLOAD) : ALIGN(4)
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{
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. = ALIGN (8);
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@ -234,8 +214,6 @@ SECTIONS
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/* _stack_sentry = ALIGN(0x8); */
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} >dram0_0_seg :dram0_0_bss_phdr
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/* __stack = 0x3ffc8000; */
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.lit4 : ALIGN(4)
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{
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_lit4_start = ABSOLUTE(.);
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@ -244,9 +222,6 @@ SECTIONS
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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} >iram1_0_seg :iram1_0_phdr
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}
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/* get ROM code address */
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INCLUDE "../ld/eagle.rom.addr.v6.ld"
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@ -94,6 +94,9 @@ SECTIONS
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*(.ver_number)
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*.c.o( EXCLUDE_FILE (umm_malloc.c.o) .literal*, EXCLUDE_FILE (umm_malloc.c.o) .text* )
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*.cpp.o(.literal*, .text*)
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#ifdef VTABLES_IN_FLASH
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*(.rodata._ZTV*) /* C++ vtables */
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#endif
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*libc.a:(.literal .text .literal.* .text.*)
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*libm.a:(.literal .text .literal.* .text.*)
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*libgcc.a:_umoddi3.o(.literal .text)
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@ -167,7 +170,7 @@ SECTIONS
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_etext = .;
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} >iram1_0_seg :iram1_0_phdr
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#ifdef VTABLES_IN_IRAM
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#if defined(VTABLES_IN_IRAM) || defined(VTABLES_IN_FLASH)
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#include "eagle.app.v6.common.ld.vtables.h"
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#endif
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