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mirror of https://github.com/esp8266/Arduino.git synced 2025-07-30 16:24:09 +03:00

[sam] merging CMSIS with current internal dev

This commit is contained in:
Thibaut VIARD
2011-10-11 20:46:18 +02:00
parent 2699d5d001
commit ee7177d68b
87 changed files with 955 additions and 1078 deletions

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@ -2,9 +2,11 @@
*
* \brief This file contains the default exception handlers.
*
* $asf_license$
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \note
@ -17,8 +19,6 @@
*
******************************************************************************/
/* $asf_license$ */
#include "exceptions.h"
/* @cond 0 */

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@ -2,9 +2,11 @@
*
* \brief This file contains the interface for default exception handlers.
*
* $asf_license$
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \author Atmel Corporation: http://www.atmel.com \n
@ -12,10 +14,8 @@
*
******************************************************************************/
/* $asf_license$ */
#ifndef _EXCEPTIONS_
#define _EXCEPTIONS_
#ifndef EXCEPTIONS_H_INCLUDED
#define EXCEPTIONS_H_INCLUDED
/* @cond 0 */
/**INDENT-OFF**/
@ -85,4 +85,5 @@ extern void WDT_IrqHandler( void ) ;
/**INDENT-ON**/
/* @endcond */
#endif /* _EXCEPTIONS_ */
#endif /* EXCEPTIONS_H_INCLUDED */

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@ -2,6 +2,8 @@
*
* \brief Startup file for SAM3S8/SAM3SD.
*
* $asf_license$
*
* This file defines common SAM series.
*
* - Compiler: ARMGCC
@ -10,20 +12,10 @@
*
******************************************************************************/
/* $asf_license$ */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "exceptions.h"
#include "sam3s8.h"
#include "system_sam3sd8.h"
/*----------------------------------------------------------------------------
* Exported variables
*----------------------------------------------------------------------------*/
/* Stack Configuration */
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
__attribute__ ((aligned(8),section(".stack")))
@ -38,27 +30,18 @@ extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
/*----------------------------------------------------------------------------
* ProtoTypes
*----------------------------------------------------------------------------*/
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
extern int main( void ) ;
/** \endcond */
void ResetException( void ) ;
extern void __libc_init_array( void ) ;
/*----------------------------------------------------------------------------
* Exception Table
*----------------------------------------------------------------------------*/
/* Exception Table */
__attribute__((section(".vectors")))
IntFunc exception_table[] = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(IntFunc)(&pdwStack[STACK_SIZE-1]),
ResetException,
Reset_Handler,
NMI_Handler,
HardFault_Handler,
@ -119,7 +102,7 @@ IntFunc exception_table[] = {
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void ResetException( void )
void Reset_Handler( void )
{
uint32_t *pSrc, *pDest ;

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@ -2,6 +2,8 @@
*
* \brief Startup file for SAM3S8/SAM3SD.
*
* $asf_license$
*
* This file defines common SAM series.
*
* - Compiler: IAR EWARM
@ -10,39 +12,20 @@
*
******************************************************************************/
/* $asf_license$ */
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "exceptions.h"
#include "sam3s8.h"
#include "system_sam3sd8.h"
/*----------------------------------------------------------------------------
* Exported variables
*----------------------------------------------------------------------------*/
/*------------------------------------------------------------------------------
* Types
*------------------------------------------------------------------------------*/
typedef void( *intfunc )( void );
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
/*------------------------------------------------------------------------------
* Prototypes
*------------------------------------------------------------------------------*/
extern void __iar_program_start( void ) ;
extern int __low_level_init( void ) ;
/*------------------------------------------------------------------------------
* Exception Table
*------------------------------------------------------------------------------*/
/* Exception Table */
#pragma language=extended
#pragma segment="CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0. */

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@ -3,6 +3,8 @@
* \brief Provides the low-level initialization functions that called
* on chip startup.
*
* $asf_license$
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
@ -13,11 +15,8 @@
*
******************************************************************************/
/* $asf_license$ */
#include "system_sam3sd8.h"
#include "sam3s8.h"
#include "sam3s_ek2.h"
/* @cond 0 */
/**INDENT-OFF**/
@ -89,14 +88,17 @@ extern void SystemCoreClockUpdate( void )
/* Determine clock frequency according to clock register values */
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL)
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
SystemCoreClock = OSC32_CLK;
else
}
else {
SystemCoreClock = ERC_OSC;
}
break;
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = MAINCK_XTAL_HZ;
}
else {
SystemCoreClock = EFRC_OSC;
@ -116,8 +118,9 @@ extern void SystemCoreClockUpdate( void )
break;
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = MAINCK_XTAL_HZ;
}
else {
SystemCoreClock = EFRC_OSC;
@ -145,10 +148,12 @@ extern void SystemCoreClockUpdate( void )
break;
}
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3)
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
SystemCoreClock /= 3;
else
}
else {
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
}
}
/* @cond 0 */

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@ -3,6 +3,8 @@
* \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
* for SAM3 devices.
*
* $asf_license$
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
@ -13,10 +15,8 @@
*
******************************************************************************/
/* $asf_license$ */
#ifndef __SYSTEM_SAM3SD8_
#define __SYSTEM_SAM3SD8_
#ifndef SYSTEM_SAM3SD8_H_INCLUDED
#define SYSTEM_SAM3SD8_H_INCLUDED
/* @cond 0 */
/**INDENT-OFF**/
@ -50,4 +50,5 @@ extern void SystemCoreClockUpdate(void);
/**INDENT-ON**/
/* @endcond */
#endif /* __SYSTEM_SAM3SD8_ */
#endif /* SYSTEM_SAM3SD8_H_INCLUDED */