mirror of
https://github.com/esp8266/Arduino.git
synced 2025-07-30 16:24:09 +03:00
[sam] merging CMSIS with current internal dev
This commit is contained in:
@ -2,9 +2,11 @@
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*
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* \brief This file contains the default exception handlers.
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*
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* $asf_license$
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*
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* \par Purpose
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*
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* This file provides basic support for Cortex-M processor based
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* This file provides basic support for Cortex-M processor based
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* microcontrollers.
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*
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* \note
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@ -17,8 +19,6 @@
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*
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******************************************************************************/
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/* $asf_license$ */
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#include "exceptions.h"
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/* @cond 0 */
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@ -2,9 +2,11 @@
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*
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* \brief This file contains the interface for default exception handlers.
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*
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* $asf_license$
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*
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* \par Purpose
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*
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* This file provides basic support for Cortex-M processor based
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* This file provides basic support for Cortex-M processor based
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* microcontrollers.
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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@ -12,10 +14,8 @@
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*
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******************************************************************************/
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/* $asf_license$ */
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#ifndef _EXCEPTIONS_
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#define _EXCEPTIONS_
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#ifndef EXCEPTIONS_H_INCLUDED
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#define EXCEPTIONS_H_INCLUDED
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/* @cond 0 */
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/**INDENT-OFF**/
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@ -85,4 +85,5 @@ extern void WDT_IrqHandler( void ) ;
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/**INDENT-ON**/
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/* @endcond */
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#endif /* _EXCEPTIONS_ */
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#endif /* EXCEPTIONS_H_INCLUDED */
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@ -2,6 +2,8 @@
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*
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* \brief Startup file for SAM3S8/SAM3SD.
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*
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* $asf_license$
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*
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* This file defines common SAM series.
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*
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* - Compiler: ARMGCC
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@ -10,20 +12,10 @@
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*
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******************************************************************************/
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/* $asf_license$ */
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include "exceptions.h"
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#include "sam3s8.h"
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#include "system_sam3sd8.h"
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/*----------------------------------------------------------------------------
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* Exported variables
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*----------------------------------------------------------------------------*/
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/* Stack Configuration */
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#define STACK_SIZE 0x900 /** Stack size (in DWords) */
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__attribute__ ((aligned(8),section(".stack")))
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@ -38,27 +30,18 @@ extern uint32_t _erelocate;
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extern uint32_t _szero;
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extern uint32_t _ezero;
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/*----------------------------------------------------------------------------
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* ProtoTypes
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*----------------------------------------------------------------------------*/
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/** \cond DOXYGEN_SHOULD_SKIP_THIS */
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extern int main( void ) ;
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/** \endcond */
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void ResetException( void ) ;
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extern void __libc_init_array( void ) ;
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/*----------------------------------------------------------------------------
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* Exception Table
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*----------------------------------------------------------------------------*/
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/* Exception Table */
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__attribute__((section(".vectors")))
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IntFunc exception_table[] = {
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/* Configure Initial Stack Pointer, using linker-generated symbols */
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(IntFunc)(&pdwStack[STACK_SIZE-1]),
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ResetException,
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Reset_Handler,
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NMI_Handler,
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HardFault_Handler,
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@ -119,7 +102,7 @@ IntFunc exception_table[] = {
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* \brief This is the code that gets called on processor reset.
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* To initialize the device, and call the main() routine.
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*/
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void ResetException( void )
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void Reset_Handler( void )
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{
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uint32_t *pSrc, *pDest ;
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@ -2,6 +2,8 @@
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*
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* \brief Startup file for SAM3S8/SAM3SD.
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*
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* $asf_license$
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*
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* This file defines common SAM series.
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*
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* - Compiler: IAR EWARM
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@ -10,39 +12,20 @@
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*
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******************************************************************************/
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/* $asf_license$ */
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include "exceptions.h"
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#include "sam3s8.h"
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#include "system_sam3sd8.h"
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/*----------------------------------------------------------------------------
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* Exported variables
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*----------------------------------------------------------------------------*/
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/*------------------------------------------------------------------------------
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* Types
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*------------------------------------------------------------------------------*/
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typedef void( *intfunc )( void );
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typedef union { intfunc __fun; void * __ptr; } intvec_elem;
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/*------------------------------------------------------------------------------
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* Prototypes
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*------------------------------------------------------------------------------*/
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extern void __iar_program_start( void ) ;
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extern int __low_level_init( void ) ;
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/*------------------------------------------------------------------------------
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* Exception Table
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*------------------------------------------------------------------------------*/
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/* Exception Table */
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#pragma language=extended
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#pragma segment="CSTACK"
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/* The name "__vector_table" has special meaning for C-SPY: */
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/* it is where the SP start value is found, and the NVIC vector */
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/* table register (VTOR) is initialized to this address if != 0. */
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@ -3,6 +3,8 @@
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* \brief Provides the low-level initialization functions that called
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* on chip startup.
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*
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* $asf_license$
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*
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* \par Purpose
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*
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* This file provides basic support for Cortex-M processor based
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@ -13,11 +15,8 @@
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*
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******************************************************************************/
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/* $asf_license$ */
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#include "system_sam3sd8.h"
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#include "sam3s8.h"
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#include "sam3s_ek2.h"
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/* @cond 0 */
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/**INDENT-OFF**/
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@ -89,14 +88,17 @@ extern void SystemCoreClockUpdate( void )
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/* Determine clock frequency according to clock register values */
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switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
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case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
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if (SUPC->SUPC_SR & SUPC_SR_OSCSEL)
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if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
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SystemCoreClock = OSC32_CLK;
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else
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}
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else {
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SystemCoreClock = ERC_OSC;
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}
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break;
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case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
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if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
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if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
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SystemCoreClock = MAINCK_XTAL_HZ;
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}
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else {
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SystemCoreClock = EFRC_OSC;
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@ -116,8 +118,9 @@ extern void SystemCoreClockUpdate( void )
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break;
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case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
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case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
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if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)
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if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
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SystemCoreClock = MAINCK_XTAL_HZ;
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}
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else {
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SystemCoreClock = EFRC_OSC;
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@ -145,10 +148,12 @@ extern void SystemCoreClockUpdate( void )
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break;
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}
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if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3)
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if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
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SystemCoreClock /= 3;
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else
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}
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else {
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SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
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}
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}
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/* @cond 0 */
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@ -3,6 +3,8 @@
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* \brief CMSIS Cortex-M# Device Peripheral Access Layer Header File
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* for SAM3 devices.
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*
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* $asf_license$
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*
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* \par Purpose
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*
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* This file provides basic support for Cortex-M processor based
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@ -13,10 +15,8 @@
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*
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******************************************************************************/
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/* $asf_license$ */
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#ifndef __SYSTEM_SAM3SD8_
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#define __SYSTEM_SAM3SD8_
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#ifndef SYSTEM_SAM3SD8_H_INCLUDED
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#define SYSTEM_SAM3SD8_H_INCLUDED
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/* @cond 0 */
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/**INDENT-OFF**/
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@ -50,4 +50,5 @@ extern void SystemCoreClockUpdate(void);
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/**INDENT-ON**/
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/* @endcond */
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#endif /* __SYSTEM_SAM3SD8_ */
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#endif /* SYSTEM_SAM3SD8_H_INCLUDED */
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