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[sam] merging CMSIS with current internal dev
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@@ -79,9 +79,10 @@ typedef enum IRQn
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* \brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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#define __MPU_PRESENT 0 /**< SAM3N4C does not provide a MPU */
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#define __NVIC_PRIO_BITS 4 /**< SAM3N4C uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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#define __CM3_REV 0x0200 /**< SAM3N4C core revision number ([15:8] revision number, [7:0] patch number) */
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#define __MPU_PRESENT 0 /**< SAM3N4C does not provide a MPU */
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#define __NVIC_PRIO_BITS 4 /**< SAM3N4C uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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/*
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* \brief CMSIS includes
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@@ -272,12 +273,12 @@ typedef enum IRQn
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/* MEMORY MAPPING DEFINITIONS FOR SAM3N4C */
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/* ************************************************************************** */
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#define IFLASH_SIZE 0x40000
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#define IFLASH_PAGE_SIZE 256
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#define IFLASH_LOCK_REGION_SIZE 16384
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#define IFLASH_NB_OF_PAGES 1024
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#define IFLASH_NB_OF_LOCK_BITS 16
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#define IRAM_SIZE 0x6000
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#define IFLASH_SIZE (0x40000u)
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#define IFLASH_PAGE_SIZE (256u)
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#define IFLASH_LOCK_REGION_SIZE (16384u)
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#define IFLASH_NB_OF_PAGES (1024u)
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#define IFLASH_NB_OF_LOCK_BITS (16u)
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#define IRAM_SIZE (0x6000u)
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#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */
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#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */
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