From dc08418f086bdc6a850582b9ede5e313df4065b4 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 22 Jun 2015 03:18:02 +0300 Subject: [PATCH] Provide init data for register_chipv6_phy --- cores/esp8266/core_esp8266_main.cpp | 15 +- cores/esp8266/core_esp8266_phy.c | 248 ++++++++++++++++++++++++++++ platform.txt | 3 +- 3 files changed, 251 insertions(+), 15 deletions(-) create mode 100644 cores/esp8266/core_esp8266_phy.c diff --git a/cores/esp8266/core_esp8266_main.cpp b/cores/esp8266/core_esp8266_main.cpp index 0b165fcaf..df2d65d70 100644 --- a/cores/esp8266/core_esp8266_main.cpp +++ b/cores/esp8266/core_esp8266_main.cpp @@ -114,26 +114,13 @@ static void do_global_ctors(void) { } void init_done() { + system_set_os_print(1); do_global_ctors(); esp_schedule(); } -extern "C" int __get_rf_mode() __attribute__((weak)); -extern "C" int __get_rf_mode() -{ - return 0; // default mode -} - -extern "C" { -void user_rf_pre_init() { - system_phy_set_rfoption(__get_rf_mode()); -} -} - extern "C" { void user_init(void) { - uart_div_modify(0, UART_CLK_FREQ / (74480)); - system_rtc_mem_read(0, &resetInfo, sizeof(struct rst_info)); struct rst_info info = { 0 }; system_rtc_mem_write(0, &info, sizeof(struct rst_info)); diff --git a/cores/esp8266/core_esp8266_phy.c b/cores/esp8266/core_esp8266_phy.c new file mode 100644 index 000000000..2ac33a8a6 --- /dev/null +++ b/cores/esp8266/core_esp8266_phy.c @@ -0,0 +1,248 @@ +/* + phy.c - ESP8266 PHY initialization data + + Copyright (c) 2015 Ivan Grokhotkov. All rights reserved. + This file is part of the esp8266 core for Arduino environment. + + This library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + This library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with this library; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + + #include + #include + #include + +static uint8_t phy_init_data[128] = +{ + [0] = 5, // Reserved, do not change + [1] = 0, // Reserved, do not change + [2] = 4, // Reserved, do not change + [3] = 2, // Reserved, do not change + [4] = 5, // Reserved, do not change + [5] = 5, // Reserved, do not change + [6] = 5, // Reserved, do not change + [7] = 2, // Reserved, do not change + [8] = 5, // Reserved, do not change + [9] = 0, // Reserved, do not change + [10] = 4, // Reserved, do not change + [11] = 5, // Reserved, do not change + [12] = 5, // Reserved, do not change + [13] = 4, // Reserved, do not change + [14] = 5, // Reserved, do not change + [15] = 5, // Reserved, do not change + [16] = 4, // Reserved, do not change + [17] = -2, // Reserved, do not change + [18] = -3, // Reserved, do not change + [19] = -1, // Reserved, do not change + [20] = -16, // Reserved, do not change + [21] = -16, // Reserved, do not change + [22] = -16, // Reserved, do not change + [23] = -32, // Reserved, do not change + [24] = -32, // Reserved, do not change + [25] = -32, // Reserved, do not change + + [26] = 225, // spur_freq_cfg, spur_freq=spur_freq_cfg/spur_freq_cfg_div + [27] = 10, // spur_freq_cfg_div + // each bit for 1 channel, 1 to select the spur_freq if in band, else 40 + [28] = 0, // spur_freq_en_h + [29] = 0, // spur_freq_en_l + + [30] = 0xf8, // Reserved, do not change + [31] = 0, // Reserved, do not change + [32] = 0xf8, // Reserved, do not change + [33] = 0xf8, // Reserved, do not change + + [34] = 82, // target_power_qdb_0, 82 means target power is 82/4=20.5dbm + [35] = 78, // target_power_qdb_1, 78 means target power is 78/4=19.5dbm + [36] = 74, // target_power_qdb_2, 74 means target power is 74/4=18.5dbm + [37] = 68, // target_power_qdb_3, 68 means target power is 68/4=17dbm + [38] = 64, // target_power_qdb_4, 64 means target power is 64/4=16dbm + [39] = 56, // target_power_qdb_5, 56 means target power is 56/4=14dbm + + [40] = 0, // target_power_index_mcs0 + [41] = 0, // target_power_index_mcs1 + [42] = 1, // target_power_index_mcs2 + [43] = 1, // target_power_index_mcs3 + [44] = 2, // target_power_index_mcs4 + [45] = 3, // target_power_index_mcs5 + [46] = 4, // target_power_index_mcs6 + [47] = 5, // target_power_index_mcs7 + + // crystal_26m_en + // 0: 40MHz + // 1: 26MHz + // 2: 24MHz + [48] = 1, + + + + // sdio_configure + // 0: Auto by pin strapping + // 1: SDIO dataoutput is at negative edges (SDIO V1.1) + // 2: SDIO dataoutput is at positive edges (SDIO V2.0) + [50] = 0, + + // bt_configure + // 0: None,no bluetooth + // 1: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + // MTMS -> BT_ACTIVE + // MTCK -> BT_PRIORITY + // U0RXD -> ANT_SEL_BT + // 2: None, have bluetooth + // 3: GPIO0 -> WLAN_ACTIVE/ANT_SEL_WIFI + // MTMS -> BT_PRIORITY + // MTCK -> BT_ACTIVE + // U0RXD -> ANT_SEL_BT + [51] = 0, + + // bt_protocol + // 0: WiFi-BT are not enabled. Antenna is for WiFi + // 1: WiFi-BT are not enabled. Antenna is for BT + // 2: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), independent ant + // 3: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), independent ant + // 4: WiFi-BT 2-wire are enabled, (only use BT_ACTIVE), share ant + // 5: WiFi-BT 3-wire are enabled, (when BT_ACTIVE = 0, BT_PRIORITY must be 0), share ant + [52] = 0, + + // dual_ant_configure + // 0: None + // 1: dual_ant (antenna diversity for WiFi-only): GPIO0 + U0RXD + // 2: T/R switch for External PA/LNA: GPIO0 is high and U0RXD is low during Tx + // 3: T/R switch for External PA/LNA: GPIO0 is low and U0RXD is high during Tx + [53] = 0, + + [54] = 2, // Reserved, do not change + + // share_xtal + // This option is to share crystal clock for BT + // The state of Crystal during sleeping + // 0: Off + // 1: Forcely On + // 2: Automatically On according to XPD_DCDC + // 3: Automatically On according to GPIO2 + [55] = 0, + + [64] = 225, // spur_freq_cfg_2, spur_freq_2=spur_freq_cfg_2/spur_freq_cfg_div_2 + [65] = 10, // spur_freq_cfg_div_2 + [66] = 0, // spur_freq_en_h_2 + [67] = 0, // spur_freq_en_l_2 + [68] = 0, // spur_freq_cfg_msb + [69] = 0, // spur_freq_cfg_2_msb + [70] = 0, // spur_freq_cfg_3_low + [71] = 0, // spur_freq_cfg_3_high + [72] = 0, // spur_freq_cfg_4_low + [73] = 0, // spur_freq_cfg_4_high + + [74] = 1, // Reserved, do not change + [75] = 0x93, // Reserved, do not change + [76] = 0x43, // Reserved, do not change + [77] = 0x00, // Reserved, do not change + + // low_power_en + // 0: disable low power mode + // 1: enable low power mode + [93] = 0, + + // lp_rf_stg10 + // the attenuation of RF gain stage 0 and 1, + // 0xf: 0db, + // 0xe: -2.5db, + // 0xd: -6db, + // 0x9: -8.5db, + // 0xc: -11.5db, + // 0x8: -14db, + // 0x4: -17.5, + // 0x0: -23 + [94] = 0x0f, + + + // lp_bb_att_ext + // the attenuation of BB gain, + // 0: 0db, + // 1: -0.25db, + // 2: -0.5db, + // 3: -0.75db, + // 4: -1db, + // 5: -1.25db, + // 6: -1.5db, + // 7: -1.75db, + // 8: -2db + // max valve is 24(-6db) + [95] = 0, + + // pwr_ind_11b_en + // 0: 11b power is same as mcs0 and 6m + // 1: enable 11b power different with ofdm + [96] = 0, + + // pwr_ind_11b_0 + // 1m, 2m power index [0~5] + [97] = 0, + + // pwr_ind_11b_1 + // 5.5m, 11m power index [0~5] + [98] = 0, + + // vdd33_const + // the voltage of PA_VDD + // x=0xff: it can measure VDD33, + // 18<=x<=36: use input voltage, + // the value is voltage*10, 33 is 3.3V, 30 is 3.0V, + // x<18 or x>36: default voltage is 3.3V + [107] = 33, + + // disable RF calibration for certain number of times + [108] = 0, + + // freq_correct_en + // bit[0]:0->do not correct frequency offset, 1->correct frequency offset. + // bit[1]:0->bbpll is 168M, it can correct + and - frequency offset, 1->bbpll is 160M, it only can correct + frequency offset + // bit[2]:0->auto measure frequency offset and correct it, 1->use 113 byte force_freq_offset to correct frequency offset. + // 0: do not correct frequency offset. + // 1: auto measure frequency offset and correct it, bbpll is 168M, it can correct + and - frequency offset. + // 3: auto measure frequency offset and correct it, bbpll is 160M, it only can correct + frequency offset. + // 5: use 113 byte force_freq_offset to correct frequency offset, bbpll is 168M, it can correct + and - frequency offset. + // 7: use 113 byte force_freq_offset to correct frequency offset, bbpll is 160M , it only can correct + frequency offset. + [112] = 0, + + // force_freq_offset + // signed, unit is 8kHz + [113] = 0, +}; + +extern int __real_register_chipv6_phy(uint8_t* init_data); +extern int __wrap_register_chipv6_phy(uint8_t* unused) { + return __real_register_chipv6_phy(phy_init_data); +} + + +void user_rf_pre_init() { + // *((volatile uint32_t*) 0x60000710) = 0; + + volatile uint32_t* rtc_reg = (volatile uint32_t*) 0x60001000; + rtc_reg[30] = 0; + + system_set_os_print(0); +} + +extern int __get_rf_mode() __attribute__((weak)); +extern int __get_rf_mode() +{ + return 0; // default mode +} + + + + diff --git a/platform.txt b/platform.txt index bbcc580cf..bf3b930b5 100644 --- a/platform.txt +++ b/platform.txt @@ -21,7 +21,8 @@ compiler.c.flags=-c -Os -g -Wpointer-arith -Wno-implicit-function-declaration -W compiler.S.cmd=xtensa-lx106-elf-gcc compiler.S.flags=-c -g -x assembler-with-cpp -MMD -compiler.c.elf.flags=-g -Os -nostdlib -Wl,--no-check-sections -u call_user_start -Wl,-static "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" "-T{build.flash_ld}" -Wl,-wrap,system_restart_local +compiler.c.elf.flags=-g -Os -nostdlib -Wl,--no-check-sections -u call_user_start -Wl,-static "-L{compiler.sdk.path}/lib" "-L{compiler.sdk.path}/ld" "-T{build.flash_ld}" -Wl,-wrap,system_restart_local -Wl,-wrap,register_chipv6_phy + compiler.c.elf.cmd=xtensa-lx106-elf-gcc compiler.c.elf.libs=-lm -lgcc -lhal -lphy -lnet80211 -llwip -lwpa -lmain -lpp -lsmartconfig