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https://github.com/esp8266/Arduino.git
synced 2025-04-19 23:22:16 +03:00
use a function to calculate best match clock register for SPI
TEST: Frequency: 1000000 -> [0x009C1001] EQU: 0 Pre: 39 N: 1 H: 0 L: 1 - Back Calculated Frequency: 1000000 Frequency: 4000000 -> [0x00001001] EQU: 0 Pre: 0 N: 1 H: 0 L: 1 - Back Calculated Frequency: 40000000 Frequency: 2000000 -> [0x00041001] EQU: 0 Pre: 1 N: 1 H: 0 L: 1 - Back Calculated Frequency: 20000000 Frequency: 1600000 -> [0x00004002] EQU: 0 Pre: 0 N: 4 H: 0 L: 2 - Back Calculated Frequency: 16000000 Frequency: 1610000 -> [0x00004002] EQU: 0 Pre: 0 N: 4 H: 0 L: 2 - Back Calculated Frequency: 16000000 Frequency: 1000000 -> [0x000C1001] EQU: 0 Pre: 3 N: 1 H: 0 L: 1 - Back Calculated Frequency: 10000000 Frequency: 8000000 -> [0x00101001] EQU: 0 Pre: 4 N: 1 H: 0 L: 1 - Back Calculated Frequency: 8000000 Frequency: 5000000 -> [0x001C1001] EQU: 0 Pre: 7 N: 1 H: 0 L: 1 - Back Calculated Frequency: 5000000 Frequency: 4000000 -> [0x00241001] EQU: 0 Pre: 9 N: 1 H: 0 L: 1 - Back Calculated Frequency: 4000000 Frequency: 2000000 -> [0x004C1001] EQU: 0 Pre: 19 N: 1 H: 0 L: 1 - Back Calculated Frequency: 2000000 Frequency: 1000000 -> [0x009C1001] EQU: 0 Pre: 39 N: 1 H: 0 L: 1 - Back Calculated Frequency: 1000000 Frequency: 500000 -> [0x013C1001] EQU: 0 Pre: 79 N: 1 H: 0 L: 1 - Back Calculated Frequency: 500000 Frequency: 250000 -> [0x027C1001] EQU: 0 Pre: 159 N: 1 H: 0 L: 1 - Back Calculated Frequency: 250000 Frequency: 125000 -> [0x04FC1001] EQU: 0 Pre: 319 N: 1 H: 0 L: 1 - Back Calculated Frequency: 125000 Frequency: 6666666 -> [0x00141001] EQU: 0 Pre: 5 N: 1 H: 0 L: 1 - Back Calculated Frequency: 6666666 Frequency: 6000000 -> [0x00181001] EQU: 0 Pre: 6 N: 1 H: 0 L: 1 - Back Calculated Frequency: 5714285 Frequency: 3000000 -> [0x00202001] EQU: 0 Pre: 8 N: 2 H: 0 L: 1 - Back Calculated Frequency: 2962962 Frequency: 100 -> [0x7FFFF020] EQU: 0 Pre: 8191 N: 63 H: 0 L: 32 - Back Calculated Frequency: 152 Frequency: 125000 -> [0x04FC1001] EQU: 0 Pre: 319 N: 1 H: 0 L: 1 - Back Calculated Frequency: 125000 Frequency: 16457 -> [0x25F81001] EQU: 0 Pre: 2430 N: 1 H: 0 L: 1 - Back Calculated Frequency: 16454
This commit is contained in:
Markus Sattler
parent
49fc1980fe
commit
d7a88c3ea3
@ -22,39 +22,16 @@
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#include "SPI.h"
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#include "SPI.h"
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#include "HardwareSerial.h"
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#include "HardwareSerial.h"
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typedef struct {
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typedef union {
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uint32_t divider;
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uint32_t regValue;
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union {
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struct {
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uint32_t regValue;
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unsigned regL :6;
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struct {
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unsigned regH :6;
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unsigned regL :6;
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unsigned regN :6;
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unsigned regH :6;
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unsigned regPre :13;
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unsigned regN :6;
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unsigned regEQU :1;
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unsigned regPre :13;
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unsigned regEQU :1;
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};
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};
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};
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} spiClockDiv_t;
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} spiClk_t;
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// todo find way of calculation for the divider
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static const spiClockDiv_t spiClockDiv[] = {
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{ 0, (0x80000000) }, ///< [0] EQU: 1 Pre: 0 N: 0 H: 0 L: 0 Div: 0 @80Mhz = 80 MHz @160Mhz = 160 MHz
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{ 2, (0x00001001) }, ///< [1] EQU: 0 Pre: 0 N: 1 H: 0 L: 1 Div: 2 @80Mhz = 40 MHz @160Mhz = 80 MHz
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{ 4, (0x00041001) }, ///< [2] EQU: 0 Pre: 1 N: 1 H: 0 L: 1 Div: 4 @80Mhz = 20 MHz @160Mhz = 40 MHz
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{ 6, (0x000fffc0) }, ///< [3] EQU: 0 Pre: 3 N: 63 H: 63 L: 0 Div: 6 @80Mhz = 16 MHz @160Mhz = 32 MHz
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{ 8, (0x000c1001) }, ///< [4] EQU: 0 Pre: 3 N: 1 H: 0 L: 1 Div: 8 @80Mhz = 10 MHz @160Mhz = 20 MHz
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{ 10, (0x00101001) }, ///< [5] EQU: 0 Pre: 4 N: 1 H: 0 L: 1 Div: 10 @80Mhz = 8 MHz @160Mhz = 16 MHz
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{ 16, (0x001c1001) }, ///< [6] EQU: 0 Pre: 7 N: 1 H: 0 L: 1 Div: 16 @80Mhz = 5 MHz @160Mhz = 10 MHz
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{ 20, (0x00241001) }, ///< [7] EQU: 0 Pre: 9 N: 1 H: 0 L: 1 Div: 20 @80Mhz = 4 MHz @160Mhz = 8 MHz
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{ 40, (0x004c1001) }, ///< [8] EQU: 0 Pre: 19 N: 1 H: 0 L: 1 Div: 40 @80Mhz = 2 MHz @160Mhz = 4 MHz
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{ 80, (0x009c1001) }, ///< [9] EQU: 0 Pre: 39 N: 1 H: 0 L: 1 Div: 80 @80Mhz = 1 MHz @160Mhz = 2 MHz
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{ 160, (0x013c1001) }, ///< [10] EQU: 0 Pre: 79 N: 1 H: 0 L: 1 Div: 160 @80Mhz = 500 KHz @160Mhz = 1 MHz
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{ 320, (0x027c1001) }, ///< [11] EQU: 0 Pre: 159 N: 1 H: 0 L: 1 Div: 320 @80Mhz = 250 KHz @160Mhz = 500 KHz
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{ 640, (0x04fc1001) } ///< [12] EQU: 0 Pre: 319 N: 1 H: 0 L: 1 Div: 640 @80Mhz = 125 KHz @160Mhz = 250 KHz
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};
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static const uint8_t spiClockDiv_count = (sizeof(spiClockDiv) / sizeof(spiClockDiv_t));
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SPIClass SPI;
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SPIClass SPI;
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@ -65,15 +42,10 @@ void SPIClass::begin() {
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pinMode(SCK, SPECIAL); ///< GPIO14
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pinMode(SCK, SPECIAL); ///< GPIO14
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pinMode(MISO, SPECIAL); ///< GPIO12
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pinMode(MISO, SPECIAL); ///< GPIO12
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pinMode(MOSI, SPECIAL); ///< GPIO13
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pinMode(MOSI, SPECIAL); ///< GPIO13
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/*
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for(uint8_t i = 0; i < (spiClockDiv_count); i++) {
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os_printf("[%d]\t EQU: %d\t Pre: %d\t N: %d\t H: %d\t L: %d\t Div: %d - %d\n", i, spiClockDiv[i].regEQU, spiClockDiv[i].regPre, spiClockDiv[i].regN, spiClockDiv[i].regH, spiClockDiv[i].regL, spiClockDiv[i].divider );
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}
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*/
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GPMUX = 0x105; // note crash if SPI flash Frequency < 40MHz
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GPMUX = 0x105; // note crash if SPI flash Frequency < 40MHz
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SPI1C = 0;
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SPI1C = 0;
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setFrequency(1000000); ///< 1Mhz
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setFrequency(1000000); ///< 1MHz
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SPI1U = SPIUMOSI | SPIUDUPLEX | SPIUSSE;
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SPI1U = SPIUMOSI | SPIUDUPLEX | SPIUSSE;
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SPI1U1 = (7 << SPILMOSI) | (7 << SPILMISO);
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SPI1U1 = (7 << SPILMOSI) | (7 << SPILMISO);
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SPI1C1 = 0;
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SPI1C1 = 0;
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@ -96,15 +68,15 @@ void SPIClass::endTransaction() {
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void SPIClass::setDataMode(uint8_t dataMode) {
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void SPIClass::setDataMode(uint8_t dataMode) {
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/**
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/**
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SPI_MODE0 0x00 - CPOL: 0 CPHA: 0
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SPI_MODE0 0x00 - CPOL: 0 CPHA: 0
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SPI_MODE1 0x01 - CPOL: 0 CPHA: 1
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SPI_MODE1 0x01 - CPOL: 0 CPHA: 1
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SPI_MODE2 0x10 - CPOL: 1 CPHA: 0
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SPI_MODE2 0x10 - CPOL: 1 CPHA: 0
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SPI_MODE3 0x11 - CPOL: 1 CPHA: 1
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SPI_MODE3 0x11 - CPOL: 1 CPHA: 1
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*/
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*/
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bool CPOL = (dataMode&0x10); ///< CPOL (Clock Polarity)
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bool CPOL = (dataMode & 0x10); ///< CPOL (Clock Polarity)
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bool CPHA = (dataMode&0x01); ///< CPHA (Clock Phase)
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bool CPHA = (dataMode & 0x01); ///< CPHA (Clock Phase)
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if(CPHA) {
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if(CPHA) {
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SPI1U |= (SPIUSME);
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SPI1U |= (SPIUSME);
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@ -126,17 +98,92 @@ void SPIClass::setBitOrder(uint8_t bitOrder) {
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}
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}
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}
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}
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/**
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* calculate the Frequency based on the register value
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* @param reg
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* @return
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*/
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static uint32_t ClkRegToFreq(spiClk_t * reg) {
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return (F_CPU / ((reg->regPre + 1) * (reg->regN + 1)));
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}
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void SPIClass::setFrequency(uint32_t freq) {
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void SPIClass::setFrequency(uint32_t freq) {
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uint8_t i = 0;
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static uint32_t lastSetFrequency = 0;
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static uint32_t lastSetRegister = 0;
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if(freq >= F_CPU) {
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setClockDivider(0x80000000);
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return;
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}
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if(lastSetFrequency == freq && lastSetRegister == SPI1CLK) {
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// do nothing (speed optimization)
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return;
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}
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const spiClk_t minFreqReg = { 0x7FFFF000 };
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uint32_t minFreq = ClkRegToFreq((spiClk_t*) &minFreqReg);
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if(freq < minFreq) {
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freq = minFreq;
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}
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uint8_t calN = 1;
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spiClk_t bestReg = { 0 };
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int32_t bestFreq = 0;
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// find the best match
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// find the best match
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if(freq < F_CPU) {
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while(calN <= 0x3F) { // 0x3F max for N
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for(i = 1; i < (spiClockDiv_count-1); i++) {
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if(freq >= (F_CPU/spiClockDiv[i].divider)) {
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spiClk_t reg = { 0 };
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int32_t calFreq;
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int32_t calPre;
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int8_t calPreVari = -2;
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reg.regN = calN;
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while(calPreVari++ <= 1) { // test different variants for Pre (we calculate in int so we miss the decimals, testing is the easyest and fastest way)
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calPre = (((F_CPU / (reg.regN + 1)) / freq) - 1) + calPreVari;
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if(calPre > 0x1FFF) {
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reg.regPre = 0x1FFF; // 8191
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} else if(calPre <= 0) {
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reg.regPre = 0;
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} else {
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reg.regPre = calPre;
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}
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reg.regL = ((reg.regN + 1) / 2);
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// reg.regH = (reg.regN - reg.regL);
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// test calculation
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calFreq = ClkRegToFreq(®);
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//os_printf("-----[0x%08X][%d]\t EQU: %d\t Pre: %d\t N: %d\t H: %d\t L: %d = %d\n", reg.regValue, freq, reg.regEQU, reg.regPre, reg.regN, reg.regH, reg.regL, calFreq);
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if(calFreq == (int32_t) freq) {
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// accurate match use it!
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memcpy(&bestReg, ®, sizeof(bestReg));
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break;
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break;
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} else if(calFreq < (int32_t) freq) {
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// never go over the requested frequency
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if(abs(freq - calFreq) < abs(freq - bestFreq)) {
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bestFreq = calFreq;
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memcpy(&bestReg, ®, sizeof(bestReg));
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}
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}
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}
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}
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}
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if(calFreq == (int32_t) freq) {
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// accurate match use it!
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break;
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}
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calN++;
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}
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}
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setClockDivider(spiClockDiv[i].regValue);
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// os_printf("[0x%08X][%d]\t EQU: %d\t Pre: %d\t N: %d\t H: %d\t L: %d\t - Real Frequency: %d\n", bestReg.regValue, freq, bestReg.regEQU, bestReg.regPre, bestReg.regN, bestReg.regH, bestReg.regL, ClkRegToFreq(&bestReg));
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setClockDivider(bestReg.regValue);
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lastSetRegister = SPI1CLK;
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lastSetFrequency = freq;
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}
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}
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void SPIClass::setClockDivider(uint32_t clockDiv) {
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void SPIClass::setClockDivider(uint32_t clockDiv) {
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@ -144,10 +191,12 @@ void SPIClass::setClockDivider(uint32_t clockDiv) {
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}
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}
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uint8_t SPIClass::transfer(uint8_t data) {
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uint8_t SPIClass::transfer(uint8_t data) {
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while(SPI1CMD & SPIBUSY);
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while(SPI1CMD & SPIBUSY)
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;
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SPI1W0 = data;
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SPI1W0 = data;
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SPI1CMD |= SPIBUSY;
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SPI1CMD |= SPIBUSY;
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while(SPI1CMD & SPIBUSY);
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while(SPI1CMD & SPIBUSY)
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;
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return (uint8_t) (SPI1W0 & 0xff);
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return (uint8_t) (SPI1W0 & 0xff);
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}
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}
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