From cc0a8ead55ce756103ff47146cdbd499cd1a2d77 Mon Sep 17 00:00:00 2001 From: Christopher Pascoe Date: Sun, 6 Dec 2015 21:03:05 -0800 Subject: [PATCH] Always arm the "TX FIFO Empty" interrupt after we write into _tx_buffer. This avoids a race where the interrupt handler detects an empty _tx_buffer just before we write data into it. Note that commit d6f62943d4b511e7d5fe6147096c8979890416f5 works around this race when data is continually added to _tx_buffer in the hung state. We revert that change here as the race should no longer occur. Testing performed: - set UART_CONF1.txfifo_empty_thrhd=0x70 (which exacerbates the issue) - generate a ~240 byte burst of data, sent in back-to-back Serial1.write(, 4) calls, optionally followed by a Serial1.flush() Test results: - before this change, observe occasional unsent data and hang in flush() (if used). - after this change, data is sent as expected. --- cores/esp8266/HardwareSerial.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/cores/esp8266/HardwareSerial.cpp b/cores/esp8266/HardwareSerial.cpp index 2e93f8aee..78108bee7 100644 --- a/cores/esp8266/HardwareSerial.cpp +++ b/cores/esp8266/HardwareSerial.cpp @@ -617,18 +617,15 @@ size_t HardwareSerial::write(uint8_t c) { size_t room = uart_get_tx_fifo_room(_uart); if(room > 0 && _tx_buffer->empty()) { uart_transmit_char(_uart, c); - if(room < 10) { - uart_arm_tx_interrupt(_uart); - } return 1; } while(_tx_buffer->room() == 0) { yield(); - uart_arm_tx_interrupt(_uart); } _tx_buffer->write(c); + uart_arm_tx_interrupt(_uart); return 1; }