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mirror of https://github.com/esp8266/Arduino.git synced 2025-06-17 22:23:10 +03:00

[sam] PIO and PMC drivers adapted to enable SAM3U compilation, makefiles prepared for SAM3U-EK and Due

This commit is contained in:
Thibaut VIARD
2011-09-12 18:01:48 +02:00
parent 5d92281c3c
commit bc253722a6
9 changed files with 137 additions and 72 deletions

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@ -1,8 +1,8 @@
# Makefile for compiling libArduino # Makefile for compiling libArduino
.SUFFIXES: .o .a .c .s .SUFFIXES: .o .a .c .s
CHIP=__SAM3S4C__ CHIP=__SAM3U4E__
VARIANT=sam3s_ek VARIANT=arduino_due
LIBNAME=libarduino_$(VARIANT) LIBNAME=libarduino_$(VARIANT)
TOOLCHAIN=gcc TOOLCHAIN=gcc

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@ -1,8 +1,8 @@
# Makefile for compiling libArduino # Makefile for compiling libArduino
.SUFFIXES: .o .a .c .s .SUFFIXES: .o .a .c .s
CHIP=__SAM3S4C__ CHIP=__SAM3U4E__
VARIANT=sam3s_ek VARIANT=sam3u_ek
LIBNAME=libarduino_$(VARIANT) LIBNAME=libarduino_$(VARIANT)
TOOLCHAIN=gcc TOOLCHAIN=gcc

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@ -11,22 +11,34 @@ all: libsam_sam3s4c_gcc_dbg.a libsam_sam3u4e_gcc_dbg.a
.PHONY: libsam_sam3s4c_gcc_dbg.a .PHONY: libsam_sam3s4c_gcc_dbg.a
libsam_sam3s4c_gcc_dbg.a: libsam_sam3s4c_gcc_dbg.a:
@echo ---
@echo ---
@echo --- Making $@ @echo --- Making $@
@echo ---
@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk @$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
.PHONY: libsam_sam3s4c_gcc_rel.a .PHONY: libsam_sam3s4c_gcc_rel.a
libsam_sam3s4c_gcc_rel.a: libsam_sam3s4c_gcc_rel.a:
@echo ---
@echo ---
@echo --- Making $@ @echo --- Making $@
@echo ---
@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk @$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk
.PHONY: libsam_sam3u4e_gcc_dbg.a .PHONY: libsam_sam3u4e_gcc_dbg.a
libsam_sam3u4e_gcc_dbg.a: libsam_sam3u4e_gcc_dbg.a:
@echo ---
@echo ---
@echo --- Making $@ @echo --- Making $@
@echo ---
@$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk @$(MAKE) CHIP=__SAM3U4E__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
.PHONY: libsam_sam3u4e_gcc_rel.a .PHONY: libsam_sam3u4e_gcc_rel.a
libsam_sam3u4e_gcc_rel.a: libsam_sam3u4e_gcc_rel.a:
@echo ---
@echo ---
@echo --- Making $@ @echo --- Making $@
@echo ---
@$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk @$(MAKE) CHIP=__SAM3U4E__ $(SUBMAKE_OPTIONS) -f sam3.mk
.PHONY: clean .PHONY: clean

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@ -94,7 +94,7 @@ C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/source/templates/gcc/*.c)
C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC))) C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC)))
# during development, remove some files # during development, remove some files
C_OBJ_FILTER=pio_it.o C_OBJ_FILTER=pio_it.o adc.o
C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP)) C_OBJ=$(filter-out $(C_OBJ_FILTER), $(C_OBJ_TEMP))

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@ -15,9 +15,7 @@
/* $asf_license$ */ /* $asf_license$ */
#include "system_sam3u.h" #include "sam3.h"
#include "sam3u.h"
#include "sam3u_ek.h"
/* @cond 0 */ /* @cond 0 */
/**INDENT-OFF**/ /**INDENT-OFF**/

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@ -21,8 +21,10 @@ typedef enum _EPioType
PIO_NOT_A_PIN, /* The pin is controlled by the associated signal of peripheral A. */ PIO_NOT_A_PIN, /* The pin is controlled by the associated signal of peripheral A. */
PIO_PERIPH_A, /* The pin is controlled by the associated signal of peripheral A. */ PIO_PERIPH_A, /* The pin is controlled by the associated signal of peripheral A. */
PIO_PERIPH_B, /* The pin is controlled by the associated signal of peripheral B. */ PIO_PERIPH_B, /* The pin is controlled by the associated signal of peripheral B. */
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
PIO_PERIPH_C, /* The pin is controlled by the associated signal of peripheral C. */ PIO_PERIPH_C, /* The pin is controlled by the associated signal of peripheral C. */
PIO_PERIPH_D, /* The pin is controlled by the associated signal of peripheral D. */ PIO_PERIPH_D, /* The pin is controlled by the associated signal of peripheral D. */
#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
PIO_INPUT, /* The pin is an input. */ PIO_INPUT, /* The pin is an input. */
PIO_OUTPUT_0, /* The pin is an output and has a default level of 0. */ PIO_OUTPUT_0, /* The pin is an output and has a default level of 0. */
PIO_OUTPUT_1 /* The pin is an output and has a default level of 1. */ PIO_OUTPUT_1 /* The pin is an output and has a default level of 1. */

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@ -21,9 +21,6 @@
extern void PMC_EnablePeripheral( uint32_t dwId ) ; extern void PMC_EnablePeripheral( uint32_t dwId ) ;
extern void PMC_DisablePeripheral( uint32_t dwId ) ; extern void PMC_DisablePeripheral( uint32_t dwId ) ;
extern void PMC_EnableAllPeripherals( void ) ;
extern void PMC_DisableAllPeripherals( void ) ;
extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ; extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ;
#ifdef __cplusplus #ifdef __cplusplus

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@ -50,7 +50,13 @@ extern void PIO_PullUp( Pio *pPio, const uint32_t dwMask, const uint32_t dwPullU
*/ */
extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff ) extern void PIO_SetDebounceFilter( Pio* pPio, const uint32_t dwMask, const uint32_t dwCuttOff )
{ {
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
pPio->PIO_IFSCER = dwMask ; /* set Debouncing, 0 bit field no effect */ pPio->PIO_IFSCER = dwMask ; /* set Debouncing, 0 bit field no effect */
#elif (defined _SAM3XA_) || (defined _SAM3U_)
pPio->PIO_DIFSR = dwMask ; /* set Debouncing, 0 bit field no effect */
#else
#error "The specified chip is not supported."
#endif
pPio->PIO_SCDR = ((32678/(2*(dwCuttOff))) - 1) & 0x3FFF; /* the lowest 14 bits work */ pPio->PIO_SCDR = ((32678/(2*(dwCuttOff))) - 1) & 0x3FFF; /* the lowest 14 bits work */
} }
@ -121,7 +127,7 @@ extern void PIO_Clear( Pio* pPio, const uint32_t dwMask )
*/ */
extern void PIO_SetPeripheral( Pio* pPio, EPioType dwType, uint32_t dwMask ) extern void PIO_SetPeripheral( Pio* pPio, EPioType dwType, uint32_t dwMask )
{ {
uint32_t dwABCDSR ; uint32_t dwSR ;
/* Disable interrupts on the pin(s) */ /* Disable interrupts on the pin(s) */
pPio->PIO_IDR = dwMask ; pPio->PIO_IDR = dwMask ;
@ -129,36 +135,52 @@ extern void PIO_SetPeripheral( Pio* pPio, EPioType dwType, uint32_t dwMask )
switch ( dwType ) switch ( dwType )
{ {
case PIO_PERIPH_A : case PIO_PERIPH_A :
dwABCDSR = pPio->PIO_ABCDSR[0] ; #if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
pPio->PIO_ABCDSR[0] &= (~dwMask & dwABCDSR) ; dwSR = pPio->PIO_ABCDSR[0] ;
pPio->PIO_ABCDSR[0] &= (~dwMask & dwSR) ;
dwABCDSR = pPio->PIO_ABCDSR[1]; dwSR = pPio->PIO_ABCDSR[1];
pPio->PIO_ABCDSR[1] &= (~dwMask & dwABCDSR) ; pPio->PIO_ABCDSR[1] &= (~dwMask & dwSR) ;
#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
#if (defined _SAM3U_) || (defined _SAM3XA_)
dwSR = pPio->PIO_ABSR ;
pPio->PIO_ABSR &= (~dwMask & dwSR) ;
#endif /* (defined _SAM3U_) || (defined _SAM3XA_) */
break ; break ;
case PIO_PERIPH_B : case PIO_PERIPH_B :
dwABCDSR = pPio->PIO_ABCDSR[0] ; #if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
pPio->PIO_ABCDSR[0] = (dwMask | dwABCDSR) ; dwSR = pPio->PIO_ABCDSR[0] ;
pPio->PIO_ABCDSR[0] = (dwMask | dwSR) ;
dwABCDSR = pPio->PIO_ABCDSR[1] ; dwSR = pPio->PIO_ABCDSR[1] ;
pPio->PIO_ABCDSR[1] &= (~dwMask & dwABCDSR) ; pPio->PIO_ABCDSR[1] &= (~dwMask & dwSR) ;
#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
#if (defined _SAM3U_) || (defined _SAM3XA_)
dwSR = pPio->PIO_ABSR ;
pPio->PIO_ABSR = (dwMask | dwSR) ;
#endif /* (defined _SAM3U_) || (defined _SAM3XA_) */
break ; break ;
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
case PIO_PERIPH_C : case PIO_PERIPH_C :
dwABCDSR = pPio->PIO_ABCDSR[0] ; dwSR = pPio->PIO_ABCDSR[0] ;
pPio->PIO_ABCDSR[0] &= (~dwMask & dwABCDSR) ; pPio->PIO_ABCDSR[0] &= (~dwMask & dwSR) ;
dwABCDSR = pPio->PIO_ABCDSR[1] ; dwSR = pPio->PIO_ABCDSR[1] ;
pPio->PIO_ABCDSR[1] = (dwMask | dwABCDSR) ; pPio->PIO_ABCDSR[1] = (dwMask | dwSR) ;
break ; break ;
case PIO_PERIPH_D : case PIO_PERIPH_D :
dwABCDSR = pPio->PIO_ABCDSR[0] ; dwSR = pPio->PIO_ABCDSR[0] ;
pPio->PIO_ABCDSR[0] = (dwMask | dwABCDSR) ; pPio->PIO_ABCDSR[0] = (dwMask | dwSR) ;
dwABCDSR = pPio->PIO_ABCDSR[1] ; dwSR = pPio->PIO_ABCDSR[1] ;
pPio->PIO_ABCDSR[1] = (dwMask | dwABCDSR) ; pPio->PIO_ABCDSR[1] = (dwMask | dwSR) ;
break ; break ;
#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
// other types are invalid in this function // other types are invalid in this function
case PIO_INPUT : case PIO_INPUT :
@ -196,6 +218,7 @@ extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute )
} }
/* Enable de-glitch or de-bounce if necessary */ /* Enable de-glitch or de-bounce if necessary */
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
if ( dwAttribute & PIO_DEGLITCH ) if ( dwAttribute & PIO_DEGLITCH )
{ {
pPio->PIO_IFSCDR = dwMask ; pPio->PIO_IFSCDR = dwMask ;
@ -207,6 +230,21 @@ extern void PIO_SetInput( Pio* pPio, uint32_t dwMask, uint32_t dwAttribute )
pPio->PIO_IFSCER = dwMask ; pPio->PIO_IFSCER = dwMask ;
} }
} }
#elif (defined _SAM3U_) || (defined _SAM3XA_)
if ( dwAttribute & PIO_DEGLITCH )
{
pPio->PIO_SCIFSR = dwMask ;
}
else
{
if ( dwAttribute & PIO_DEBOUNCE )
{
pPio->PIO_SCIFSR = dwMask ;
}
}
#else
#error "The specified chip is not supported."
#endif
/* Configure pin as input */ /* Configure pin as input */
pPio->PIO_ODR = dwMask ; pPio->PIO_ODR = dwMask ;
@ -266,8 +304,10 @@ extern uint32_t PIO_Configure( Pio* pPio, const EPioType dwType, const uint32_t
{ {
case PIO_PERIPH_A : case PIO_PERIPH_A :
case PIO_PERIPH_B : case PIO_PERIPH_B :
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_)
case PIO_PERIPH_C : case PIO_PERIPH_C :
case PIO_PERIPH_D : case PIO_PERIPH_D :
#endif /* (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3N_) */
/* Put the pin under control of peripheral */ /* Put the pin under control of peripheral */
PIO_SetPeripheral( pPio, dwType, dwMask ) ; PIO_SetPeripheral( pPio, dwType, dwMask ) ;
/* Disable interrupts on the pin(s) */ /* Disable interrupts on the pin(s) */

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@ -31,6 +31,7 @@
*/ */
extern void PMC_EnablePeripheral( uint32_t dwId ) extern void PMC_EnablePeripheral( uint32_t dwId )
{ {
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3XA_)
assert( dwId < 35 ) ; assert( dwId < 35 ) ;
if ( dwId < 32 ) if ( dwId < 32 )
@ -56,6 +57,14 @@ extern void PMC_EnablePeripheral( uint32_t dwId )
PMC->PMC_PCER1 = 1 << dwId ; PMC->PMC_PCER1 = 1 << dwId ;
} }
} }
#elif (defined _SAM3N_) || (defined _SAM3U_)
if ( (PMC->PMC_PCSR & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) )
{
PMC->PMC_PCER = 1 << dwId ;
}
#else
#error "The specified chip is not supported."
#endif
} }
/** /**
@ -68,15 +77,12 @@ extern void PMC_EnablePeripheral( uint32_t dwId )
*/ */
extern void PMC_DisablePeripheral( uint32_t dwId ) extern void PMC_DisablePeripheral( uint32_t dwId )
{ {
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3XA_)
assert( dwId < 35 ) ; assert( dwId < 35 ) ;
if ( dwId < 32 ) if ( dwId < 32 )
{ {
if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) ) if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
{
// TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", dwId ) ;
}
else
{ {
PMC->PMC_PCDR0 = 1 << dwId ; PMC->PMC_PCDR0 = 1 << dwId ;
} }
@ -84,59 +90,69 @@ extern void PMC_DisablePeripheral( uint32_t dwId )
else else
{ {
dwId -= 32 ; dwId -= 32 ;
if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) ) if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
{
// TRACE_DEBUG( "PMC_DisablePeripheral: clock of peripheral" " %u is not enabled\n\r", dwId + 32 ) ;
}
else
{ {
PMC->PMC_PCDR1 = 1 << dwId ; PMC->PMC_PCDR1 = 1 << dwId ;
} }
} }
} #elif (defined _SAM3N_) || (defined _SAM3U_)
if ( (PMC->PMC_PCSR & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) )
/**
* \brief Enable all the periph clock via PMC.
*/
extern void PMC_EnableAllPeripherals( void )
{ {
PMC->PMC_PCER0 = MASK_STATUS0 ; PMC->PMC_PCDR = 1 << dwId ;
while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0 ) ; }
#else
PMC->PMC_PCER1 = MASK_STATUS1 ; #error "The specified chip is not supported."
while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1 ) ; #endif
// TRACE_DEBUG( "Enable all periph clocks\n\r" ) ;
} }
/** /**
* \brief Disable all the periph clock via PMC. * \brief Get the status of the specified peripheral clock.
*/
extern void PMC_DisableAllPeripherals( void )
{
PMC->PMC_PCDR0 = MASK_STATUS0 ;
while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != 0 ) ;
PMC->PMC_PCDR1 = MASK_STATUS1 ;
while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != 0 ) ;
// TRACE_DEBUG( "Disable all periph clocks\n\r" ) ;
}
/**
* \brief Get Periph Status for the given peripheral ID.
* *
* \param id Peripheral ID (ID_xxx). * \note The ID must NOT be shifted (i.e. 1 << ID_xxx).
*
* \param dwId Peripheral ID (ID_xxx).
*
* \retval 0 Clock is active.
* \retval 1 Clock is inactive.
* \retval 2 Invalid parameter.
*/ */
extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) extern uint32_t PMC_IsPeripheralEnabled( uint32_t dwId )
{ {
#if (defined _SAM3S_) || (defined _SAM3S8_) || (defined _SAM3XA_)
assert( dwId < 35 ) ; assert( dwId < 35 ) ;
if ( dwId < 32 ) if ( dwId < 32 )
{ {
return ( PMC->PMC_PCSR0 & (1 << dwId) ) ; if ( PMC->PMC_PCSR0 & (1 << dwId) )
{
return 0 ;
} }
else { else
return ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) ) ; {
return 1 ;
} }
} }
else
{
if ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) )
{
return 0 ;
}
else
{
return 1 ;
}
}
#elif (defined _SAM3N_) || (defined _SAM3U_)
if ( (PMC->PMC_PCSR & ((uint32_t)1 << dwId)) )
{
return 0 ;
}
else
{
return 1 ;
}
#else
#error "The specified chip is not supported."
#endif
}