arduino/esp8266
1
0
Fork 0
mirror of https://github.com/esp8266/Arduino.git synced 2025-10-25 18:38:07 +03:00
Code Activity

Spi slave improvments (#6580)

Browse Source 
* Status length arg in begin() added

* readable bits config

* strange line removed

* Empty constructor added

Moved custom status length init overloaded constructor

* Constructor without parameters added

* Code formatting fix

* default value in constructor removed

* default begin method forwarded to new

* Comments about bits added, else if except if
This commit is contained in:
Dmytro
2019-10-31 04:49:55 +02:00
committed by Develo
parent 9f2cfb8218
commit b4c28e74d6
3 changed files with 15 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
libraries/SPISlave/src/hspi_slave.c
View File

@@ -72,11 +72,10 @@ void ICACHE_RAM_ATTR _hspi_slave_isr_handler(void *arg)
void hspi_slave_begin(uint8_t status_len, void * arg)
{
status_len &= 7;
if(status_len > 4) {
status_len = 4; //max 32 bits
}
if(status_len == 0) {
else if(status_len == 0) {
status_len = 1; //min 8 bits
}
@@ -85,7 +84,13 @@ void hspi_slave_begin(uint8_t status_len, void * arg)
pinMode(MISO, SPECIAL);
pinMode(MOSI, SPECIAL);
SPI1S = SPISE | SPISBE | 0x3E0; // SPI_SLAVE_REG
SPI1S = SPISE | SPISBE | SPISTRIE | SPISWBIE | SPISRSIE | SPISWSIE | SPISRBIE; //(0x63E0)
//setting config bits in SPI_SLAVE_REG, defined in "esp8266_peri.h" :
//SPISE - spi slave enable
//SPISBE - allows work (read/write) with buffer, without this only? status available
//SPISTRIE - enables TRANS?? interrupt
//other SPISxxIE - enables corresponding interrupts (read(R)/write(W) status(S) and buffer(B))
SPI1U = SPIUMISOH | SPIUCOMMAND | SPIUSSE; // SPI_USER_REG
SPI1CLK = 0;
SPI1U2 = (7 << SPILCOMMAND); // SPI_USER2_REG