Merged upstream arduino branch

hardware/arduino/avr/boards.txt

@@ -120,7 +120,7 @@ mega2560.cpu=2560 or ADK
 mega2560.container=Arduino Mega
 
 mega2560.upload.tool=avrdude
-mega2560.upload.protocol=stk500v2
+mega2560.upload.protocol=wiring
 mega2560.upload.maximum_size=258048
 mega2560.upload.speed=115200
 

hardware/arduino/avr/cores/arduino/Arduino.h

@@ -46,7 +46,7 @@ extern "C"{
 #define EXTERNAL 1
 #define INTERNAL 2
 #else  
-#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1284P__) 
+#if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__)
 #define INTERNAL1V1 2
 #define INTERNAL2V56 3
 #else

hardware/arduino/avr/cores/arduino/HardwareSerial.cpp

@@ -18,6 +18,7 @@
   
   Modified 23 November 2006 by David A. Mellis
   Modified 28 September 2010 by Mark Sproul
+  Modified 14 August 2012 by Alarus
 */
 
 #include <stdlib.h>
@@ -109,13 +110,22 @@ inline void store_char(unsigned char c, ring_buffer *buffer)
 #endif
   {
   #if defined(UDR0)
-    unsigned char c  =  UDR0;
+    if (bit_is_clear(UCSR0A, UPE0)) {
+      unsigned char c = UDR0;
+      store_char(c, &rx_buffer);
+    } else {
+      unsigned char c = UDR0;
+    };
   #elif defined(UDR)
-    unsigned char c  =  UDR;
+    if (bit_is_clear(UCSRA, PE)) {
+      unsigned char c = UDR;
+      store_char(c, &rx_buffer);
+    } else {
+      unsigned char c = UDR;
+    };
   #else
     #error UDR not defined
   #endif
-    store_char(c, &rx_buffer);
   }
 #endif
 #endif
@@ -126,8 +136,12 @@ inline void store_char(unsigned char c, ring_buffer *buffer)
   #define serialEvent1_implemented
   SIGNAL(USART1_RX_vect)
   {
-    unsigned char c = UDR1;
-    store_char(c, &rx_buffer1);
+    if (bit_is_clear(UCSR1A, UPE1)) {
+      unsigned char c = UDR1;
+      store_char(c, &rx_buffer1);
+    } else {
+      unsigned char c = UDR1;
+    };
   }
 #elif defined(SIG_USART1_RECV)
   #error SIG_USART1_RECV
@@ -139,8 +153,12 @@ inline void store_char(unsigned char c, ring_buffer *buffer)
   #define serialEvent2_implemented
   SIGNAL(USART2_RX_vect)
   {
-    unsigned char c = UDR2;
-    store_char(c, &rx_buffer2);
+    if (bit_is_clear(UCSR2A, UPE2)) {
+      unsigned char c = UDR2;
+      store_char(c, &rx_buffer2);
+    } else {
+      unsigned char c = UDR2;
+    };
   }
 #elif defined(SIG_USART2_RECV)
   #error SIG_USART2_RECV
@@ -152,8 +170,12 @@ inline void store_char(unsigned char c, ring_buffer *buffer)
   #define serialEvent3_implemented
   SIGNAL(USART3_RX_vect)
   {
-    unsigned char c = UDR3;
-    store_char(c, &rx_buffer3);
+    if (bit_is_clear(UCSR3A, UPE3)) {
+      unsigned char c = UDR3;
+      store_char(c, &rx_buffer3);
+    } else {
+      unsigned char c = UDR3;
+    };
   }
 #elif defined(SIG_USART3_RECV)
   #error SIG_USART3_RECV
@@ -274,7 +296,7 @@ ISR(USART3_UDRE_vect)
 HardwareSerial::HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer,
   volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
   volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
-  volatile uint8_t *udr,
+  volatile uint8_t *ucsrc, volatile uint8_t *udr,
   uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udrie, uint8_t u2x)
 {
   _rx_buffer = rx_buffer;
@@ -283,6 +305,7 @@ HardwareSerial::HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer,
   _ubrrl = ubrrl;
   _ucsra = ucsra;
   _ucsrb = ucsrb;
+  _ucsrc = ucsrc;
   _udr = udr;
   _rxen = rxen;
   _txen = txen;
@@ -327,6 +350,55 @@ try_again:
   *_ubrrh = baud_setting >> 8;
   *_ubrrl = baud_setting;
 
+  transmitting = false;
+
+  sbi(*_ucsrb, _rxen);
+  sbi(*_ucsrb, _txen);
+  sbi(*_ucsrb, _rxcie);
+  cbi(*_ucsrb, _udrie);
+}
+
+void HardwareSerial::begin(unsigned long baud, byte config)
+{
+  uint16_t baud_setting;
+  uint8_t current_config;
+  bool use_u2x = true;
+
+#if F_CPU == 16000000UL
+  // hardcoded exception for compatibility with the bootloader shipped
+  // with the Duemilanove and previous boards and the firmware on the 8U2
+  // on the Uno and Mega 2560.
+  if (baud == 57600) {
+    use_u2x = false;
+  }
+#endif
+
+try_again:
+  
+  if (use_u2x) {
+    *_ucsra = 1 << _u2x;
+    baud_setting = (F_CPU / 4 / baud - 1) / 2;
+  } else {
+    *_ucsra = 0;
+    baud_setting = (F_CPU / 8 / baud - 1) / 2;
+  }
+  
+  if ((baud_setting > 4095) && use_u2x)
+  {
+    use_u2x = false;
+    goto try_again;
+  }
+
+  // assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register)
+  *_ubrrh = baud_setting >> 8;
+  *_ubrrl = baud_setting;
+
+  //set the data bits, parity, and stop bits
+#if defined(__AVR_ATmega8__)
+  config |= 0x80; // select UCSRC register (shared with UBRRH)
+#endif
+  *_ucsrc = config;
+  
   sbi(*_ucsrb, _rxen);
   sbi(*_ucsrb, _txen);
   sbi(*_ucsrb, _rxcie);
@@ -376,8 +448,9 @@ int HardwareSerial::read(void)
 
 void HardwareSerial::flush()
 {
-  while (_tx_buffer->head != _tx_buffer->tail)
-    ;
+  // UDR is kept full while the buffer is not empty, so TXC triggers when EMPTY && SENT
+  while (transmitting && ! (*_ucsra & _BV(TXC0)));
+  transmitting = false;
 }
 
 size_t HardwareSerial::write(uint8_t c)
@@ -394,6 +467,9 @@ size_t HardwareSerial::write(uint8_t c)
   _tx_buffer->head = i;
 	
   sbi(*_ucsrb, _udrie);
+  // clear the TXC bit -- "can be cleared by writing a one to its bit location"
+  transmitting = true;
+  sbi(*_ucsra, TXC0);
   
   return 1;
 }
@@ -405,9 +481,9 @@ HardwareSerial::operator bool() {
 // Preinstantiate Objects //////////////////////////////////////////////////////
 
 #if defined(UBRRH) && defined(UBRRL)
-  HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRRH, &UBRRL, &UCSRA, &UCSRB, &UDR, RXEN, TXEN, RXCIE, UDRIE, U2X);
+  HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRRH, &UBRRL, &UCSRA, &UCSRB, &UCSRC, &UDR, RXEN, TXEN, RXCIE, UDRIE, U2X);
 #elif defined(UBRR0H) && defined(UBRR0L)
-  HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UDR0, RXEN0, TXEN0, RXCIE0, UDRIE0, U2X0);
+  HardwareSerial Serial(&rx_buffer, &tx_buffer, &UBRR0H, &UBRR0L, &UCSR0A, &UCSR0B, &UCSR0C, &UDR0, RXEN0, TXEN0, RXCIE0, UDRIE0, U2X0);
 #elif defined(USBCON)
   // do nothing - Serial object and buffers are initialized in CDC code
 #else
@@ -415,13 +491,13 @@ HardwareSerial::operator bool() {
 #endif
 
 #if defined(UBRR1H)
-  HardwareSerial Serial1(&rx_buffer1, &tx_buffer1, &UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UDR1, RXEN1, TXEN1, RXCIE1, UDRIE1, U2X1);
+  HardwareSerial Serial1(&rx_buffer1, &tx_buffer1, &UBRR1H, &UBRR1L, &UCSR1A, &UCSR1B, &UCSR1C, &UDR1, RXEN1, TXEN1, RXCIE1, UDRIE1, U2X1);
 #endif
 #if defined(UBRR2H)
-  HardwareSerial Serial2(&rx_buffer2, &tx_buffer2, &UBRR2H, &UBRR2L, &UCSR2A, &UCSR2B, &UDR2, RXEN2, TXEN2, RXCIE2, UDRIE2, U2X2);
+  HardwareSerial Serial2(&rx_buffer2, &tx_buffer2, &UBRR2H, &UBRR2L, &UCSR2A, &UCSR2B, &UCSR2C, &UDR2, RXEN2, TXEN2, RXCIE2, UDRIE2, U2X2);
 #endif
 #if defined(UBRR3H)
-  HardwareSerial Serial3(&rx_buffer3, &tx_buffer3, &UBRR3H, &UBRR3L, &UCSR3A, &UCSR3B, &UDR3, RXEN3, TXEN3, RXCIE3, UDRIE3, U2X3);
+  HardwareSerial Serial3(&rx_buffer3, &tx_buffer3, &UBRR3H, &UBRR3L, &UCSR3A, &UCSR3B, &UCSR3C, &UDR3, RXEN3, TXEN3, RXCIE3, UDRIE3, U2X3);
 #endif
 
 #endif // whole file

hardware/arduino/avr/cores/arduino/HardwareSerial.h

@@ -17,6 +17,7 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 
   Modified 28 September 2010 by Mark Sproul
+  Modified 14 August 2012 by Alarus
 */
 
 #ifndef HardwareSerial_h
@@ -37,29 +38,62 @@ class HardwareSerial : public Stream
     volatile uint8_t *_ubrrl;
     volatile uint8_t *_ucsra;
     volatile uint8_t *_ucsrb;
+    volatile uint8_t *_ucsrc;
     volatile uint8_t *_udr;
     uint8_t _rxen;
     uint8_t _txen;
     uint8_t _rxcie;
     uint8_t _udrie;
     uint8_t _u2x;
+    bool transmitting;
   public:
     HardwareSerial(ring_buffer *rx_buffer, ring_buffer *tx_buffer,
       volatile uint8_t *ubrrh, volatile uint8_t *ubrrl,
       volatile uint8_t *ucsra, volatile uint8_t *ucsrb,
-      volatile uint8_t *udr,
+      volatile uint8_t *ucsrc, volatile uint8_t *udr,
       uint8_t rxen, uint8_t txen, uint8_t rxcie, uint8_t udrie, uint8_t u2x);
     void begin(unsigned long);
+    void begin(unsigned long, byte);
     void end();
     virtual int available(void);
     virtual int peek(void);
     virtual int read(void);
     virtual void flush(void);
     virtual size_t write(uint8_t);
+    inline size_t write(unsigned long n) { return write((uint8_t)n); }
+    inline size_t write(long n) { return write((uint8_t)n); }
+    inline size_t write(unsigned int n) { return write((uint8_t)n); }
+    inline size_t write(int n) { return write((uint8_t)n); }
     using Print::write; // pull in write(str) and write(buf, size) from Print
     operator bool();
 };
 
+// Define config for Serial.begin(baud, config);
+#define SERIAL_5N1 0x00
+#define SERIAL_6N1 0x02
+#define SERIAL_7N1 0x04
+#define SERIAL_8N1 0x06
+#define SERIAL_5N2 0x08
+#define SERIAL_6N2 0x0A
+#define SERIAL_7N2 0x0C
+#define SERIAL_8N2 0x0E
+#define SERIAL_5E1 0x20
+#define SERIAL_6E1 0x22
+#define SERIAL_7E1 0x24
+#define SERIAL_8E1 0x26
+#define SERIAL_5E2 0x28
+#define SERIAL_6E2 0x2A
+#define SERIAL_7E2 0x2C
+#define SERIAL_8E2 0x2E
+#define SERIAL_5O1 0x30
+#define SERIAL_6O1 0x32
+#define SERIAL_7O1 0x34
+#define SERIAL_8O1 0x36
+#define SERIAL_5O2 0x38
+#define SERIAL_6O2 0x3A
+#define SERIAL_7O2 0x3C
+#define SERIAL_8O2 0x3E
+
 #if defined(UBRRH) || defined(UBRR0H)
   extern HardwareSerial Serial;
 #elif defined(USBCON)
@@ -76,6 +110,22 @@ class HardwareSerial : public Stream
   extern HardwareSerial Serial3;
 #endif
 
+/*
+ * on ATmega8, the uart and its bits are not numbered, so there is no "TXC0"
+ * definition.  It is slightly cleaner to define this here instead of having
+ * conditional code in the cpp module.
+ */
+#if !defined(TXC0)
+#if defined(TXC)
+#define TXC0 TXC
+#elif defined(TXC1)
+// Some devices have uart1 but no uart0
+#define TXC0 TXC1
+#else
+#error TXC0 not definable in HardwareSerial.h
+#endif
+#endif
+
 extern void serialEventRun(void) __attribute__((weak));
 
 #endif

hardware/arduino/avr/cores/arduino/USBCore.cpp

@@ -603,7 +603,7 @@ ISR(USB_GEN_vect)
 	{
 #ifdef CDC_ENABLED
 		USB_Flush(CDC_TX);				// Send a tx frame if found
-		while (USB_Available(CDC_RX))	// Handle received bytes (if any)
+		if (USB_Available(CDC_RX))	// Handle received bytes (if any)
 			Serial.accept();
 #endif
 		

hardware/arduino/avr/cores/arduino/wiring_analog.c

@@ -45,7 +45,7 @@ int analogRead(uint8_t pin)
 	if (pin >= 54) pin -= 54; // allow for channel or pin numbers
 #elif defined(__AVR_ATmega32U4__)
 	if (pin >= 18) pin -= 18; // allow for channel or pin numbers
-#elif defined(__AVR_ATmega1284__)
+#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__)
 	if (pin >= 24) pin -= 24; // allow for channel or pin numbers
 #else
 	if (pin >= 14) pin -= 14; // allow for channel or pin numbers

hardware/arduino/avr/cores/arduino/wiring_private.h

@@ -54,7 +54,7 @@ extern "C"{
 
 #if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
 #define EXTERNAL_NUM_INTERRUPTS 8
-#elif defined(__AVR_ATmega1284P__) 
+#elif defined(__AVR_ATmega1284P__) || defined(__AVR_ATmega644P__)
 #define EXTERNAL_NUM_INTERRUPTS 3
 #elif defined(__AVR_ATmega32U4__)
 #define EXTERNAL_NUM_INTERRUPTS 4

hardware/arduino/avr/libraries/Servo/Servo.h

@@ -65,9 +65,8 @@
 typedef enum { _timer5, _timer1, _timer3, _timer4, _Nbr_16timers } timer16_Sequence_t ;
 
 #elif defined(__AVR_ATmega32U4__)  
-#define _useTimer3
 #define _useTimer1 
-typedef enum { _timer3, _timer1, _Nbr_16timers } timer16_Sequence_t ;
+typedef enum { _timer1, _Nbr_16timers } timer16_Sequence_t ;
 
 #elif defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
 #define _useTimer3
@@ -124,4 +123,4 @@ private:
    int8_t max;                       // maximum is this value times 4 added to MAX_PULSE_WIDTH   
 };
 
-#endif
+#endif

hardware/arduino/avr/variants/leonardo/pins_arduino.h

@@ -27,6 +27,69 @@
 
 #include <avr/pgmspace.h>
 
+// Workaround for wrong definitions in "iom32u4.h".
+// This should be fixed in the AVR toolchain.
+#undef UHCON
+#undef UHINT
+#undef UHIEN
+#undef UHADDR
+#undef UHFNUM
+#undef UHFNUML
+#undef UHFNUMH
+#undef UHFLEN
+#undef UPINRQX
+#undef UPINTX
+#undef UPNUM
+#undef UPRST
+#undef UPCONX
+#undef UPCFG0X
+#undef UPCFG1X
+#undef UPSTAX
+#undef UPCFG2X
+#undef UPIENX
+#undef UPDATX
+#undef TCCR2A
+#undef WGM20
+#undef WGM21
+#undef COM2B0
+#undef COM2B1
+#undef COM2A0
+#undef COM2A1
+#undef TCCR2B
+#undef CS20
+#undef CS21
+#undef CS22
+#undef WGM22
+#undef FOC2B
+#undef FOC2A
+#undef TCNT2
+#undef TCNT2_0
+#undef TCNT2_1
+#undef TCNT2_2
+#undef TCNT2_3
+#undef TCNT2_4
+#undef TCNT2_5
+#undef TCNT2_6
+#undef TCNT2_7
+#undef OCR2A
+#undef OCR2_0
+#undef OCR2_1
+#undef OCR2_2
+#undef OCR2_3
+#undef OCR2_4
+#undef OCR2_5
+#undef OCR2_6
+#undef OCR2_7
+#undef OCR2B
+#undef OCR2_0
+#undef OCR2_1
+#undef OCR2_2
+#undef OCR2_3
+#undef OCR2_4
+#undef OCR2_5
+#undef OCR2_6
+#undef OCR2_7
+
 #define TX_RX_LED_INIT	DDRD |= (1<<5), DDRB |= (1<<0)
 #define TXLED0			PORTD |= (1<<5)
 #define TXLED1			PORTD &= ~(1<<5)

hardware/arduino/firmwares/wifishield/scripts/ArduinoWifiShield_upgrade.sh

@@ -0,0 +1,96 @@
+#!/bin/sh
+
+WIFI_FW_PATH="/hardware/arduino/firmwares/wifi-shield"
+AVR_TOOLS_PATH="/hardware/tools/avr/bin"
+
+progname=$0
+
+usage () {
+cat <<EOF
+Usage: $progname [-a Arduino_path] [-f which_firmware] [-h] 
+       -a set the path where the Arduino IDE is installed
+       -f the firmware you want to upload, valid parameters are:
+	  shield  - to upgrade the WiFi shield firmware
+	  all     - to upgrade both firmwares
+       -h help
+EOF
+  exit 0
+}
+
+upgradeHDmodule () {
+  sleep 1 # Give time to the shield to end the boot
+  echo "****Upgrade HD WiFi module firmware****\n"
+  dfu-programmer at32uc3a1256 erase
+  dfu-programmer at32uc3a1256 flash --suppress-bootloader-mem $WIFI_FW_PATH/wifi_dnld.hex
+  dfu-programmer at32uc3a1256 start
+  echo -n "\nRemove the J3 jumper then press the RESET button on the shield then type [ENTER] to upgrade the firmware of the shield..\n"
+  read readEnter
+}
+
+upgradeShield () {
+  sleep 1 # Give time to the shield to end the boot
+  echo "****Upgrade WiFi Shield firmware****\n"
+  dfu-programmer at32uc3a1256 erase
+  dfu-programmer at32uc3a1256 flash --suppress-bootloader-mem $WIFI_FW_PATH/wifiHD.hex
+  dfu-programmer at32uc3a1256 start 
+  echo "\nDone. Remove the J3 jumper and press the RESET button on the shield."
+  echo "Thank you!\n"
+}
+
+cat <<EOF
+
+       Arduino WiFi Shield upgrade
+=========================================
+Disclaimer: to access to the USB devices correctly, the dfu-programmer needs to be used as root. Run this script as root.
+
+EOF
+
+if [ $USER = 'root' ] ; then  #check if the current user is root
+  while getopts ":a:f:h" opt; do
+    case $opt in
+	a)
+	  ARDUINO_PATH=$OPTARG 
+	  WIFI_FW_PATH=$ARDUINO_PATH$WIFI_FW_PATH
+	  AVR_TOOLS_PATH=$ARDUINO_PATH$AVR_TOOLS_PATH
+	  cd $AVR_TOOLS_PATH
+	  ./avr-objcopy --output-target=ihex $WIFI_FW_PATH/wifi_dnld.elf  $WIFI_FW_PATH/wifi_dnld.hex	
+	  ./avr-objcopy --output-target=ihex $WIFI_FW_PATH/wifiHD.elf  $WIFI_FW_PATH/wifiHD.hex
+	  ;;
+	f)
+	  if [ "$ARDUINO_PATH" != "" ] ; then
+	    if [ "$OPTARG" = "all" ] ; then
+	      upgradeHDmodule
+	      upgradeShield
+	      exit 0
+	    else
+	      if [ "$OPTARG" = "shield" ] ; then
+		upgradeShield
+		exit 0
+	      else
+		echo "invalid parameter for the -f [firmware] option, please retry."
+		echo "Type -h for help\n"
+		exit 1
+	      fi
+	     fi
+	  else
+	    echo "Arduino Path not setted. Retry...\n"
+	  fi
+	  ;;
+	h)
+	  usage ;; 
+	\?)
+	  echo "Invalid option: $OPTARG" >&2
+	  usage
+	  exit 1
+	  ;;
+	:)
+	  echo "Option -$OPTARG requires an argument." >&2
+	  exit 1
+	  ;;
+	esac
+  done
+else
+  echo "You are not root!\n"
+fi
+
+shift $(($OPTIND - 1))

hardware/arduino/firmwares/wifishield/scripts/ArduinoWifiShield_upgrade_mac.sh

@@ -0,0 +1,96 @@
+#!/bin/sh
+
+WIFI_FW_PATH="/hardware/arduino/firmwares/wifi-shield"
+AVR_TOOLS_PATH="/hardware/tools/avr/bin"
+
+progname=$0
+
+usage () {
+cat <<EOF
+Usage: $progname [-a Arduino_path] [-f which_firmware] [-h] 
+       -a set the path where the Arduino IDE is installed
+       -f the firmware you want to upload, valid parameters are:
+	  shield  - to upgrade the WiFi shield firmware
+	  all     - to upgrade both firmwares
+       -h help
+EOF
+  exit 0
+}
+
+upgradeHDmodule () {
+  sleep 1 # Give time to the shield to end the boot
+  echo "****Upgrade HD WiFi module firmware****\n"
+  dfu-programmer at32uc3a1256 erase
+  dfu-programmer at32uc3a1256 flash --suppress-bootloader-mem $WIFI_FW_PATH/wifi_dnld.hex
+  dfu-programmer at32uc3a1256 start
+  echo -n "\nRemove the J3 jumper then press the RESET button on the shield then type [ENTER] to upgrade the firmware of the shield..\n"
+  read readEnter
+}
+
+upgradeShield () {
+  sleep 1 # Give time to the shield to end the boot
+  echo "****Upgrade WiFi Shield firmware****\n"
+  dfu-programmer at32uc3a1256 erase
+  dfu-programmer at32uc3a1256 flash --suppress-bootloader-mem $WIFI_FW_PATH/wifiHD.hex
+  dfu-programmer at32uc3a1256 start 
+  echo "\nDone. Remove the J3 jumper and press the RESET button on the shield."
+  echo "Thank you!\n"
+}
+
+cat <<EOF
+
+       Arduino WiFi Shield upgrade
+=========================================
+Disclaimer: to access to the USB devices correctly, the dfu-programmer needs to be used as root. Run this script as root.
+
+EOF
+
+if [ $USER = 'root' ] ; then  #check if the current user is root
+  while getopts ":a:f:h" opt; do
+    case $opt in
+	a)
+	  ARDUINO_PATH=$OPTARG 
+	  WIFI_FW_PATH=$ARDUINO_PATH$WIFI_FW_PATH
+	  AVR_TOOLS_PATH=$ARDUINO_PATH$AVR_TOOLS_PATH
+	  cd $AVR_TOOLS_PATH
+	  ./avr-objcopy --output-target=ihex $WIFI_FW_PATH/wifi_dnld.elf  $WIFI_FW_PATH/wifi_dnld.hex	
+	  ./avr-objcopy --output-target=ihex $WIFI_FW_PATH/wifiHD.elf  $WIFI_FW_PATH/wifiHD.hex
+	  ;;
+	f)
+	  if [ "$ARDUINO_PATH" != "" ] ; then
+	    if [ "$OPTARG" = "all" ] ; then
+	      upgradeHDmodule
+	      upgradeShield
+	      exit 0
+	    else
+	      if [ "$OPTARG" = "shield" ] ; then
+		upgradeShield
+		exit 0
+	      else
+		echo "invalid parameter for the -f [firmware] option, please retry."
+		echo "Type -h for help\n"
+		exit 1
+	      fi
+	     fi
+	  else
+	    echo "Arduino Path not setted. Retry...\n"
+	  fi
+	  ;;
+	h)
+	  usage ;; 
+	\?)
+	  echo "Invalid option: $OPTARG" >&2
+	  usage
+	  exit 1
+	  ;;
+	:)
+	  echo "Option -$OPTARG requires an argument." >&2
+	  exit 1
+	  ;;
+	esac
+  done
+else
+  echo "You are not root!\n"
+fi
+
+shift $(($OPTIND - 1))

hardware/arduino/firmwares/wifishield/wifiHD/.project

@@ -0,0 +1,77 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>wifiHD</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/wifiHD/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>false</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.atmel.avr32.core.nature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>UC3 Software Framework</name>
+			<type>2</type>
+			<locationURI>framework:/com.atmel.avr32.sf.uc3</locationURI>
+		</link>
+	</linkedResources>
+</projectDescription>

hardware/arduino/firmwares/wifishield/wifiHD/src/CONFIG/conf_access.h

@@ -0,0 +1,170 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Memory access control configuration file.
+ *
+ * This file contains the possible external configuration of the memory access
+ * control.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _CONF_ACCESS_H_
+#define _CONF_ACCESS_H_
+
+#include "compiler.h"
+#include "board.h"
+
+
+/*! \name Activation of Logical Unit Numbers
+ */
+//! @{
+#define LUN_0                DISABLE  //!< On-Chip Virtual Memory.
+#define LUN_1                ENABLE   //!< AT45DBX Data Flash.
+#define LUN_2                DISABLE  //!< SD/MMC Card over SPI.
+#define LUN_3                DISABLE
+#define LUN_4                DISABLE
+#define LUN_5                DISABLE
+#define LUN_6                DISABLE
+#define LUN_7                DISABLE
+#define LUN_USB              DISABLE  //!< Host Mass-Storage Memory.
+//! @}
+
+/*! \name LUN 0 Definitions
+ */
+//! @{
+#define VIRTUAL_MEM                             LUN_0
+#define LUN_ID_VIRTUAL_MEM                      LUN_ID_0
+#define LUN_0_INCLUDE                           "virtual_mem.h"
+#define Lun_0_test_unit_ready                   virtual_test_unit_ready
+#define Lun_0_read_capacity                     virtual_read_capacity
+#define Lun_0_wr_protect                        virtual_wr_protect
+#define Lun_0_removal                           virtual_removal
+#define Lun_0_usb_read_10                       virtual_usb_read_10
+#define Lun_0_usb_write_10                      virtual_usb_write_10
+#define Lun_0_mem_2_ram                         virtual_mem_2_ram
+#define Lun_0_ram_2_mem                         virtual_ram_2_mem
+#define LUN_0_NAME                              "\"On-Chip Virtual Memory\""
+//! @}
+
+/*! \name LUN 1 Definitions
+ */
+//! @{
+#define AT45DBX_MEM                             LUN_1
+#define LUN_ID_AT45DBX_MEM                      LUN_ID_1
+#define LUN_1_INCLUDE                           "at45dbx_mem.h"
+#define Lun_1_test_unit_ready                   at45dbx_test_unit_ready
+#define Lun_1_read_capacity                     at45dbx_read_capacity
+#define Lun_1_wr_protect                        at45dbx_wr_protect
+#define Lun_1_removal                           at45dbx_removal
+#define Lun_1_usb_read_10                       at45dbx_usb_read_10
+#define Lun_1_usb_write_10                      at45dbx_usb_write_10
+#define Lun_1_mem_2_ram                         at45dbx_df_2_ram
+#define Lun_1_ram_2_mem                         at45dbx_ram_2_df
+#define LUN_1_NAME                              "\"AT45DBX Data Flash\""
+//! @}
+
+/*! \name LUN 2 Definitions
+ */
+//! @{
+#define SD_MMC_SPI_MEM                          LUN_2
+#define LUN_ID_SD_MMC_SPI_MEM                   LUN_ID_2
+#define LUN_2_INCLUDE                           "sd_mmc_spi_mem.h"
+#define Lun_2_test_unit_ready                   sd_mmc_spi_test_unit_ready
+#define Lun_2_read_capacity                     sd_mmc_spi_read_capacity
+#define Lun_2_wr_protect                        sd_mmc_spi_wr_protect
+#define Lun_2_removal                           sd_mmc_spi_removal
+#define Lun_2_usb_read_10                       sd_mmc_spi_usb_read_10
+#define Lun_2_usb_write_10                      sd_mmc_spi_usb_write_10
+#define Lun_2_mem_2_ram                         sd_mmc_spi_mem_2_ram
+#define Lun_2_ram_2_mem                         sd_mmc_spi_ram_2_mem
+#define LUN_2_NAME                              "\"SD/MMC Card over SPI\""
+//! @}
+
+/*! \name USB LUNs Definitions
+ */
+//! @{
+#define MEM_USB                                 LUN_USB
+#define LUN_ID_MEM_USB                          LUN_ID_USB
+#define LUN_USB_INCLUDE                         "host_mem.h"
+#define Lun_usb_test_unit_ready(lun)            host_test_unit_ready(lun)
+#define Lun_usb_read_capacity(lun, nb_sect)     host_read_capacity(lun, nb_sect)
+#define Lun_usb_read_sector_size(lun)           host_read_sector_size(lun)
+#define Lun_usb_wr_protect(lun)                 host_wr_protect(lun)
+#define Lun_usb_removal()                       host_removal()
+#define Lun_usb_mem_2_ram(addr, ram)            host_read_10_ram(addr, ram)
+#define Lun_usb_ram_2_mem(addr, ram)            host_write_10_ram(addr, ram)
+#define LUN_USB_NAME                            "\"Host Mass-Storage Memory\""
+//! @}
+
+/*! \name Actions Associated with Memory Accesses
+ *
+ * Write here the action to associate with each memory access.
+ *
+ * \warning Be careful not to waste time in order not to disturb the functions.
+ */
+//! @{
+#define memory_start_read_action(nb_sectors)
+#define memory_stop_read_action()
+#define memory_start_write_action(nb_sectors)
+#define memory_stop_write_action()
+//! @}
+
+/*! \name Activation of Interface Features
+ */
+//! @{
+#define ACCESS_USB           DISABLED //!< MEM <-> USB interface.
+#define ACCESS_MEM_TO_RAM    ENABLED  //!< MEM <-> RAM interface.
+#define ACCESS_STREAM        ENABLED  //!< Streaming MEM <-> MEM interface.	//mlf
+#define ACCESS_STREAM_RECORD DISABLED //!< Streaming MEM <-> MEM interface in record mode.
+#define ACCESS_MEM_TO_MEM    DISABLED //!< MEM <-> MEM interface.
+#define ACCESS_CODEC         DISABLED //!< Codec interface.
+//! @}
+
+/*! \name Specific Options for Access Control
+ */
+//! @{
+#define GLOBAL_WR_PROTECT    DISABLED //!< Management of a global write protection.
+//! @}
+
+
+#endif  // _CONF_ACCESS_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/CONFIG/conf_at45dbx.h

@@ -0,0 +1,83 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AT45DBX configuration file.
+ *
+ * This file contains the possible external configuration of the AT45DBX.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _CONF_AT45DBX_H_
+#define _CONF_AT45DBX_H_
+
+
+#include "conf_access.h"
+
+#if AT45DBX_MEM == DISABLE
+  #error conf_at45dbx.h is #included although AT45DBX_MEM is disabled
+#endif
+
+
+#include "at45dbx.h"
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+//! Size of AT45DBX data flash memories to manage.
+#define AT45DBX_MEM_SIZE            AT45DBX_1MB
+
+//! Number of AT45DBX components to manage.
+#define AT45DBX_MEM_CNT             1
+
+//! First chip select used by AT45DBX components on the SPI module instance.
+//! AT45DBX_SPI_NPCS0_PIN always corresponds to this first NPCS, whatever it is.
+#define AT45DBX_SPI_FIRST_NPCS      AT45DBX_SPI_NPCS
+
+//! SPI master speed in Hz.
+#define AT45DBX_SPI_MASTER_SPEED    12000000
+
+//! Number of bits in each SPI transfer.
+#define AT45DBX_SPI_BITS            8
+
+
+#endif  // _CONF_AT45DBX_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/CONFIG/conf_ebi.h

@@ -0,0 +1,108 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief CONF_EBI EBI/SMC driver for AVR32 UC3.
+ *
+ * \note The values defined in this file are device-specific. See the device
+ *       datasheet for further information.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SMC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _CONF_EBI_H_
+#define _CONF_EBI_H_
+
+#include "compiler.h"
+#include "board.h"
+
+#if (ET024006DHU_SMC_USE_NCS == 0)
+#define  SMC_USE_NCS0                             
+#define  SMC_COMPONENT_CS0          ET024006DHU_SMC_COMPONENT_CS
+#else
+
+#if (ET024006DHU_SMC_USE_NCS == 2)
+#define SMC_USE_NCS2
+#define SMC_COMPONENT_CS2 ET024006DHU_SMC_COMPONENT_CS
+
+#else
+#error This board is not supported
+#endif
+#endif
+
+#define EBI_DATA_0                  ET024006DHU_EBI_DATA_0
+#define EBI_DATA_1                  ET024006DHU_EBI_DATA_1
+#define EBI_DATA_2                  ET024006DHU_EBI_DATA_2
+#define EBI_DATA_3                  ET024006DHU_EBI_DATA_3
+#define EBI_DATA_4                  ET024006DHU_EBI_DATA_4
+#define EBI_DATA_5                  ET024006DHU_EBI_DATA_5
+#define EBI_DATA_6                  ET024006DHU_EBI_DATA_6
+#define EBI_DATA_7                  ET024006DHU_EBI_DATA_7
+#define EBI_DATA_8                  ET024006DHU_EBI_DATA_8
+#define EBI_DATA_9                  ET024006DHU_EBI_DATA_9
+#define EBI_DATA_10                 ET024006DHU_EBI_DATA_10
+#define EBI_DATA_11                 ET024006DHU_EBI_DATA_11
+#define EBI_DATA_12                 ET024006DHU_EBI_DATA_12
+#define EBI_DATA_13                 ET024006DHU_EBI_DATA_13
+#define EBI_DATA_14                 ET024006DHU_EBI_DATA_14
+#define EBI_DATA_15                 ET024006DHU_EBI_DATA_15
+
+#if BOARD==EVK1105
+#ifdef EVK1105_REV3
+#define EBI_ADDR_19                 AVR32_EBI_ADDR_19
+#define EBI_NCS_2                   ET024006DHU_EBI_NCS
+#else
+#define EBI_ADDR_21                 ET024006DHU_EBI_ADDR_21
+#define EBI_NCS_0                   ET024006DHU_EBI_NCS
+#endif
+#elif BOARD == UC3C_EK
+#define EBI_ADDR_22		    AVR32_EBI_ADDR_22
+#define EBI_NCS_0                   ET024006DHU_EBI_NCS
+#elif BOARD == EVK1104
+#define EBI_ADDR_21                 ET024006DHU_EBI_ADDR_21
+#define EBI_NCS_0                   ET024006DHU_EBI_NCS
+#endif
+
+
+#define EBI_NWE0                    ET024006DHU_EBI_NWE
+#define EBI_NRD                     ET024006DHU_EBI_NRD
+    
+#endif  // _CONF_EBI_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/CONFIG/conf_sd_mmc_spi.h

@@ -0,0 +1,73 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief SD/MMC configuration file.
+ *
+ * This file contains the possible external configuration of the SD/MMC.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _CONF_SD_MMC_SPI_H_
+#define _CONF_SD_MMC_SPI_H_
+
+
+#include "conf_access.h"
+
+#if SD_MMC_SPI_MEM == DISABLE
+  #error conf_sd_mmc_spi.h is #included although SD_MMC_SPI_MEM is disabled
+#endif
+
+
+#include "sd_mmc_spi.h"
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+//! SPI master speed in Hz.
+#define SD_MMC_SPI_MASTER_SPEED     12000000
+
+//! Number of bits in each SPI transfer.
+#define SD_MMC_SPI_BITS             8
+
+
+#endif  // _CONF_SD_MMC_SPI_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/ASM/trampoline.x

@@ -0,0 +1,74 @@
+/* This file is part of the ATMEL AVR32-SoftwareFramework-AT32UC3A-1.4.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AVR32 UC3 ISP trampoline.
+ *
+ * In order to be able to program a project with both BatchISP and JTAGICE mkII
+ * without having to take the general-purpose fuses into consideration, add this
+ * file to the project and change the program entry point to _trampoline.
+ *
+ * The pre-programmed ISP will be erased if JTAGICE mkII is used.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32UC devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (C) 2006-2008, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "conf_isp.h"
+
+
+//! @{
+//! \verbatim
+
+
+  // This must be linked @ 0x80000000 if it is to be run upon reset.
+  .section  .reset, "ax", @progbits
+
+
+  .global _trampoline
+  .type _trampoline, @function
+_trampoline:
+  // Jump to program start.
+  rjmp    program_start
+
+  .org  PROGRAM_START_OFFSET
+program_start:
+  // Jump to the C runtime startup routine.
+  lda.w   pc, _stext
+
+
+//! \endverbatim
+//! @}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/arduino.h

@@ -0,0 +1,236 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AT32UC3A EVK1100 board header file.
+ *
+ * This file contains definitions and services related to the features of the
+ * EVK1100 board rev. B and C.
+ *
+ * To use this board, define BOARD=EVK1100.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _ARDUINO_H_
+#define _ARDUINO_H_
+
+#include "compiler.h"
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+#  include "led.h"
+#endif  // __AVR32_ABI_COMPILER__
+
+
+/*! \name Oscillator Definitions
+ */
+//! @{
+
+// RCOsc has no custom calibration by default. Set the following definition to
+// the appropriate value if a custom RCOsc calibration has been applied to your
+// part.
+//#define FRCOSC          AVR32_PM_RCOSC_FREQUENCY              //!< RCOsc frequency: Hz.
+
+#define FOSC32          32768                                 //!< Osc32 frequency: Hz.
+#define OSC32_STARTUP   AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC //!< Osc32 startup time: RCOsc periods.
+
+#define FOSC0           12000000                              //!< Osc0 frequency: Hz.
+#define OSC0_STARTUP    AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC  //!< Osc0 startup time: RCOsc periods.
+
+// Osc1 crystal is not mounted by default. Set the following definitions to the
+// appropriate values if a custom Osc1 crystal is mounted on your board.
+//#define FOSC1           12000000                              //!< Osc1 frequency: Hz.
+//#define OSC1_STARTUP    AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC  //!< Osc1 startup time: RCOsc periods.
+
+//! @}
+
+
+//! Number of LEDs.
+#define LED_COUNT   0
+
+/*! \name GPIO Connections of LEDs
+ */
+//! @{
+#define LED0_GPIO   AVR32_PIN_PB19
+#define LED1_GPIO   AVR32_PIN_PB20
+#define LED2_GPIO   AVR32_PIN_PB21
+#define DEB_PIN_GPIO AVR32_PIN_PA20
+//! @}
+
+/*! \name PWM Channels of LEDs
+ */
+//! @{
+#define LED0_PWM      0
+#define LED1_PWM      1
+#define LED2_PWM      2
+//! @}
+
+/*! \name PWM Functions of LEDs
+ */
+//! @{
+#define LED0_PWM_FUNCTION   AVR32_PWM_0_FUNCTION
+#define LED1_PWM_FUNCTION   AVR32_PWM_1_FUNCTION
+#define LED2_PWM_FUNCTION   AVR32_PWM_2_FUNCTION
+//! @}
+
+/*! \name Color Identifiers of LEDs to Use with LED Functions
+ */
+//! @{
+#define LED_MONO0_GREEN   LED0
+#define LED_MONO1_RED   	LED1
+#define LED_MONO2_BLU   	LED2
+//! @}
+
+#if 0
+/*! \name SPI Connections of the DIP204 LCD
+ */
+//! @{
+#define DIP204_SPI                  (&AVR32_SPI1)
+#define DIP204_SPI_NPCS             2
+#define DIP204_SPI_SCK_PIN          AVR32_SPI1_SCK_0_0_PIN
+#define DIP204_SPI_SCK_FUNCTION     AVR32_SPI1_SCK_0_0_FUNCTION
+#define DIP204_SPI_MISO_PIN         AVR32_SPI1_MISO_0_0_PIN
+#define DIP204_SPI_MISO_FUNCTION    AVR32_SPI1_MISO_0_0_FUNCTION
+#define DIP204_SPI_MOSI_PIN         AVR32_SPI1_MOSI_0_0_PIN
+#define DIP204_SPI_MOSI_FUNCTION    AVR32_SPI1_MOSI_0_0_FUNCTION
+#define DIP204_SPI_NPCS_PIN         AVR32_SPI1_NPCS_2_0_PIN
+#define DIP204_SPI_NPCS_FUNCTION    AVR32_SPI1_NPCS_2_0_FUNCTION
+//! @}
+
+/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight
+ */
+//! @{
+#define DIP204_BACKLIGHT_PIN        AVR32_PIN_PB18
+#define DIP204_PWM_CHANNEL          6
+#define DIP204_PWM_PIN              AVR32_PWM_6_PIN
+#define DIP204_PWM_FUNCTION         AVR32_PWM_6_FUNCTION
+//! @}
+#endif
+
+/*! \name SPI Connections of the AT45DBX Data Flash Memory
+ */
+//! @{
+#define AT45DBX_SPI                 (&AVR32_SPI1)
+#define AT45DBX_SPI_NPCS            2
+#define AT45DBX_SPI_SCK_PIN         AVR32_SPI1_SCK_0_0_PIN
+#define AT45DBX_SPI_SCK_FUNCTION    AVR32_SPI1_SCK_0_0_FUNCTION
+#define AT45DBX_SPI_MISO_PIN        AVR32_SPI1_MISO_0_0_PIN
+#define AT45DBX_SPI_MISO_FUNCTION   AVR32_SPI1_MISO_0_0_FUNCTION
+#define AT45DBX_SPI_MOSI_PIN        AVR32_SPI1_MOSI_0_0_PIN
+#define AT45DBX_SPI_MOSI_FUNCTION   AVR32_SPI1_MOSI_0_0_FUNCTION
+#define AT45DBX_SPI_NPCS2_PIN       AVR32_SPI1_NPCS_2_0_PIN
+#define AT45DBX_SPI_NPCS2_FUNCTION  AVR32_SPI1_NPCS_2_0_FUNCTION
+#define AT45DBX_CHIP_RESET  		AVR32_PIN_PA02
+//! @}
+
+
+/*! \name GPIO and SPI Connections of the SD/MMC Connector
+ */
+//! @{
+//#define SD_MMC_CARD_DETECT_PIN      AVR32_PIN_PA02
+//#define SD_MMC_WRITE_PROTECT_PIN    AVR32_PIN_PA07
+#define SD_MMC_SPI                  (&AVR32_SPI1)
+#define SD_MMC_SPI_NPCS             1
+#define SD_MMC_SPI_SCK_PIN          AVR32_SPI1_SCK_0_0_PIN
+#define SD_MMC_SPI_SCK_FUNCTION     AVR32_SPI1_SCK_0_0_FUNCTION
+#define SD_MMC_SPI_MISO_PIN         AVR32_SPI1_MISO_0_0_PIN
+#define SD_MMC_SPI_MISO_FUNCTION    AVR32_SPI1_MISO_0_0_FUNCTION
+#define SD_MMC_SPI_MOSI_PIN         AVR32_SPI1_MOSI_0_0_PIN
+#define SD_MMC_SPI_MOSI_FUNCTION    AVR32_SPI1_MOSI_0_0_FUNCTION
+#define SD_MMC_SPI_NPCS_PIN         AVR32_SPI1_NPCS_1_0_PIN
+#define SD_MMC_SPI_NPCS_FUNCTION    AVR32_SPI1_NPCS_1_0_FUNCTION
+//! @}
+
+/*	Timer Counter to generate clock for WiFi chip*/
+#  define WIFI_TC                    (&AVR32_TC)
+#  define WIFI_TC_CHANNEL_ID         0
+#  define WIFI_TC_CHANNEL_PIN        AVR32_TC_A0_0_0_PIN
+#  define WIFI_TC_CHANNEL_FUNCTION   AVR32_TC_A0_0_0_FUNCTION
+// Note that TC_A0_0_0 pin is pin 6 (PB23) on AT32UC3A1512 QFP100.
+
+/* Pin related to WiFi chip communication */
+#ifndef USE_POLL
+ #define USE_POLL
+#endif
+ #define SPI_CS 					0
+ #define AVR32_SPI 					AVR32_SPI1
+ #define GPIO_IRQ_PIN 				AVR32_PIN_PA03
+ #define GPIO_IRQ 					AVR32_GPIO_IRQ_7
+ #define GPIO_W_RESET_PIN 			AVR32_PIN_PA07
+ #define GPIO_W_SHUTDOWN_PIN 		AVR32_PIN_PA09
+
+/* Pin related to shield communication */
+ #define ARDUINO_HANDSHAKE_PIN 		AVR32_PIN_PA25
+ #define ARDUINO_EXTINT_PIN 		AVR32_PIN_PA04		//not used
+
+ #define AVR32_PDCA_PID_TX 			AVR32_PDCA_PID_SPI1_TX
+ #define AVR32_PDCA_PID_RX 			AVR32_PDCA_PID_SPI1_RX
+
+
+#if 0
+/*! \name TWI Connections of the Spare TWI Connector
+ */
+//! @{
+#define SPARE_TWI                   (&AVR32_TWI)
+#define SPARE_TWI_SCL_PIN           AVR32_TWI_SCL_0_0_PIN
+#define SPARE_TWI_SCL_FUNCTION      AVR32_TWI_SCL_0_0_FUNCTION
+#define SPARE_TWI_SDA_PIN           AVR32_TWI_SDA_0_0_PIN
+#define SPARE_TWI_SDA_FUNCTION      AVR32_TWI_SDA_0_0_FUNCTION
+//! @}
+
+
+/*! \name SPI Connections of the Spare SPI Connector
+ */
+//! @{
+#define SPARE_SPI                   (&AVR32_SPI0)
+#define SPARE_SPI_NPCS              0
+#define SPARE_SPI_SCK_PIN           AVR32_SPI0_SCK_0_0_PIN
+#define SPARE_SPI_SCK_FUNCTION      AVR32_SPI0_SCK_0_0_FUNCTION
+#define SPARE_SPI_MISO_PIN          AVR32_SPI0_MISO_0_0_PIN
+#define SPARE_SPI_MISO_FUNCTION     AVR32_SPI0_MISO_0_0_FUNCTION
+#define SPARE_SPI_MOSI_PIN          AVR32_SPI0_MOSI_0_0_PIN
+#define SPARE_SPI_MOSI_FUNCTION     AVR32_SPI0_MOSI_0_0_FUNCTION
+#define SPARE_SPI_NPCS_PIN          AVR32_SPI0_NPCS_0_0_PIN
+#define SPARE_SPI_NPCS_FUNCTION     AVR32_SPI0_NPCS_0_0_FUNCTION
+//! @}
+#endif
+
+#endif  // _ARDUINO_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.c

@@ -0,0 +1,346 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AT32UC3A EVK1100 board LEDs support package.
+ *
+ * This file contains definitions and services related to the LED features of
+ * the EVK1100 board.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include <avr32/io.h>
+#include "preprocessor.h"
+#include "compiler.h"
+#include "arduino.h"
+#include "led.h"
+
+
+//! Structure describing LED hardware connections.
+typedef const struct
+{
+  struct
+  {
+    U32 PORT;     //!< LED GPIO port.
+    U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port.
+  } GPIO; //!< LED GPIO descriptor.
+  struct
+  {
+    S32 CHANNEL;  //!< LED PWM channel (< 0 if N/A).
+    S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A).
+  } PWM;  //!< LED PWM descriptor.
+} tLED_DESCRIPTOR;
+
+
+//! Hardware descriptors of all LEDs.
+static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] =
+{
+#define INSERT_LED_DESCRIPTOR(LED_NO, unused)                 \
+  {                                                           \
+    {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\
+    {LED##LED_NO##_PWM,       LED##LED_NO##_PWM_FUNCTION    } \
+  },
+  MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~)
+#undef INSERT_LED_DESCRIPTOR
+};
+
+
+//! Saved state of all LEDs.
+static volatile U32 LED_State = (1 << LED_COUNT) - 1;
+
+
+U32 LED_Read_Display(void)
+{
+  return LED_State;
+}
+
+
+void LED_Display(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor;
+  volatile avr32_gpio_port_t *led_gpio_port;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  LED_State = leds;
+
+  // For all LEDs...
+  for (led_descriptor = &LED_DESCRIPTOR[0];
+       led_descriptor < LED_DESCRIPTOR + LED_COUNT;
+       led_descriptor++)
+  {
+    // Set the LED to the requested state.
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    if (leds & 1)
+    {
+      led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;
+    }
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= 1;
+  }
+}
+
+
+U32 LED_Read_Display_Mask(U32 mask)
+{
+  return Rd_bits(LED_State, mask);
+}
+
+
+void LED_Display_Mask(U32 mask, U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  mask &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Wr_bits(LED_State, mask, leds);
+
+  // While there are specified LEDs left to manage...
+  while (mask)
+  {
+    // Select the next specified LED and set it to the requested state.
+    led_shift = 1 + ctz(mask);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    leds >>= led_shift - 1;
+    if (leds & 1)
+    {
+      led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;
+    }
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= 1;
+    mask >>= led_shift;
+  }
+}
+
+
+Bool LED_Test(U32 leds)
+{
+  return Tst_bits(LED_State, leds);
+}
+
+
+void LED_Off(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Clr_bits(LED_State, leds);
+
+  // While there are specified LEDs left to manage...
+  while (leds)
+  {
+    // Select the next specified LED and turn it off.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= led_shift;
+  }
+}
+
+
+void LED_On(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Set_bits(LED_State, leds);
+
+  // While there are specified LEDs left to manage...
+  while (leds)
+  {
+    // Select the next specified LED and turn it on.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= led_shift;
+  }
+}
+
+
+void LED_Toggle(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Tgl_bits(LED_State, leds);
+
+  // While there are specified LEDs left to manage...
+  while (leds)
+  {
+    // Select the next specified LED and toggle it.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    led_gpio_port->ovrt  = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= led_shift;
+  }
+}
+
+
+U32 LED_Read_Display_Field(U32 field)
+{
+  return Rd_bitfield(LED_State, field);
+}
+
+
+void LED_Display_Field(U32 field, U32 leds)
+{
+  // Move the bit-field to the appropriate position for the bit-mask.
+  LED_Display_Mask(field, leds << ctz(field));
+}
+
+
+U8 LED_Get_Intensity(U32 led)
+{
+  tLED_DESCRIPTOR *led_descriptor;
+
+  // Check that the argument value is valid.
+  led = ctz(led);
+  led_descriptor = &LED_DESCRIPTOR[led];
+  if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0;
+
+  // Return the duty cycle value if the LED PWM channel is enabled, else 0.
+  return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ?
+           AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0;
+}
+
+
+void LED_Set_Intensity(U32 leds, U8 intensity)
+{
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_pwm_channel_t *led_pwm_channel;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // For each specified LED...
+  for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift)
+  {
+    // Select the next specified LED and check that it has a PWM channel.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    if (led_descriptor->PWM.CHANNEL < 0) continue;
+
+    // Initialize or update the LED PWM channel.
+    led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL];
+    if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)))
+    {
+      led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) &
+                             ~(AVR32_PWM_CALG_MASK |
+                               AVR32_PWM_CPOL_MASK |
+                               AVR32_PWM_CPD_MASK);
+      led_pwm_channel->cprd = 0x000000FF;
+      led_pwm_channel->cdty = intensity;
+      AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL;
+    }
+    else
+    {
+      AVR32_PWM.isr;
+      while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL)));
+      led_pwm_channel->cupd = intensity;
+    }
+
+    // Switch the LED pin to its PWM function.
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    if (led_descriptor->PWM.FUNCTION & 0x1)
+    {
+      led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK;
+    }
+    if (led_descriptor->PWM.FUNCTION & 0x2)
+    {
+      led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK;
+    }
+    led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK;
+  }
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/ARDUINO/led.h

@@ -0,0 +1,191 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AT32UC3A EVK1100 board LEDs support package.
+ *
+ * This file contains definitions and services related to the LED features of
+ * the EVK1100 board.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _LED_H_
+#define _LED_H_
+
+#include "compiler.h"
+
+
+/*! \name Identifiers of LEDs to Use with LED Functions
+ */
+//! @{
+#define LED0  0x01
+#define LED1  0x02
+#define LED2  0x04
+#define LED3  0x08
+#define LED4  0x10
+#define LED5  0x20
+#define LED6  0x40
+#define LED7  0x80
+//! @}
+
+
+/*! \brief Gets the last state of all LEDs set through the LED API.
+ *
+ * \return State of all LEDs (1 bit per LED).
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U32 LED_Read_Display(void);
+
+/*! \brief Sets the state of all LEDs.
+ *
+ * \param leds New state of all LEDs (1 bit per LED).
+ *
+ * \note The pins of all LEDs are set to GPIO output mode.
+ */
+extern void LED_Display(U32 leds);
+
+/*! \brief Gets the last state of the specified LEDs set through the LED API.
+ *
+ * \param mask LEDs of which to get the state (1 bit per LED).
+ *
+ * \return State of the specified LEDs (1 bit per LED).
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U32 LED_Read_Display_Mask(U32 mask);
+
+/*! \brief Sets the state of the specified LEDs.
+ *
+ * \param mask LEDs of which to set the state (1 bit per LED).
+ *
+ * \param leds New state of the specified LEDs (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Display_Mask(U32 mask, U32 leds);
+
+/*! \brief Tests the last state of the specified LEDs set through the LED API.
+ *
+ * \param leds LEDs of which to test the state (1 bit per LED).
+ *
+ * \return \c TRUE if at least one of the specified LEDs has a state on, else
+ *         \c FALSE.
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern Bool LED_Test(U32 leds);
+
+/*! \brief Turns off the specified LEDs.
+ *
+ * \param leds LEDs to turn off (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Off(U32 leds);
+
+/*! \brief Turns on the specified LEDs.
+ *
+ * \param leds LEDs to turn on (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_On(U32 leds);
+
+/*! \brief Toggles the specified LEDs.
+ *
+ * \param leds LEDs to toggle (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Toggle(U32 leds);
+
+/*! \brief Gets as a bit-field the last state of the specified LEDs set through
+ *         the LED API.
+ *
+ * \param field LEDs of which to get the state (1 bit per LED).
+ *
+ * \return State of the specified LEDs (1 bit per LED, beginning with the first
+ *         specified LED).
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U32 LED_Read_Display_Field(U32 field);
+
+/*! \brief Sets as a bit-field the state of the specified LEDs.
+ *
+ * \param field LEDs of which to set the state (1 bit per LED).
+ * \param leds New state of the specified LEDs (1 bit per LED, beginning with
+ *             the first specified LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Display_Field(U32 field, U32 leds);
+
+/*! \brief Gets the intensity of the specified LED.
+ *
+ * \param led LED of which to get the intensity (1 bit per LED; only the least
+ *            significant set bit is used).
+ *
+ * \return Intensity of the specified LED (0x00 to 0xFF).
+ *
+ * \warning The PWM channel of the specified LED is supposed to be used only by
+ *          this module.
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U8 LED_Get_Intensity(U32 led);
+
+/*! \brief Sets the intensity of the specified LEDs.
+ *
+ * \param leds LEDs of which to set the intensity (1 bit per LED).
+ * \param intensity New intensity of the specified LEDs (0x00 to 0xFF).
+ *
+ * \warning The PWM channels of the specified LEDs are supposed to be used only
+ *          by this module.
+ *
+ * \note The pins of the specified LEDs are set to PWM output mode.
+ */
+extern void LED_Set_Intensity(U32 leds, U8 intensity);
+
+
+#endif  // _LED_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/evk1105.h

@@ -0,0 +1,433 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AT32UC3A EVK1105 board header file.
+ *
+ * This file contains definitions and services related to the features of the
+ * EVK1105 board rev. B.
+ *
+ * To use this board, define BOARD=EVK1105.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _EVK1105_H_
+#define _EVK1105_H_
+
+#ifdef EVK1105_REV3
+#  include "evk1105_rev3.h"
+#else
+
+#include "compiler.h"
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+#  include "led.h"
+#endif  // __AVR32_ABI_COMPILER__
+
+
+/*! \name Oscillator Definitions
+ */
+//! @{
+
+// RCOsc has no custom calibration by default. Set the following definition to
+// the appropriate value if a custom RCOsc calibration has been applied to your
+// part.
+//#define FRCOSC          AVR32_PM_RCOSC_FREQUENCY              //!< RCOsc frequency: Hz.
+
+#define FOSC32          32768                                 //!< Osc32 frequency: Hz.
+#define OSC32_STARTUP   AVR32_PM_OSCCTRL32_STARTUP_8192_RCOSC //!< Osc32 startup time: RCOsc periods.
+
+#define FOSC0           12000000                              //!< Osc0 frequency: Hz.
+#define OSC0_STARTUP    AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC  //!< Osc0 startup time: RCOsc periods.
+
+#define FOSC1           11289600                              //!< Osc1 frequency: Hz
+#define OSC1_STARTUP    AVR32_PM_OSCCTRL1_STARTUP_2048_RCOSC  //!< Osc1 startup time: RCOsc periods.
+
+
+//! @}
+
+
+/*! \name SDRAM Definitions
+ */
+//! @{
+
+//! Part header file of used SDRAM(s).
+#define SDRAM_PART_HDR  "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h"
+
+//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on
+//! UC3).
+#define SDRAM_DBW       16
+//! @}
+
+
+/*! \name USB Definitions
+ */
+//! @{
+//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x.
+//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and
+//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.
+#define AVR32_USBB_USB_ID_0_2_PIN          21
+#define AVR32_USBB_USB_ID_0_2_FUNCTION     2
+#define USB_ID                      AVR32_USBB_USB_ID_0_2
+
+//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x.
+//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and
+//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from <avr32/uc3axxxx.h>.
+#  define USB_VBOF                    AVR32_USBB_USB_VBOF_0_1
+
+
+//! Active level of the USB_VBOF output pin.
+#  define USB_VBOF_ACTIVE_LEVEL       LOW
+
+//! USB overcurrent detection pin.
+#  define USB_OVERCURRENT_DETECT_PIN  AVR32_PIN_PX15
+
+//! @}
+
+
+//! GPIO connection of the MAC PHY PWR_DOWN/INT signal.
+#  define MACB_INTERRUPT_PIN  AVR32_PIN_PA26
+
+
+
+//! Number of LEDs.
+#define LED_COUNT   4
+
+/*! \name GPIO Connections of LEDs
+ */
+//! @{
+#  define LED0_GPIO   AVR32_PIN_PB27
+#  define LED1_GPIO   AVR32_PIN_PB28
+#  define LED2_GPIO   AVR32_PIN_PA05
+#  define LED3_GPIO   AVR32_PIN_PA06
+//! @}
+
+/*! \name Color Identifiers of LEDs to Use with LED Functions
+ */
+//! @{
+#define LED_MONO0_GREEN   LED0
+#define LED_MONO1_GREEN   LED1
+#define LED_MONO2_GREEN   LED2
+#define LED_MONO3_GREEN   LED3
+//! @}
+
+/*! \name PWM Channels of LEDs
+ */
+//! @{
+#define LED0_PWM      4
+#define LED1_PWM      5
+#define LED2_PWM      (-1)
+#define LED3_PWM      (-1)
+//! @}
+
+/*! \name PWM Functions of LEDs
+ */
+//! @{
+/* TODO: Implement PWM functionality */
+#define LED0_PWM_FUNCTION   (-1)//AVR32_PWM_0_FUNCTION
+#define LED1_PWM_FUNCTION   (-1)//AVR32_PWM_1_FUNCTION
+#define LED2_PWM_FUNCTION   (-1)
+#define LED3_PWM_FUNCTION   (-1)
+//! @}
+
+//! External interrupt connection of touch sensor.
+#define QT1081_EIC_EXTINT_PIN       AVR32_EIC_EXTINT_1_PIN
+#define QT1081_EIC_EXTINT_FUNCTION  AVR32_EIC_EXTINT_1_FUNCTION
+#define QT1081_EIC_EXTINT_IRQ       AVR32_EIC_IRQ_1
+#define QT1081_EIC_EXTINT_INT       AVR32_EIC_INT1
+/*! \name Touch sensor low power mode select
+ */
+#define QT1081_LP_MODE    AVR32_PIN_PB29
+
+/*! \name GPIO Connections of touch buttons
+ */
+//! @{
+#define QT1081_TOUCH_SENSOR_0           AVR32_PIN_PB22
+#define QT1081_TOUCH_SENSOR_0_PRESSED   1
+#define QT1081_TOUCH_SENSOR_1           AVR32_PIN_PB23
+#define QT1081_TOUCH_SENSOR_1_PRESSED   1
+#define QT1081_TOUCH_SENSOR_2           AVR32_PIN_PB24
+#define QT1081_TOUCH_SENSOR_2_PRESSED   1
+#define QT1081_TOUCH_SENSOR_3           AVR32_PIN_PB25
+#define QT1081_TOUCH_SENSOR_3_PRESSED   1
+#define QT1081_TOUCH_SENSOR_4           AVR32_PIN_PB26
+#define QT1081_TOUCH_SENSOR_4_PRESSED   1
+
+#define QT1081_TOUCH_SENSOR_ENTER           QT1081_TOUCH_SENSOR_4
+#define QT1081_TOUCH_SENSOR_ENTER_PRESSED   QT1081_TOUCH_SENSOR_4_PRESSED
+#define QT1081_TOUCH_SENSOR_LEFT            QT1081_TOUCH_SENSOR_3
+#define QT1081_TOUCH_SENSOR_LEFT_PRESSED    QT1081_TOUCH_SENSOR_3_PRESSED
+#define QT1081_TOUCH_SENSOR_RIGHT           QT1081_TOUCH_SENSOR_2
+#define QT1081_TOUCH_SENSOR_RIGHT_PRESSED   QT1081_TOUCH_SENSOR_2_PRESSED
+#define QT1081_TOUCH_SENSOR_UP              QT1081_TOUCH_SENSOR_0
+#define QT1081_TOUCH_SENSOR_UP_PRESSED      QT1081_TOUCH_SENSOR_0_PRESSED
+#define QT1081_TOUCH_SENSOR_DOWN            QT1081_TOUCH_SENSOR_1
+#define QT1081_TOUCH_SENSOR_DOWN_PRESSED    QT1081_TOUCH_SENSOR_1_PRESSED
+//! @}
+
+/*! \name SPI Connections of the AT45DBX Data Flash Memory
+ */
+//! @{
+#define AT45DBX_SPI                 (&AVR32_SPI0)
+#define AT45DBX_SPI_NPCS            0
+#define AT45DBX_SPI_SCK_PIN         AVR32_SPI0_SCK_0_0_PIN
+#define AT45DBX_SPI_SCK_FUNCTION    AVR32_SPI0_SCK_0_0_FUNCTION
+#define AT45DBX_SPI_MISO_PIN        AVR32_SPI0_MISO_0_0_PIN
+#define AT45DBX_SPI_MISO_FUNCTION   AVR32_SPI0_MISO_0_0_FUNCTION
+#define AT45DBX_SPI_MOSI_PIN        AVR32_SPI0_MOSI_0_0_PIN
+#define AT45DBX_SPI_MOSI_FUNCTION   AVR32_SPI0_MOSI_0_0_FUNCTION
+#define AT45DBX_SPI_NPCS0_PIN       AVR32_SPI0_NPCS_0_0_PIN
+#define AT45DBX_SPI_NPCS0_FUNCTION  AVR32_SPI0_NPCS_0_0_FUNCTION
+//! @}
+
+/*! \name GPIO and SPI Connections of the SD/MMC Connector
+ */
+//! @{
+#define SD_MMC_CARD_DETECT_PIN      AVR32_PIN_PA02
+#define SD_MMC_WRITE_PROTECT_PIN    AVR32_PIN_PA18
+#define SD_MMC_SPI                  (&AVR32_SPI0)
+#define SD_MMC_SPI_NPCS             1
+#define SD_MMC_SPI_SCK_PIN          AVR32_SPI0_SCK_0_0_PIN
+#define SD_MMC_SPI_SCK_FUNCTION     AVR32_SPI0_SCK_0_0_FUNCTION
+#define SD_MMC_SPI_MISO_PIN         AVR32_SPI0_MISO_0_0_PIN
+#define SD_MMC_SPI_MISO_FUNCTION    AVR32_SPI0_MISO_0_0_FUNCTION
+#define SD_MMC_SPI_MOSI_PIN         AVR32_SPI0_MOSI_0_0_PIN
+#define SD_MMC_SPI_MOSI_FUNCTION    AVR32_SPI0_MOSI_0_0_FUNCTION
+#define SD_MMC_SPI_NPCS_PIN         AVR32_SPI0_NPCS_1_0_PIN
+#define SD_MMC_SPI_NPCS_FUNCTION    AVR32_SPI0_NPCS_1_0_FUNCTION
+//! @}
+
+
+/*! \name TWI expansion
+ */
+//! @{
+#define EXPANSION_TWI                   (&AVR32_TWI)
+#define EXPANSION_RESET                 AVR32_PIN_PX16
+#define EXPANSION_TWI_SCL_PIN           AVR32_TWI_SCL_0_0_PIN
+#define EXPANSION_TWI_SCL_FUNCTION      AVR32_TWI_SCL_0_0_FUNCTION
+#define EXPANSION_TWI_SDA_PIN           AVR32_TWI_SDA_0_0_PIN
+#define EXPANSION_TWI_SDA_FUNCTION      AVR32_TWI_SDA_0_0_FUNCTION
+//! @}
+
+/*! \name Wireless expansion
+ */
+
+#define WEXPANSION_EXTINT_PIN           AVR32_EIC_EXTINT_8_PIN
+#define WEXPANSION_EXTINT_FUNCTION      AVR32_EIC_EXTINT_8_FUNCTION
+#define WEXPANSION_GPIO1                AVR32_PIN_PB30
+#define WEXPANSION_GPIO2                AVR32_PIN_PB31
+
+#define WEXPANSION_SPI                  (&AVR32_SPI0)
+#define WEXPANSION_SPI_NPCS             2
+#define WEXPANSION_SPI_SCK_PIN          AVR32_SPI0_SCK_0_0_PIN
+#define WEXPANSION_SPI_SCK_FUNCTION     AVR32_SPI0_SCK_0_0_FUNCTION
+#define WEXPANSION_SPI_MISO_PIN         AVR32_SPI0_MISO_0_0_PIN
+#define WEXPANSION_SPI_MISO_FUNCTION    AVR32_SPI0_MISO_0_0_FUNCTION
+#define WEXPANSION_SPI_MOSI_PIN         AVR32_SPI0_MOSI_0_0_PIN
+#define WEXPANSION_SPI_MOSI_FUNCTION    AVR32_SPI0_MOSI_0_0_FUNCTION
+#define WEXPANSION_SPI_NPCS_PIN         AVR32_SPI0_NPCS_2_0_PIN
+#define WEXPANSION_SPI_NPCS_FUNCTION    AVR32_SPI0_NPCS_2_0_FUNCTION
+
+//! @}
+
+/*! \name ET024006DHU TFT display
+ */
+//! @{
+
+#define ET024006DHU_TE_PIN              AVR32_PIN_PX19
+#define ET024006DHU_RESET_PIN           AVR32_PIN_PX22
+#define ET024006DHU_BL_PIN              AVR32_PWM_6_PIN
+#define ET024006DHU_BL_FUNCTION         AVR32_PWM_6_FUNCTION
+#define ET024006DHU_DNC_PIN             AVR32_EBI_ADDR_21_1_PIN
+#define ET024006DHU_DNC_FUNCTION        AVR32_EBI_ADDR_21_1_FUNCTION
+#define ET024006DHU_EBI_NCS_PIN         AVR32_EBI_NCS_0_1_PIN
+#define ET024006DHU_EBI_NCS_FUNCTION    AVR32_EBI_NCS_0_1_FUNCTION
+
+//! @}
+/*! \name Optional SPI connection to the TFT
+ */
+//! @{
+
+#define ET024006DHU_SPI                  (&AVR32_SPI0)
+#define ET024006DHU_SPI_NPCS             3
+#define ET024006DHU_SPI_SCK_PIN          AVR32_SPI0_SCK_0_0_PIN
+#define ET024006DHU_SPI_SCK_FUNCTION     AVR32_SPI0_SCK_0_0_FUNCTION
+#define ET024006DHU_SPI_MISO_PIN         AVR32_SPI0_MISO_0_0_PIN
+#define ET024006DHU_SPI_MISO_FUNCTION    AVR32_SPI0_MISO_0_0_FUNCTION
+#define ET024006DHU_SPI_MOSI_PIN         AVR32_SPI0_MOSI_0_0_PIN
+#define ET024006DHU_SPI_MOSI_FUNCTION    AVR32_SPI0_MOSI_0_0_FUNCTION
+#define ET024006DHU_SPI_NPCS_PIN         AVR32_SPI1_NPCS_3_0_PIN
+#define ET024006DHU_SPI_NPCS_FUNCTION    AVR32_SPI1_NPCS_3_0_FUNCTION
+
+//! @}
+
+
+/*! \name Audio amplifier connection to the DAC
+ */
+//! @{
+
+#define TPA6130_ABDAC             (&AVR32_ABDAC)
+
+#define TPA6130_DATA0_PIN         AVR32_ABDAC_DATA_0_1_PIN
+#define TPA6130_DATA0_FUNCTION    AVR32_ABDAC_DATA_0_1_FUNCTION
+#define TPA6130_DATAN0_PIN        AVR32_ABDAC_DATAN_0_1_PIN
+#define TPA6130_DATAN0_FUNCTION   AVR32_ABDAC_DATAN_0_1_FUNCTION
+#define TPA6130_DATA1_PIN         AVR32_ABDAC_DATA_1_1_PIN
+#define TPA6130_DATA1_FUNCTION    AVR32_ABDAC_DATA_1_1_FUNCTION
+#define TPA6130_DATAN1_PIN        AVR32_ABDAC_DATAN_1_1_PIN
+#define TPA6130_DATAN1_FUNCTION   AVR32_ABDAC_DATAN_1_1_FUNCTION
+
+#define TPA6130_ABDAC_PDCA_PID       AVR32_PDCA_PID_ABDAC_TX
+#define TPA6130_ABDAC_PDCA_CHANNEL   0
+#define TPA6130_ABDAC_PDCA_IRQ       AVR32_PDCA_IRQ_0
+#define TPA6130_ABDAC_PDCA_INT_LEVEL AVR32_INTC_INT3
+
+#define TPA6130_TWI                  (&AVR32_TWI)
+#define TPA6130_TWI_SCL_PIN          AVR32_TWI_SCL_0_0_PIN
+#define TPA6130_TWI_SCL_FUNCTION     AVR32_TWI_SCL_0_0_FUNCTION
+#define TPA6130_TWI_SDA_PIN          AVR32_TWI_SDA_0_0_PIN
+#define TPA6130_TWI_SDA_FUNCTION     AVR32_TWI_SDA_0_0_FUNCTION
+
+//! }@
+/*! \name TI TLV320AIC23B sound chip
+ */
+//! @{
+#define TLV320_SSC                           (&AVR32_SSC)
+#define TLV320_SSC_TX_CLOCK_PIN              AVR32_SSC_TX_CLOCK_0_PIN
+#define TLV320_SSC_TX_CLOCK_FUNCTION         AVR32_SSC_TX_CLOCK_0_FUNCTION
+#define TLV320_SSC_TX_DATA_PIN               AVR32_SSC_TX_DATA_0_PIN
+#define TLV320_SSC_TX_DATA_FUNCTION          AVR32_SSC_TX_DATA_0_FUNCTION
+#define TLV320_SSC_TX_FRAME_SYNC_PIN         AVR32_SSC_TX_FRAME_SYNC_0_PIN
+#define TLV320_SSC_TX_FRAME_SYNC_FUNCTION    AVR32_SSC_TX_FRAME_SYNC_0_FUNCTION
+
+#define TLV320_TWI                   (&AVR32_TWI)
+#define TLV320_TWI_SCL_PIN           AVR32_TWI_SCL_0_0_PIN
+#define TLV320_TWI_SCL_FUNCTION      AVR32_TWI_SCL_0_0_FUNCTION
+#define TLV320_TWI_SDA_PIN           AVR32_TWI_SDA_0_0_PIN
+#define TLV320_TWI_SDA_FUNCTION      AVR32_TWI_SDA_0_0_FUNCTION
+
+#define TLV320_PM_GCLK_PIN         AVR32_PM_GCLK_0_0_PIN
+#define TLV320_PM_GCLK_FUNCTION    AVR32_PM_GCLK_0_0_FUNCTION
+//! @}
+
+////! \name SPI: Apple Authentication Chip Hardware Connections
+////! @{
+#define IPOD_AUTH_CHIP_SPI                  (&AVR32_SPI0)
+#define IPOD_AUTH_CHIP_SPI_IRQ              AVR32_SPI0_IRQ
+#define IPOD_AUTH_CHIP_SPI_NPCS             2
+#define IPOD_AUTH_CHIP_SPI_SCK_PIN          AVR32_SPI0_SCK_0_0_PIN
+#define IPOD_AUTH_CHIP_SPI_SCK_FUNCTION     AVR32_SPI0_SCK_0_0_FUNCTION
+#define IPOD_AUTH_CHIP_SPI_MISO_PIN         AVR32_SPI0_MISO_0_0_PIN
+#define IPOD_AUTH_CHIP_SPI_MISO_FUNCTION    AVR32_SPI0_MISO_0_0_FUNCTION
+#define IPOD_AUTH_CHIP_SPI_MOSI_PIN         AVR32_SPI0_MOSI_0_0_PIN
+#define IPOD_AUTH_CHIP_SPI_MOSI_FUNCTION    AVR32_SPI0_MOSI_0_0_FUNCTION
+#define IPOD_AUTH_CHIP_SPI_NPCS_PIN         AVR32_SPI0_NPCS_2_0_PIN
+#define IPOD_AUTH_CHIP_SPI_NPCS_FUNCTION    AVR32_SPI0_NPCS_2_0_FUNCTION
+#define IPOD_AUTH_CHIP_SPI_N_RESET_PIN      AVR32_PIN_PB30
+#define IPOD_AUTH_CHIP_SPI_CP_READY_PIN     AVR32_PIN_PB31
+//! }@
+
+/*! \name Connections of the iPOD Authentication Coprocessor
+ */
+//! @{
+        
+#define IPOD_AUTH_CHIP_TWI                  (&AVR32_TWI)
+#define IPOD_AUTH_CHIP_TWI_SCL_PIN          AVR32_TWI_SCL_0_0_PIN
+#define IPOD_AUTH_CHIP_TWI_SCL_FUNCTION     AVR32_TWI_SCL_0_0_FUNCTION
+#define IPOD_AUTH_CHIP_TWI_SDA_PIN          AVR32_TWI_SDA_0_0_PIN
+#define IPOD_AUTH_CHIP_TWI_SDA_FUNCTION     AVR32_TWI_SDA_0_0_FUNCTION
+#define IPOD_AUTH_CHIP_TWI_N_RESET_PIN      AVR32_PIN_PX16
+
+//! @}
+
+/*! \name USART connection to the UC3B board controller
+ */
+//! @{
+
+#define USART0_RXD_PIN          AVR32_USART0_RXD_0_0_PIN
+#define USART0_RXD_FUNCTION     AVR32_USART0_RXD_0_0_FUNCTION
+#define USART0_TXD_PIN          AVR32_USART0_TXD_0_0_PIN
+#define USART0_TXD_FUNCTION     AVR32_USART0_TXD_0_0_FUNCTION
+#define USART0_RTS_PIN          AVR32_USART0_RTS_0_0_PIN
+#define USART0_RTS_FUNCTION     AVR32_USART0_RTS_0_0_FUNCTION
+#define USART0_CTS_PIN          AVR32_USART0_CTS_0_0_PIN
+#define USART0_CTS_FUNCTION     AVR32_USART0_CTS_0_0_FUNCTION
+
+//! @}
+
+#define ADC_VEXT_PIN         AVR32_ADC_AD_7_PIN
+#define ADC_VEXT_FUNCTION    AVR32_ADC_AD_7_FUNCTION
+
+/*! \name LCD Connections of the ET024006DHU display
+ */
+//! @{
+#define ET024006DHU_SMC_USE_NCS           0
+#define ET024006DHU_SMC_COMPONENT_CS      "smc_et024006dhu.h"
+
+#define ET024006DHU_EBI_DATA_0    AVR32_EBI_DATA_0
+#define ET024006DHU_EBI_DATA_1    AVR32_EBI_DATA_1
+#define ET024006DHU_EBI_DATA_2    AVR32_EBI_DATA_2
+#define ET024006DHU_EBI_DATA_3    AVR32_EBI_DATA_3
+#define ET024006DHU_EBI_DATA_4    AVR32_EBI_DATA_4
+#define ET024006DHU_EBI_DATA_5    AVR32_EBI_DATA_5
+#define ET024006DHU_EBI_DATA_6    AVR32_EBI_DATA_6
+#define ET024006DHU_EBI_DATA_7    AVR32_EBI_DATA_7
+#define ET024006DHU_EBI_DATA_8    AVR32_EBI_DATA_8
+#define ET024006DHU_EBI_DATA_9    AVR32_EBI_DATA_9
+#define ET024006DHU_EBI_DATA_10   AVR32_EBI_DATA_10
+#define ET024006DHU_EBI_DATA_11   AVR32_EBI_DATA_11
+#define ET024006DHU_EBI_DATA_12   AVR32_EBI_DATA_12
+#define ET024006DHU_EBI_DATA_13   AVR32_EBI_DATA_13
+#define ET024006DHU_EBI_DATA_14   AVR32_EBI_DATA_14
+#define ET024006DHU_EBI_DATA_15   AVR32_EBI_DATA_15
+
+#define ET024006DHU_EBI_ADDR_21   AVR32_EBI_ADDR_21_1
+
+#define ET024006DHU_EBI_NWE       AVR32_EBI_NWE0_0
+#define ET024006DHU_EBI_NRD       AVR32_EBI_NRD_0
+#define ET024006DHU_EBI_NCS       AVR32_EBI_NCS_0_1
+//! @}
+
+
+#endif  // !EVK1105_REVA
+
+#endif  // _EVK1105_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.c

@@ -0,0 +1,346 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AT32UC3A EVK1105 board LEDs support package.
+ *
+ * This file contains definitions and services related to the LED features of
+ * the EVK1105 board.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include <avr32/io.h>
+#include "preprocessor.h"
+#include "compiler.h"
+#include "evk1105.h"
+#include "led.h"
+
+
+//! Structure describing LED hardware connections.
+typedef const struct
+{
+  struct
+  {
+    U32 PORT;     //!< LED GPIO port.
+    U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port.
+  } GPIO; //!< LED GPIO descriptor.
+  struct
+  {
+    S32 CHANNEL;  //!< LED PWM channel (< 0 if N/A).
+    S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A).
+  } PWM;  //!< LED PWM descriptor.
+} tLED_DESCRIPTOR;
+
+
+//! Hardware descriptors of all LEDs.
+static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] =
+{
+#define INSERT_LED_DESCRIPTOR(LED_NO, unused)                 \
+  {                                                           \
+    {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\
+    {LED##LED_NO##_PWM,       LED##LED_NO##_PWM_FUNCTION    } \
+  },
+  MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~)
+#undef INSERT_LED_DESCRIPTOR
+};
+
+
+//! Saved state of all LEDs.
+static volatile U32 LED_State = (1 << LED_COUNT) - 1;
+
+
+U32 LED_Read_Display(void)
+{
+  return LED_State;
+}
+
+
+void LED_Display(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor;
+  volatile avr32_gpio_port_t *led_gpio_port;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  LED_State = leds;
+
+  // For all LEDs...
+  for (led_descriptor = &LED_DESCRIPTOR[0];
+       led_descriptor < LED_DESCRIPTOR + LED_COUNT;
+       led_descriptor++)
+  {
+    // Set the LED to the requested state.
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    if (leds & 1)
+    {
+      led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;
+    }
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= 1;
+  }
+}
+
+
+U32 LED_Read_Display_Mask(U32 mask)
+{
+  return Rd_bits(LED_State, mask);
+}
+
+
+void LED_Display_Mask(U32 mask, U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  mask &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Wr_bits(LED_State, mask, leds);
+
+  // While there are specified LEDs left to manage...
+  while (mask)
+  {
+    // Select the next specified LED and set it to the requested state.
+    led_shift = 1 + ctz(mask);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    leds >>= led_shift - 1;
+    if (leds & 1)
+    {
+      led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;
+    }
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= 1;
+    mask >>= led_shift;
+  }
+}
+
+
+Bool LED_Test(U32 leds)
+{
+  return Tst_bits(LED_State, leds);
+}
+
+
+void LED_Off(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Clr_bits(LED_State, leds);
+
+  // While there are specified LEDs left to manage...
+  while (leds)
+  {
+    // Select the next specified LED and turn it off.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    led_gpio_port->ovrs  = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= led_shift;
+  }
+}
+
+
+void LED_On(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Set_bits(LED_State, leds);
+
+  // While there are specified LEDs left to manage...
+  while (leds)
+  {
+    // Select the next specified LED and turn it on.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    led_gpio_port->ovrc  = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= led_shift;
+  }
+}
+
+
+void LED_Toggle(U32 leds)
+{
+  // Use the LED descriptors to get the connections of a given LED to the MCU.
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // Make sure only existing LEDs are specified.
+  leds &= (1 << LED_COUNT) - 1;
+
+  // Update the saved state of all LEDs with the requested changes.
+  Tgl_bits(LED_State, leds);
+
+  // While there are specified LEDs left to manage...
+  while (leds)
+  {
+    // Select the next specified LED and toggle it.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    led_gpio_port->ovrt  = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK;
+    led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK;
+    leds >>= led_shift;
+  }
+}
+
+
+U32 LED_Read_Display_Field(U32 field)
+{
+  return Rd_bitfield(LED_State, field);
+}
+
+
+void LED_Display_Field(U32 field, U32 leds)
+{
+  // Move the bit-field to the appropriate position for the bit-mask.
+  LED_Display_Mask(field, leds << ctz(field));
+}
+
+
+U8 LED_Get_Intensity(U32 led)
+{
+  tLED_DESCRIPTOR *led_descriptor;
+
+  // Check that the argument value is valid.
+  led = ctz(led);
+  led_descriptor = &LED_DESCRIPTOR[led];
+  if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0;
+
+  // Return the duty cycle value if the LED PWM channel is enabled, else 0.
+  return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ?
+           AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0;
+}
+
+
+void LED_Set_Intensity(U32 leds, U8 intensity)
+{
+  tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1;
+  volatile avr32_pwm_channel_t *led_pwm_channel;
+  volatile avr32_gpio_port_t *led_gpio_port;
+  U8 led_shift;
+
+  // For each specified LED...
+  for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift)
+  {
+    // Select the next specified LED and check that it has a PWM channel.
+    led_shift = 1 + ctz(leds);
+    led_descriptor += led_shift;
+    if (led_descriptor->PWM.CHANNEL < 0) continue;
+
+    // Initialize or update the LED PWM channel.
+    led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL];
+    if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)))
+    {
+      led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) &
+                             ~(AVR32_PWM_CALG_MASK |
+                               AVR32_PWM_CPOL_MASK |
+                               AVR32_PWM_CPD_MASK);
+      led_pwm_channel->cprd = 0x000000FF;
+      led_pwm_channel->cdty = intensity;
+      AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL;
+    }
+    else
+    {
+      AVR32_PWM.isr;
+      while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL)));
+      led_pwm_channel->cupd = intensity;
+    }
+
+    // Switch the LED pin to its PWM function.
+    led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT];
+    if (led_descriptor->PWM.FUNCTION & 0x1)
+    {
+      led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK;
+    }
+    if (led_descriptor->PWM.FUNCTION & 0x2)
+    {
+      led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK;
+    }
+    else
+    {
+      led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK;
+    }
+    led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK;
+  }
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/EVK1105/led.h

@@ -0,0 +1,187 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief AT32UC3A EVK1105 board LEDs support package.
+ *
+ * This file contains definitions and services related to the LED features of
+ * the EVK1105 board.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 AT32UC3A devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _LED_H_
+#define _LED_H_
+
+#include "compiler.h"
+
+
+/*! \name Identifiers of LEDs to Use with LED Functions
+ */
+//! @{
+#define LED0  0x01
+#define LED1  0x02
+#define LED2  0x04
+#define LED3  0x08
+//! @}
+
+
+/*! \brief Gets the last state of all LEDs set through the LED API.
+ *
+ * \return State of all LEDs (1 bit per LED).
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U32 LED_Read_Display(void);
+
+/*! \brief Sets the state of all LEDs.
+ *
+ * \param leds New state of all LEDs (1 bit per LED).
+ *
+ * \note The pins of all LEDs are set to GPIO output mode.
+ */
+extern void LED_Display(U32 leds);
+
+/*! \brief Gets the last state of the specified LEDs set through the LED API.
+ *
+ * \param mask LEDs of which to get the state (1 bit per LED).
+ *
+ * \return State of the specified LEDs (1 bit per LED).
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U32 LED_Read_Display_Mask(U32 mask);
+
+/*! \brief Sets the state of the specified LEDs.
+ *
+ * \param mask LEDs of which to set the state (1 bit per LED).
+ *
+ * \param leds New state of the specified LEDs (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Display_Mask(U32 mask, U32 leds);
+
+/*! \brief Tests the last state of the specified LEDs set through the LED API.
+ *
+ * \param leds LEDs of which to test the state (1 bit per LED).
+ *
+ * \return \c TRUE if at least one of the specified LEDs has a state on, else
+ *         \c FALSE.
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern Bool LED_Test(U32 leds);
+
+/*! \brief Turns off the specified LEDs.
+ *
+ * \param leds LEDs to turn off (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Off(U32 leds);
+
+/*! \brief Turns on the specified LEDs.
+ *
+ * \param leds LEDs to turn on (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_On(U32 leds);
+
+/*! \brief Toggles the specified LEDs.
+ *
+ * \param leds LEDs to toggle (1 bit per LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Toggle(U32 leds);
+
+/*! \brief Gets as a bit-field the last state of the specified LEDs set through
+ *         the LED API.
+ *
+ * \param field LEDs of which to get the state (1 bit per LED).
+ *
+ * \return State of the specified LEDs (1 bit per LED, beginning with the first
+ *         specified LED).
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U32 LED_Read_Display_Field(U32 field);
+
+/*! \brief Sets as a bit-field the state of the specified LEDs.
+ *
+ * \param field LEDs of which to set the state (1 bit per LED).
+ * \param leds New state of the specified LEDs (1 bit per LED, beginning with
+ *             the first specified LED).
+ *
+ * \note The pins of the specified LEDs are set to GPIO output mode.
+ */
+extern void LED_Display_Field(U32 field, U32 leds);
+
+/*! \brief Gets the intensity of the specified LED.
+ *
+ * \param led LED of which to get the intensity (1 bit per LED; only the least
+ *            significant set bit is used).
+ *
+ * \return Intensity of the specified LED (0x00 to 0xFF).
+ *
+ * \warning The PWM channel of the specified LED is supposed to be used only by
+ *          this module.
+ *
+ * \note The GPIO pin configuration of all LEDs is left unchanged.
+ */
+extern U8 LED_Get_Intensity(U32 led);
+
+/*! \brief Sets the intensity of the specified LEDs.
+ *
+ * \param leds LEDs of which to set the intensity (1 bit per LED).
+ * \param intensity New intensity of the specified LEDs (0x00 to 0xFF).
+ *
+ * \warning The PWM channels of the specified LEDs are supposed to be used only
+ *          by this module.
+ *
+ * \note The pins of the specified LEDs are set to PWM output mode.
+ */
+extern void LED_Set_Intensity(U32 leds, U8 intensity);
+
+
+#endif  // _LED_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/board.h

@@ -0,0 +1,120 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <avr32/io.h>
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100           1   //!< AT32UC3A EVK1100 board.
+#define EVK1101           2   //!< AT32UC3B EVK1101 board.
+#define UC3C_EK           3   //!< AT32UC3C UC3C_EK board.
+#define EVK1104           4   //!< AT32UC3A3 EVK1104 board.
+#define EVK1105           5   //!< AT32UC3A EVK1105 board.
+#define STK1000           6   //!< AT32AP7000 STK1000 board.
+#define NGW100            7   //!< AT32AP7000 NGW100 board.
+#define STK600_RCUC3L0    8   //!< STK600 RCUC3L0 board.
+#define UC3L_EK           9   //!< AT32UC3L-EK board.
+#define USER_BOARD        99  //!< User-reserved board (if any).
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102           1   //!< AT32UC3B EXT1102 board.
+#define MC300             2   //!< AT32UC3 MC300 board.
+#define USER_EXT_BOARD    99  //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+  #include "EVK1100/evk1100.h"
+#elif BOARD == EVK1101
+  #include "EVK1101/evk1101.h"
+#elif BOARD == UC3C_EK
+  #include "UC3C_EK/uc3c_ek.h"
+#elif BOARD == EVK1104
+  #include "EVK1104/evk1104.h"
+#elif BOARD == EVK1105
+  #include "EVK1105/evk1105.h"
+#elif BOARD == STK1000
+  #include "STK1000/stk1000.h"
+#elif BOARD == NGW100
+  #include "NGW100/ngw100.h"
+#elif BOARD == STK600_RCUC3L0
+  #include "STK600/RCUC3L0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+  #include "UC3L_EK/uc3l_ek.h"
+#elif BOARD == ARDUINO
+  #include "ARDUINO/arduino.h"
+#else
+  #error No known AVR32 board defined
+#endif
+
+#if (defined EXT_BOARD)
+  #if EXT_BOARD == EXT1102
+    #include "EXT1102/ext1102.h"
+  #elif EXT_BOARD == MC300
+    #include "MC300/mc300.h"
+  #elif EXT_BOARD == USER_EXT_BOARD
+    // User-reserved area: #include the header file of your extension board here
+    // (if any).
+  #endif
+#endif
+
+
+#ifndef FRCOSC
+  #define FRCOSC    AVR32_PM_RCOSC_FREQUENCY  //!< Default RCOsc frequency.
+#endif
+
+
+#endif  // _BOARD_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/BOARDS/board.h.my

@@ -0,0 +1,120 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Standard board header file.
+ *
+ * This file includes the appropriate board header file according to the
+ * defined board.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <avr32/io.h>
+
+/*! \name Base Boards
+ */
+//! @{
+#define EVK1100           1   //!< AT32UC3A EVK1100 board.
+#define EVK1101           2   //!< AT32UC3B EVK1101 board.
+#define UC3C_EK           3   //!< AT32UC3C UC3C_EK board.
+#define EVK1104           4   //!< AT32UC3A3 EVK1104 board.
+#define EVK1105           5   //!< AT32UC3A EVK1105 board.
+#define STK1000           6   //!< AT32AP7000 STK1000 board.
+#define NGW100            7   //!< AT32AP7000 NGW100 board.
+#define STK600_RCUC3L0    8   //!< STK600 RCUC3L0 board.
+#define UC3L_EK           9   //!< AT32UC3L-EK board.
+#define USER_BOARD        99  //!< User-reserved board (if any).
+//! @}
+
+/*! \name Extension Boards
+ */
+//! @{
+#define EXT1102           1   //!< AT32UC3B EXT1102 board.
+#define MC300             2   //!< AT32UC3 MC300 board.
+#define USER_EXT_BOARD    99  //!< User-reserved extension board (if any).
+//! @}
+
+#if BOARD == EVK1100
+  #include "EVK1100/evk1100.h"
+#elif BOARD == EVK1101
+  #include "EVK1101/evk1101.h"
+#elif BOARD == UC3C_EK
+  #include "UC3C_EK/uc3c_ek.h"
+#elif BOARD == EVK1104
+  #include "EVK1104/evk1104.h"
+#elif BOARD == EVK1105
+  #include "EVK1105/evk1105.h"
+#elif BOARD == STK1000
+  #include "STK1000/stk1000.h"
+#elif BOARD == NGW100
+  #include "NGW100/ngw100.h"
+#elif BOARD == STK600_RCUC3L0
+  #include "STK600/RCUC3L0/stk600_rcuc3l0.h"
+#elif BOARD == UC3L_EK
+  #include "UC3L_EK/uc3l_ek.h"
+#elif BOARD == ARDUINO
+  #include "ARDUINO/arduino.h"
+#else
+  #error No known AVR32 board defined
+#endif
+
+#if (defined EXT_BOARD)
+  #if EXT_BOARD == EXT1102
+    #include "EXT1102/ext1102.h"
+  #elif EXT_BOARD == MC300
+    #include "MC300/mc300.h"
+  #elif EXT_BOARD == USER_EXT_BOARD
+    // User-reserved area: #include the header file of your extension board here
+    // (if any).
+  #endif
+#endif
+
+
+#ifndef FRCOSC
+  #define FRCOSC    AVR32_PM_RCOSC_FREQUENCY  //!< Default RCOsc frequency.
+#endif
+
+
+#endif  // _BOARD_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.c

@@ -0,0 +1,653 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Management of the AT45DBX data flash controller through SPI.
+ *
+ * This file manages the accesses to the AT45DBX data flash components.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+//_____  I N C L U D E S ___________________________________________________
+
+#include "conf_access.h"
+
+
+#if AT45DBX_MEM == ENABLE
+
+#include "compiler.h"
+#include "board.h"
+#include "gpio.h"
+#include "spi.h"
+#include "conf_at45dbx.h"
+#include "at45dbx.h"
+
+
+#if AT45DBX_MEM_CNT > 4
+  #error AT45DBX_MEM_CNT must not exceed 4
+#endif
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+/*! \name AT45DBX Group A Commands
+ */
+//! @{
+#define AT45DBX_CMDA_RD_PAGE              0xD2        //!< Main Memory Page Read (Serial/8-bit Mode).
+#define AT45DBX_CMDA_RD_ARRAY_LEG         0xE8        //!< Continuous Array Read, Legacy Command (Serial/8-bit Mode).
+#define AT45DBX_CMDA_RD_ARRAY_LF_SM       0x03        //!< Continuous Array Read, Low-Frequency Mode (Serial Mode).
+#define AT45DBX_CMDA_RD_ARRAY_AF_SM       0x0B        //!< Continuous Array Read, Any-Frequency Mode (Serial Mode).
+#define AT45DBX_CMDA_RD_SECTOR_PROT_REG   0x32        //!< Read Sector Protection Register (Serial/8-bit Mode).
+#define AT45DBX_CMDA_RD_SECTOR_LKDN_REG   0x35        //!< Read Sector Lockdown Register (Serial/8-bit Mode).
+#define AT45DBX_CMDA_RD_SECURITY_REG      0x77        //!< Read Security Register (Serial/8-bit Mode).
+//! @}
+
+/*! \name AT45DBX Group B Commands
+ */
+//! @{
+#define AT45DBX_CMDB_ER_PAGE              0x81        //!< Page Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_ER_BLOCK             0x50        //!< Block Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_ER_SECTOR            0x7C        //!< Sector Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_ER_CHIP              0xC794809A  //!< Chip Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_XFR_PAGE_TO_BUF1     0x53        //!< Main Memory Page to Buffer 1 Transfer (Serial/8-bit Mode).
+#define AT45DBX_CMDB_XFR_PAGE_TO_BUF2     0x55        //!< Main Memory Page to Buffer 2 Transfer (Serial/8-bit Mode).
+#define AT45DBX_CMDB_CMP_PAGE_TO_BUF1     0x60        //!< Main Memory Page to Buffer 1 Compare (Serial/8-bit Mode).
+#define AT45DBX_CMDB_CMP_PAGE_TO_BUF2     0x61        //!< Main Memory Page to Buffer 2 Compare (Serial/8-bit Mode).
+#define AT45DBX_CMDB_PR_BUF1_TO_PAGE_ER   0x83        //!< Buffer 1 to Main Memory Page Program with Built-in Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_PR_BUF2_TO_PAGE_ER   0x86        //!< Buffer 2 to Main Memory Page Program with Built-in Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_PR_BUF1_TO_PAGE      0x88        //!< Buffer 1 to Main Memory Page Program without Built-in Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_PR_BUF2_TO_PAGE      0x89        //!< Buffer 2 to Main Memory Page Program without Built-in Erase (Serial/8-bit Mode).
+#define AT45DBX_CMDB_PR_PAGE_TH_BUF1      0x82        //!< Main Memory Page Program through Buffer 1 (Serial/8-bit Mode).
+#define AT45DBX_CMDB_PR_PAGE_TH_BUF2      0x85        //!< Main Memory Page Program through Buffer 2 (Serial/8-bit Mode).
+#define AT45DBX_CMDB_RWR_PAGE_TH_BUF1     0x58        //!< Auto Page Rewrite through Buffer 1 (Serial/8-bit Mode).
+#define AT45DBX_CMDB_RWR_PAGE_TH_BUF2     0x59        //!< Auto Page Rewrite through Buffer 2 (Serial/8-bit Mode).
+//! @}
+
+/*! \name AT45DBX Group C Commands
+ */
+//! @{
+#define AT45DBX_CMDC_RD_BUF1_LF_SM        0xD1        //!< Buffer 1 Read, Low-Frequency Mode (Serial Mode).
+#define AT45DBX_CMDC_RD_BUF2_LF_SM        0xD3        //!< Buffer 2 Read, Low-Frequency Mode (Serial Mode).
+#define AT45DBX_CMDC_RD_BUF1_AF_SM        0xD4        //!< Buffer 1 Read, Any-Frequency Mode (Serial Mode).
+#define AT45DBX_CMDC_RD_BUF2_AF_SM        0xD6        //!< Buffer 2 Read, Any-Frequency Mode (Serial Mode).
+#define AT45DBX_CMDC_RD_BUF1_AF_8M        0x54        //!< Buffer 1 Read, Any-Frequency Mode (8-bit Mode).
+#define AT45DBX_CMDC_RD_BUF2_AF_8M        0x56        //!< Buffer 2 Read, Any-Frequency Mode (8-bit Mode).
+#define AT45DBX_CMDC_WR_BUF1              0x84        //!< Buffer 1 Write (Serial/8-bit Mode).
+#define AT45DBX_CMDC_WR_BUF2              0x87        //!< Buffer 2 Write (Serial/8-bit Mode).
+#define AT45DBX_CMDC_RD_STATUS_REG        0xD7        //!< Status Register Read (Serial/8-bit Mode).
+#define AT45DBX_CMDC_RD_MNFCT_DEV_ID_SM   0x9F        //!< Manufacturer and Device ID Read (Serial Mode).
+//! @}
+
+/*! \name AT45DBX Group D Commands
+ */
+//! @{
+#define AT45DBX_CMDD_EN_SECTOR_PROT       0x3D2A7FA9  //!< Enable Sector Protection (Serial/8-bit Mode).
+#define AT45DBX_CMDD_DIS_SECTOR_PROT      0x3D2A7F9A  //!< Disable Sector Protection (Serial/8-bit Mode).
+#define AT45DBX_CMDD_ER_SECTOR_PROT_REG   0x3D2A7FCF  //!< Erase Sector Protection Register (Serial/8-bit Mode).
+#define AT45DBX_CMDD_PR_SECTOR_PROT_REG   0x3D2A7FFC  //!< Program Sector Protection Register (Serial/8-bit Mode).
+#define AT45DBX_CMDD_LKDN_SECTOR          0x3D2A7F30  //!< Sector Lockdown (Serial/8-bit Mode).
+#define AT45DBX_CMDD_PR_SECURITY_REG      0x9B000000  //!< Program Security Register (Serial/8-bit Mode).
+#define AT45DBX_CMDD_PR_CONF_REG          0x3D2A80A6  //!< Program Configuration Register (Serial/8-bit Mode).
+#define AT45DBX_CMDD_DEEP_PWR_DN          0xB9        //!< Deep Power-down (Serial/8-bit Mode).
+#define AT45DBX_CMDD_RSM_DEEP_PWR_DN      0xAB        //!< Resume from Deep Power-down (Serial/8-bit Mode).
+//! @}
+
+
+/*! \name Bit-Masks and Values for the Status Register
+ */
+//! @{
+#define AT45DBX_MSK_BUSY                  0x80        //!< Busy status bit-mask.
+#define AT45DBX_BUSY                      0x00        //!< Busy status value (0x00 when busy, 0x80 when ready).
+#define AT45DBX_MSK_DENSITY               0x3C        //!< Device density bit-mask.
+//! @}
+#if AT45DBX_MEM_SIZE == AT45DBX_1MB
+
+/*! \name AT45DB081 Memories
+ */
+//! @{
+#define AT45DBX_DENSITY                   0x24        //!< Device density value.
+#define AT45DBX_BYTE_ADDR_BITS             9          //!< Address bits for byte position within buffer.
+
+//! @}
+#elif AT45DBX_MEM_SIZE == AT45DBX_2MB
+
+/*! \name AT45DB161 Memories
+ */
+//! @{
+#define AT45DBX_DENSITY                   0x2C        //!< Device density value.
+#define AT45DBX_BYTE_ADDR_BITS            10          //!< Address bits for byte position within buffer.
+//! @}
+
+#elif AT45DBX_MEM_SIZE == AT45DBX_4MB
+
+/*! \name AT45DB321 Memories
+ */
+//! @{
+#define AT45DBX_DENSITY                   0x34        //!< Device density value.
+#define AT45DBX_BYTE_ADDR_BITS            10          //!< Address bits for byte position within buffer.
+//! @}
+
+#elif AT45DBX_MEM_SIZE == AT45DBX_8MB
+
+/*! \name AT45DB642 Memories
+ */
+//! @{
+#define AT45DBX_DENSITY                   0x3C        //!< Device density value.
+#define AT45DBX_BYTE_ADDR_BITS            11          //!< Address bits for byte position within buffer.
+//! @}
+
+#else
+  #error AT45DBX_MEM_SIZE is not defined to a supported value
+#endif
+
+//! Address bits for page selection.
+#define AT45DBX_PAGE_ADDR_BITS            (AT45DBX_MEM_SIZE - AT45DBX_PAGE_BITS)
+
+//! Number of bits for addresses within pages.
+#define AT45DBX_PAGE_BITS                 (AT45DBX_BYTE_ADDR_BITS - 1)
+
+//! Page size in bytes.
+#define AT45DBX_PAGE_SIZE                 (1 << AT45DBX_PAGE_BITS)
+
+//! Bit-mask for byte position within buffer in \ref gl_ptr_mem.
+#define AT45DBX_MSK_PTR_BYTE              ((1 << AT45DBX_PAGE_BITS) - 1)
+
+//! Bit-mask for page selection in \ref gl_ptr_mem.
+#define AT45DBX_MSK_PTR_PAGE              (((1 << AT45DBX_PAGE_ADDR_BITS) - 1) << AT45DBX_PAGE_BITS)
+
+//! Bit-mask for byte position within sector in \ref gl_ptr_mem.
+#define AT45DBX_MSK_PTR_SECTOR            ((1 << AT45DBX_SECTOR_BITS) - 1)
+
+
+/*! \brief Sends a dummy byte through SPI.
+ */
+#define spi_write_dummy()                 spi_write(AT45DBX_SPI, 0xFF)
+
+
+//! Boolean indicating whether memory is in busy state.
+static Bool at45dbx_busy;
+
+//! Memory data pointer.
+static U32 gl_ptr_mem;
+
+//! Sector buffer.
+static U8 sector_buf[AT45DBX_SECTOR_SIZE];
+
+
+/*! \name Control Functions
+ */
+//! @{
+
+
+Bool at45dbx_init(spi_options_t spiOptions, unsigned int pba_hz)
+{
+  // Setup SPI registers according to spiOptions.
+  for (spiOptions.reg = AT45DBX_SPI_FIRST_NPCS;
+       spiOptions.reg < AT45DBX_SPI_FIRST_NPCS + AT45DBX_MEM_CNT;
+       spiOptions.reg++)
+  {
+    if (spi_setupChipReg(AT45DBX_SPI, &spiOptions, pba_hz) != SPI_OK) return KO;
+  }
+
+  // Memory ready.
+  at45dbx_busy = FALSE;
+
+  return OK;
+}
+
+
+/*! \brief Selects or unselects a DF memory.
+ *
+ * \param memidx  Memory ID of DF to select or unselect.
+ * \param bSelect Boolean indicating whether the DF memory has to be selected.
+ */
+static void at45dbx_chipselect_df(U8 memidx, Bool bSelect)
+{
+  if (bSelect)
+  {
+    // Select SPI chip.
+    spi_selectChip(AT45DBX_SPI, AT45DBX_SPI_FIRST_NPCS + memidx);
+  }
+  else
+  {
+    // Unselect SPI chip.
+    spi_unselectChip(AT45DBX_SPI, AT45DBX_SPI_FIRST_NPCS + memidx);
+  }
+}
+
+
+Bool at45dbx_mem_check(void)
+{
+  U8 df;
+  U16 status = 0;
+
+  // DF memory check.
+  for (df = 0; df < AT45DBX_MEM_CNT; df++)
+  {
+    // Select the DF memory to check.
+    at45dbx_chipselect_df(df, TRUE);
+
+    // Send the Status Register Read command.
+    spi_write(AT45DBX_SPI, AT45DBX_CMDC_RD_STATUS_REG);
+
+    // Send a dummy byte to read the status register.
+    spi_write_dummy();
+    spi_read(AT45DBX_SPI, &status);
+
+    // Unselect the checked DF memory.
+    at45dbx_chipselect_df(df, FALSE);
+
+    // Unexpected device density value.
+    if ((status & AT45DBX_MSK_DENSITY) < AT45DBX_DENSITY) return KO;
+  }
+
+  return OK;
+}
+
+
+/*! \brief Waits until the DF is ready.
+ */
+static void at45dbx_wait_ready(void)
+{
+  U16 status;
+
+  // Select the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE);
+
+  // Send the Status Register Read command.
+  spi_write(AT45DBX_SPI, AT45DBX_CMDC_RD_STATUS_REG);
+
+  // Read the status register until the DF is ready.
+  do
+  {
+    // Send a dummy byte to read the status register.
+    spi_write_dummy();
+    spi_read(AT45DBX_SPI, &status);
+  } while ((status & AT45DBX_MSK_BUSY) == AT45DBX_BUSY);
+
+  // Unselect the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+}
+
+
+Bool at45dbx_read_open(U32 sector)
+{
+  U32 addr;
+
+  // Set the global memory pointer to a byte address.
+  gl_ptr_mem = sector << AT45DBX_SECTOR_BITS; // gl_ptr_mem = sector * AT45DBX_SECTOR_SIZE.
+
+  // If the DF memory is busy, wait until it's ready.
+  if (at45dbx_busy) at45dbx_wait_ready();
+  at45dbx_busy = FALSE;
+
+  // Select the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE);
+
+  // Initiate a page read at a given sector.
+
+  // Send the Main Memory Page Read command.
+  spi_write(AT45DBX_SPI, AT45DBX_CMDA_RD_PAGE);
+
+  // Send the three address bytes, which comprise:
+  //  - (24 - (AT45DBX_PAGE_ADDR_BITS + AT45DBX_BYTE_ADDR_BITS)) reserved bits;
+  //  - then AT45DBX_PAGE_ADDR_BITS bits specifying the page in main memory to be read;
+  //  - then AT45DBX_BYTE_ADDR_BITS bits specifying the starting byte address within that page.
+  // NOTE: The bits of gl_ptr_mem above the AT45DBX_MEM_SIZE bits are useless for the local
+  // DF addressing. They are used for DF discrimination when there are several DFs.
+  addr = (Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_PAGE) << AT45DBX_BYTE_ADDR_BITS) |
+         Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE);
+  spi_write(AT45DBX_SPI, LSB2W(addr));
+  spi_write(AT45DBX_SPI, LSB1W(addr));
+  spi_write(AT45DBX_SPI, LSB0W(addr));
+
+  // Send 32 don't care clock cycles to initialize the read operation.
+  spi_write_dummy();
+  spi_write_dummy();
+  spi_write_dummy();
+  spi_write_dummy();
+
+  return OK;
+}
+
+
+void at45dbx_read_close(void)
+{
+  // Unselect the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+
+  // Memory ready.
+  at45dbx_busy = FALSE;
+}
+
+
+Bool at45dbx_write_open(U32 sector)
+{
+  U32 addr;
+
+  // Set the global memory pointer to a byte address.
+  gl_ptr_mem = sector << AT45DBX_SECTOR_BITS; // gl_ptr_mem = sector * AT45DBX_SECTOR_SIZE.
+
+  // If the DF memory is busy, wait until it's ready.
+  if (at45dbx_busy) at45dbx_wait_ready();
+  at45dbx_busy = FALSE;
+
+#if AT45DBX_PAGE_SIZE > AT45DBX_SECTOR_SIZE
+  // Select the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE);
+
+  // Transfer the content of the current page to buffer 1.
+
+  // Send the Main Memory Page to Buffer 1 Transfer command.
+  spi_write(AT45DBX_SPI, AT45DBX_CMDB_XFR_PAGE_TO_BUF1);
+
+  // Send the three address bytes, which comprise:
+  //  - (24 - (AT45DBX_PAGE_ADDR_BITS + AT45DBX_BYTE_ADDR_BITS)) reserved bits;
+  //  - then AT45DBX_PAGE_ADDR_BITS bits specifying the page in main memory to be read;
+  //  - then AT45DBX_BYTE_ADDR_BITS don't care bits.
+  // NOTE: The bits of gl_ptr_mem above the AT45DBX_MEM_SIZE bits are useless for the local
+  // DF addressing. They are used for DF discrimination when there are several DFs.
+  addr = Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_PAGE) << AT45DBX_BYTE_ADDR_BITS;
+  spi_write(AT45DBX_SPI, LSB2W(addr));
+  spi_write(AT45DBX_SPI, LSB1W(addr));
+  spi_write(AT45DBX_SPI, LSB0W(addr));
+
+  // Unselect the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+
+  // Wait for end of page transfer.
+  at45dbx_wait_ready();
+#endif
+
+  // Select the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, TRUE);
+
+  // Initiate a page write at a given sector.
+
+  // Send the Main Memory Page Program through Buffer 1 command.
+  spi_write(AT45DBX_SPI, AT45DBX_CMDB_PR_PAGE_TH_BUF1);
+
+  // Send the three address bytes, which comprise:
+  //  - (24 - (AT45DBX_PAGE_ADDR_BITS + AT45DBX_BYTE_ADDR_BITS)) reserved bits;
+  //  - then AT45DBX_PAGE_ADDR_BITS bits specifying the page in main memory to be written;
+  //  - then AT45DBX_BYTE_ADDR_BITS bits specifying the starting byte address within that page.
+  // NOTE: The bits of gl_ptr_mem above the AT45DBX_MEM_SIZE bits are useless for the local
+  // DF addressing. They are used for DF discrimination when there are several DFs.
+  addr = (Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_PAGE) << AT45DBX_BYTE_ADDR_BITS) |
+         Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE);
+  spi_write(AT45DBX_SPI, LSB2W(addr));
+  spi_write(AT45DBX_SPI, LSB1W(addr));
+  spi_write(AT45DBX_SPI, LSB0W(addr));
+
+  return OK;
+}
+
+
+void at45dbx_write_close(void)
+{
+  // While end of logical sector not reached, zero-fill remaining memory bytes.
+  while (Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_SECTOR))
+  {
+    spi_write(AT45DBX_SPI, 0x00);
+    gl_ptr_mem++;
+  }
+
+  // Unselect the DF memory gl_ptr_mem points to.
+  at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+
+  // Memory busy.
+  at45dbx_busy = TRUE;
+}
+
+
+//! @}
+
+
+/*! \name Single-Byte Access Functions
+ */
+//! @{
+
+
+U8 at45dbx_read_byte(void)
+{
+  U16 data;
+
+  // Memory busy.
+  if (at45dbx_busy)
+  {
+    // Being here, we know that we previously finished a page read.
+    // => We have to access the next page.
+
+    // Memory ready.
+    at45dbx_busy = FALSE;
+
+    // Eventually select the next DF and open the next page.
+    // NOTE: at45dbx_read_open input parameter is a sector.
+    at45dbx_read_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE.
+  }
+
+  // Send a dummy byte to read the next data byte.
+  spi_write_dummy();
+  spi_read(AT45DBX_SPI, &data);
+  gl_ptr_mem++;
+
+  // If end of page reached,
+  if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE))
+  {
+    // unselect the DF memory gl_ptr_mem points to.
+    at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+
+    // Memory busy.
+    at45dbx_busy = TRUE;
+  }
+
+  return data;
+}
+
+
+Bool at45dbx_write_byte(U8 b)
+{
+  // Memory busy.
+  if (at45dbx_busy)
+  {
+    // Being here, we know that we previously launched a page programming.
+    // => We have to access the next page.
+
+    // Eventually select the next DF and open the next page.
+    // NOTE: at45dbx_write_open input parameter is a sector.
+    at45dbx_write_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE.
+  }
+
+  // Write the next data byte.
+  spi_write(AT45DBX_SPI, b);
+  gl_ptr_mem++;
+
+  // If end of page reached,
+  if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE))
+  {
+    // unselect the DF memory gl_ptr_mem points to in order to program the page.
+    at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+
+    // Memory busy.
+    at45dbx_busy = TRUE;
+  }
+
+  return OK;
+}
+
+
+//! @}
+
+
+/*! \name Multiple-Sector Access Functions
+ */
+//! @{
+
+
+Bool at45dbx_read_multiple_sector(U16 nb_sector)
+{
+  while (nb_sector--)
+  {
+    // Read the next sector.
+    at45dbx_read_sector_2_ram(sector_buf);
+    at45dbx_read_multiple_sector_callback(sector_buf);
+  }
+
+  return OK;
+}
+
+
+Bool at45dbx_write_multiple_sector(U16 nb_sector)
+{
+  while (nb_sector--)
+  {
+    // Write the next sector.
+    at45dbx_write_multiple_sector_callback(sector_buf);
+    at45dbx_write_sector_from_ram(sector_buf);
+  }
+
+  return OK;
+}
+
+
+//! @}
+
+
+/*! \name Single-Sector Access Functions
+ */
+//! @{
+
+
+Bool at45dbx_read_sector_2_ram(void *ram)
+{
+  U8 *_ram = ram;
+  U16 i;
+  U16 data;
+
+  // Memory busy.
+  if (at45dbx_busy)
+  {
+    // Being here, we know that we previously finished a page read.
+    // => We have to access the next page.
+
+    // Memory ready.
+    at45dbx_busy = FALSE;
+
+    // Eventually select the next DF and open the next page.
+    // NOTE: at45dbx_read_open input parameter is a sector.
+    at45dbx_read_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE.
+  }
+
+  // Read the next sector.
+  for (i = AT45DBX_SECTOR_SIZE; i; i--)
+  {
+    // Send a dummy byte to read the next data byte.
+    spi_write_dummy();
+    spi_read(AT45DBX_SPI, &data);
+    *_ram++ = data;
+  }
+
+  // Update the memory pointer.
+  gl_ptr_mem += AT45DBX_SECTOR_SIZE;
+
+#if AT45DBX_PAGE_SIZE > AT45DBX_SECTOR_SIZE
+  // If end of page reached,
+  if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE))
+#endif
+  {
+    // unselect the DF memory gl_ptr_mem points to.
+    at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+
+    // Memory busy.
+    at45dbx_busy = TRUE;
+  }
+
+  return OK;
+}
+
+
+Bool at45dbx_write_sector_from_ram(const void *ram)
+{
+  const U8 *_ram = ram;
+  U16 i;
+
+  // Memory busy.
+  if (at45dbx_busy)
+  {
+    // Being here, we know that we previously launched a page programming.
+    // => We have to access the next page.
+
+    // Eventually select the next DF and open the next page.
+    // NOTE: at45dbx_write_open input parameter is a sector.
+    at45dbx_write_open(gl_ptr_mem >> AT45DBX_SECTOR_BITS); // gl_ptr_mem / AT45DBX_SECTOR_SIZE.
+  }
+
+  // Write the next sector.
+  for (i = AT45DBX_SECTOR_SIZE; i; i--)
+  {
+    // Write the next data byte.
+    spi_write(AT45DBX_SPI, *_ram++);
+  }
+
+  // Update the memory pointer.
+  gl_ptr_mem += AT45DBX_SECTOR_SIZE;
+
+#if AT45DBX_PAGE_SIZE > AT45DBX_SECTOR_SIZE
+  // If end of page reached,
+  if (!Rd_bitfield(gl_ptr_mem, AT45DBX_MSK_PTR_BYTE))
+#endif
+  {
+    // unselect the DF memory gl_ptr_mem points to in order to program the page.
+    at45dbx_chipselect_df(gl_ptr_mem >> AT45DBX_MEM_SIZE, FALSE);
+
+    // Memory busy.
+    at45dbx_busy = TRUE;
+  }
+
+  return OK;
+}
+
+
+//! @}
+
+
+#endif  // AT45DBX_MEM == ENABLE

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx.h

@@ -0,0 +1,270 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Management of the AT45DBX data flash controller through SPI.
+ *
+ * This file manages the accesses to the AT45DBX data flash components.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _AT45DBX_H_
+#define _AT45DBX_H_
+
+
+#include "conf_access.h"
+
+#if AT45DBX_MEM == DISABLE
+  #error at45dbx.h is #included although AT45DBX_MEM is disabled
+#endif
+
+
+#include "spi.h"
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+/*! \name Available AT45DBX Sizes
+ *
+ * Number of address bits of available AT45DBX data flash memories.
+ *
+ * \note Only memories with page sizes of at least 512 bytes (sector size) are
+ *       supported.
+ */
+//! @{
+#define AT45DBX_1MB             20
+#define AT45DBX_2MB             21
+#define AT45DBX_4MB             22
+#define AT45DBX_8MB             23
+//! @}
+
+// AT45DBX_1MB
+#define AT45DBX_SECTOR_BITS     			8		  //! Number of bits for addresses within sectors.
+// AT45DBX_2MB AT45DBX_4MB AT45DBX_8MB
+//#define AT45DBX_SECTOR_BITS     			9		  //! Number of bits for addresses within sectors.
+
+//! Sector size in bytes.
+#define AT45DBX_SECTOR_SIZE     (1 << AT45DBX_SECTOR_BITS)
+
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+/*! \name Control Functions
+ */
+//! @{
+
+/*! \brief Initializes the data flash controller and the SPI channel by which
+ *         the DF is controlled.
+ *
+ * \param spiOptions  Initialization options of the DF SPI channel.
+ * \param pba_hz      SPI module input clock frequency (PBA clock, Hz).
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ */
+extern Bool at45dbx_init(spi_options_t spiOptions, unsigned int pba_hz);
+
+/*! \brief Performs a memory check on all DFs.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ */
+extern Bool at45dbx_mem_check(void);
+
+/*! \brief Opens a DF memory in read mode at a given sector.
+ *
+ * \param sector  Start sector.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ *
+ * \note Sector may be page-unaligned (depending on the DF page size).
+ */
+extern Bool at45dbx_read_open(U32 sector);
+
+/*! \brief Unselects the current DF memory.
+ */
+extern void at45dbx_read_close(void);
+
+/*! \brief This function opens a DF memory in write mode at a given sector.
+ *
+ * \param sector  Start sector.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ *
+ * \note Sector may be page-unaligned (depending on the DF page size).
+ *
+ * \note If \ref AT45DBX_PAGE_SIZE > \ref AT45DBX_SECTOR_SIZE, page content is
+ *       first loaded in buffer to then be partially updated by write byte or
+ *       write sector functions.
+ */
+extern Bool at45dbx_write_open(U32 sector);
+
+/*! \brief Fills the end of the current logical sector and launches page programming.
+ */
+extern void at45dbx_write_close(void);
+
+//! @}
+
+
+/*! \name Single-Byte Access Functions
+ */
+//! @{
+
+/*! \brief Performs a single byte read from DF memory.
+ *
+ * \return The read byte.
+ *
+ * \note First call must be preceded by a call to the \ref at45dbx_read_open
+ *       function.
+ */
+extern U8 at45dbx_read_byte(void);
+
+/*! \brief Performs a single byte write to DF memory.
+ *
+ * \param b The byte to write.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ *
+ * \note First call must be preceded by a call to the \ref at45dbx_write_open
+ *       function.
+ */
+extern Bool at45dbx_write_byte(U8 b);
+
+//! @}
+
+
+/*! \name Multiple-Sector Access Functions
+ */
+//! @{
+
+/*! \brief Reads \a nb_sector sectors from DF memory.
+ *
+ * Data flow is: DF -> callback.
+ *
+ * \param nb_sector Number of contiguous sectors to read.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ *
+ * \note First call must be preceded by a call to the \ref at45dbx_read_open
+ *       function.
+ *
+ * \note As \ref AT45DBX_PAGE_SIZE is always a multiple of
+ *       \ref AT45DBX_SECTOR_SIZE, there is no need to check page end for each
+ *       byte.
+ */
+extern Bool at45dbx_read_multiple_sector(U16 nb_sector);
+
+/*! \brief Callback function invoked after each sector read during
+ *         \ref at45dbx_read_multiple_sector.
+ *
+ * \param psector Pointer to read sector.
+ */
+extern void at45dbx_read_multiple_sector_callback(const void *psector);
+
+/*! \brief Writes \a nb_sector sectors to DF memory.
+ *
+ * Data flow is: callback -> DF.
+ *
+ * \param nb_sector Number of contiguous sectors to write.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ *
+ * \note First call must be preceded by a call to the \ref at45dbx_write_open
+ *       function.
+ *
+ * \note As \ref AT45DBX_PAGE_SIZE is always a multiple of
+ *       \ref AT45DBX_SECTOR_SIZE, there is no need to check page end for each
+ *       byte.
+ */
+extern Bool at45dbx_write_multiple_sector(U16 nb_sector);
+
+/*! \brief Callback function invoked before each sector write during
+ *         \ref at45dbx_write_multiple_sector.
+ *
+ * \param psector Pointer to sector to write.
+ */
+extern void at45dbx_write_multiple_sector_callback(void *psector);
+
+//! @}
+
+
+/*! \name Single-Sector Access Functions
+ */
+//! @{
+
+/*! \brief Reads 1 DF sector to a RAM buffer.
+ *
+ * Data flow is: DF -> RAM.
+ *
+ * \param ram Pointer to RAM buffer.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ *
+ * \note First call must be preceded by a call to the \ref at45dbx_read_open
+ *       function.
+ */
+extern Bool at45dbx_read_sector_2_ram(void *ram);
+
+/*! \brief Writes 1 DF sector from a RAM buffer.
+ *
+ * Data flow is: RAM -> DF.
+ *
+ * \param ram Pointer to RAM buffer.
+ *
+ * \retval OK Success.
+ * \retval KO Failure.
+ *
+ * \note First call must be preceded by a call to the \ref at45dbx_write_open
+ *       function.
+ */
+extern Bool at45dbx_write_sector_from_ram(const void *ram);
+
+//! @}
+
+
+#endif  // _AT45DBX_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.c

@@ -0,0 +1,234 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief CTRL_ACCESS interface for the AT45DBX data flash controller.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+//_____  I N C L U D E S ___________________________________________________
+
+#include "conf_access.h"
+
+
+#if AT45DBX_MEM == ENABLE
+
+#include "conf_at45dbx.h"
+#include "at45dbx.h"
+#include "at45dbx_mem.h"
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+//! Whether to detect write accesses to the memory.
+#define AT45DBX_MEM_TEST_CHANGE_STATE     ENABLED
+
+
+#if (ACCESS_USB == ENABLED || ACCESS_MEM_TO_RAM == ENABLED) && AT45DBX_MEM_TEST_CHANGE_STATE == ENABLED
+
+//! Memory data modified flag.
+static volatile Bool s_b_data_modify = FALSE;
+
+#endif
+
+
+/*! \name Control Interface
+ */
+//! @{
+
+
+Ctrl_status at45dbx_test_unit_ready(void)
+{
+  return (at45dbx_mem_check() == OK) ? CTRL_GOOD : CTRL_NO_PRESENT;
+}
+
+
+Ctrl_status at45dbx_read_capacity(U32 *u32_nb_sector)
+{
+  *u32_nb_sector = (AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) - 1;
+
+  return CTRL_GOOD;
+}
+
+
+Bool at45dbx_wr_protect(void)
+{
+  return FALSE;
+}
+
+
+Bool at45dbx_removal(void)
+{
+  return FALSE;
+}
+
+
+//! @}
+
+
+#if ACCESS_USB == ENABLED
+
+#include "usb_drv.h"
+#include "scsi_decoder.h"
+
+
+/*! \name MEM <-> USB Interface
+ */
+//! @{
+
+
+Ctrl_status at45dbx_usb_read_10(U32 addr, U16 nb_sector)
+{
+  if (addr + nb_sector > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL;
+
+  at45dbx_read_open(addr);
+  at45dbx_read_multiple_sector(nb_sector);
+  at45dbx_read_close();
+
+  return CTRL_GOOD;
+}
+
+
+void at45dbx_read_multiple_sector_callback(const void *psector)
+{
+  U16 data_to_transfer = AT45DBX_SECTOR_SIZE;
+
+  // Transfer read sector to the USB interface.
+  while (data_to_transfer)
+  {
+    while (!Is_usb_in_ready(g_scsi_ep_ms_in))
+    {
+      if(!Is_usb_endpoint_enabled(g_scsi_ep_ms_in))
+         return; // USB Reset
+    }         
+
+    Usb_reset_endpoint_fifo_access(g_scsi_ep_ms_in);
+    data_to_transfer = usb_write_ep_txpacket(g_scsi_ep_ms_in, psector,
+                                             data_to_transfer, &psector);
+    Usb_ack_in_ready_send(g_scsi_ep_ms_in);
+  }
+}
+
+
+Ctrl_status at45dbx_usb_write_10(U32 addr, U16 nb_sector)
+{
+  if (addr + nb_sector > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL;
+
+#if AT45DBX_MEM_TEST_CHANGE_STATE == ENABLED
+  if (nb_sector) s_b_data_modify = TRUE;
+#endif
+
+  at45dbx_write_open(addr);
+  at45dbx_write_multiple_sector(nb_sector);
+  at45dbx_write_close();
+
+  return CTRL_GOOD;
+}
+
+
+void at45dbx_write_multiple_sector_callback(void *psector)
+{
+  U16 data_to_transfer = AT45DBX_SECTOR_SIZE;
+
+  // Transfer sector to write from the USB interface.
+  while (data_to_transfer)
+  {
+    while (!Is_usb_out_received(g_scsi_ep_ms_out))
+    {
+      if(!Is_usb_endpoint_enabled(g_scsi_ep_ms_out))
+         return; // USB Reset
+    }         
+
+    Usb_reset_endpoint_fifo_access(g_scsi_ep_ms_out);
+    data_to_transfer = usb_read_ep_rxpacket(g_scsi_ep_ms_out, psector,
+                                            data_to_transfer, &psector);
+    Usb_ack_out_received_free(g_scsi_ep_ms_out);
+  }
+}
+
+
+//! @}
+
+#endif  // ACCESS_USB == ENABLED
+
+
+#if ACCESS_MEM_TO_RAM == ENABLED
+
+/*! \name MEM <-> RAM Interface
+ */
+//! @{
+
+
+Ctrl_status at45dbx_df_2_ram(U32 addr, void *ram)
+{
+  if (addr + 1 > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL;
+
+  at45dbx_read_open(addr);
+  at45dbx_read_sector_2_ram(ram);
+  at45dbx_read_close();
+
+  return CTRL_GOOD;
+}
+
+
+Ctrl_status at45dbx_ram_2_df(U32 addr, const void *ram)
+{
+  if (addr + 1 > AT45DBX_MEM_CNT << (AT45DBX_MEM_SIZE - AT45DBX_SECTOR_BITS)) return CTRL_FAIL;
+
+#if AT45DBX_MEM_TEST_CHANGE_STATE == ENABLED
+  s_b_data_modify = TRUE;
+#endif
+
+  at45dbx_write_open(addr);
+  at45dbx_write_sector_from_ram(ram);
+  at45dbx_write_close();
+
+  return CTRL_GOOD;
+}
+
+
+//! @}
+
+#endif  // ACCESS_MEM_TO_RAM == ENABLED
+
+
+#endif  // AT45DBX_MEM == ENABLE

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/MEMORY/DATA_FLASH/AT45DBX/at45dbx_mem.h

@@ -0,0 +1,164 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief CTRL_ACCESS interface for the AT45DBX data flash controller.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _AT45DBX_MEM_H_
+#define _AT45DBX_MEM_H_
+
+
+#include "conf_access.h"
+
+#if AT45DBX_MEM == DISABLE
+  #error at45dbx_mem.h is #included although AT45DBX_MEM is disabled
+#endif
+
+
+#include "ctrl_access.h"
+
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+/*! \name Control Interface
+ */
+//! @{
+
+/*! \brief Tests the memory state and initializes the memory if required.
+ *
+ * The TEST UNIT READY SCSI primary command allows an application client to poll
+ * a LUN until it is ready without having to allocate memory for returned data.
+ *
+ * This command may be used to check the media status of LUNs with removable
+ * media.
+ *
+ * \return Status.
+ */
+extern Ctrl_status at45dbx_test_unit_ready(void);
+
+/*! \brief Returns the address of the last valid sector in the memory.
+ *
+ * \param u32_nb_sector Pointer to the address of the last valid sector.
+ *
+ * \return Status.
+ */
+extern Ctrl_status at45dbx_read_capacity(U32 *u32_nb_sector);
+
+/*! \brief Returns the write-protection state of the memory.
+ *
+ * \return \c TRUE if the memory is write-protected, else \c FALSE.
+ *
+ * \note Only used by removable memories with hardware-specific write
+ *       protection.
+ */
+extern Bool at45dbx_wr_protect(void);
+
+/*! \brief Tells whether the memory is removable.
+ *
+ * \return \c TRUE if the memory is removable, else \c FALSE.
+ */
+extern Bool at45dbx_removal(void);
+
+//! @}
+
+
+#if ACCESS_USB == ENABLED
+
+/*! \name MEM <-> USB Interface
+ */
+//! @{
+
+/*! \brief Tranfers data from the memory to USB.
+ *
+ * \param addr      Address of first memory sector to read.
+ * \param nb_sector Number of sectors to transfer.
+ *
+ * \return Status.
+ */
+extern Ctrl_status at45dbx_usb_read_10(U32 addr, U16 nb_sector);
+
+/*! \brief Tranfers data from USB to the memory.
+ *
+ * \param addr      Address of first memory sector to write.
+ * \param nb_sector Number of sectors to transfer.
+ *
+ * \return Status.
+ */
+extern Ctrl_status at45dbx_usb_write_10(U32 addr, U16 nb_sector);
+
+//! @}
+
+#endif
+
+
+#if ACCESS_MEM_TO_RAM == ENABLED
+
+/*! \name MEM <-> RAM Interface
+ */
+//! @{
+
+/*! \brief Copies 1 data sector from the memory to RAM.
+ *
+ * \param addr  Address of first memory sector to read.
+ * \param ram   Pointer to RAM buffer to write.
+ *
+ * \return Status.
+ */
+extern Ctrl_status at45dbx_df_2_ram(U32 addr, void *ram);
+
+/*! \brief Copies 1 data sector from RAM to the memory.
+ *
+ * \param addr  Address of first memory sector to write.
+ * \param ram   Pointer to RAM buffer to read.
+ *
+ * \return Status.
+ */
+extern Ctrl_status at45dbx_ram_2_df(U32 addr, const void *ram);
+
+//! @}
+
+#endif
+
+
+#endif  // _AT45DBX_MEM_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/v2.7.0/revision.txt

@@ -0,0 +1 @@
+Revision: 2491

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/wl_os.h

@@ -0,0 +1,35 @@
+#ifndef WL_OS_H
+#define WL_OS_H
+
+#include <stdarg.h>
+#include <stdlib.h>
+
+void *owl_os_alloc(size_t size);
+void *owl_os_realloc(void *ptr, size_t size);
+void owl_os_free(void *p);
+void *owl_os_memcpy(void *dst, const void *src, size_t n);
+void *owl_os_memset(void *s, int c, size_t n);
+void *owl_os_memmove(void *dst, const void *src, size_t n);
+size_t owl_os_strlen(char *s);
+char *owl_os_strncpy(char *dst, const char *src, size_t n);
+int owl_os_strncmp(const char *s1, const char *s2, size_t n);
+int owl_os_strcmp(const char *s1, const char *s2);
+char *owl_os_strcpy(char *dst, const char *src);
+char *owl_os_strdup(const char *s);
+char *owl_os_strndup(const char *s, size_t n);
+int owl_os_memcmp(const void *s1, const void *s2, size_t n);
+long int owl_os_strtol(const char *nptr, char **endptr, int base);
+char *owl_os_strchr(const char *s, int c);
+char *owl_os_strrchr(const char *s, int c);
+int owl_os_strcasecmp(const char *s1, const char *s2);
+char *owl_os_strstr(const char *haystack, const char *needle);
+
+int owl_os_snprintf(char *str, size_t size, const char *format, ...)
+        __attribute__((format(printf, 3, 4)));
+
+int owl_os_vprintf(const char *format, va_list arg); /* debug only */
+int owl_os_printf(const char *format, ...) /* debug only */
+        __attribute__((format(printf, 1, 2)));
+
+#endif /* WL_OS_H */
+

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/wl_sdio.h

@@ -0,0 +1,172 @@
+/*!
+ *  \file wl_sdio.h
+ *  \brief SDIO interface for wl_api.
+ *  Copyright (C) 2010 HD Wireless AB
+ *
+ *  You should have received a copy of the license along with this library.
+ */
+
+#ifndef WL_SDIO_H
+#define WL_SDIO_H
+
+/** \defgroup wl_sdio SDIO Interface
+ *
+ * These functions implement the interface that the wl_api library
+ * needs to work with a SDIO transport layer.
+ *
+ * The functions prototyped here must be implemented when porting the
+ * wl_api library to a new platform with a different SDIO configuration
+ *
+ * On platforms supported by H&D Wireless these functions are
+ * implemented in the file avr32_sdio.c
+ *
+ *  @{
+ */
+
+/**
+ * Maximum transfer size. This will set an upper limit on the len parameter
+ * passed to owl_sdio_tx() and owl_sdio_rx().
+ *
+ */ 
+#define MAX_BLOCK_LEN 512
+
+
+/**
+ * This flag might be set when owl_sdio_cmd() is called in case the cmd will
+ * be followed by a data transfer. If the flag is set, the transfer direction is
+ * from the device to the host (read). Otherwise, the transfer direction is
+ * from the host to the device (write).
+ *
+ */
+ #define CMD_FLAG_TO_HOST (1 << 0)
+
+
+/**
+ * Indicates that the sdio driver needs to be polled in order to make
+ * forward progress, i.e. it does not support interrupts
+ *
+ * The actual polling will result in owl_sdio_cmd() being called to
+ * request status information from the device.
+ *
+ * To activate polling, this flag should be set in owl_sdio_init().
+ */
+#define SDIO_FLAG_POLL (1 << 0)
+
+/**
+ * Indicates that the sdio driver only supports 1-bit mode.
+ *
+ * To set 1-bit mode, this flag should be set in owl_sdio_init().
+ */
+#define SDIO_FLAG_1BIT_MODE (1 << 1)
+
+/**
+ * This function will be invoked when wlan initialization should be performed,
+ * this happens when the wl_fw_download() function in the transport group of
+ * wl_api is invoked.
+ *
+ * The wifi device supports sdio high speed mode and clock frequencies up to
+ * 50 MHz.
+ *
+ * The function is responsible for doing any necessary sdio initialization such
+ * as allocating gpio's, setting up the mci master, one time allocations of
+ * dma buffers etc.
+ *
+ * @param flags is an out parameter that should hold any sdio flags upon return.
+ *        The avaible flags are prefixed with SDIO_FLAG_
+ * 
+ *
+ */
+void owl_sdio_init(uint8_t *flags);
+
+
+
+/**
+ * This function will be invoked when an sdio cmd should be sent to the
+ * device.
+ *
+ * @param idx is the sdio command number
+ * @param arg is the sdio command argument
+ * @param flags specifies other options, such as any transfer direction.
+ * @param rsp should hold the command response upon return. If null, the
+ *        response can be ignored.
+ * @param data holds a pointer to any data that might follow the command. This
+ *        allows the sdio driver to setup dma transfers while waiting for the
+ *        command response. NULL if no data transfer will follow. Note that
+ *        the same data pointer will be passed to owl_sdio_tx(), which should
+ *        start the actual transfer.
+ * @param len is the length of the data buffer.
+ *
+ */
+void owl_sdio_cmd(uint8_t idx, uint32_t arg, uint8_t flags, uint32_t *rsp,
+                       const uint8_t *data, uint16_t len);
+
+
+/**
+ * This function will be invoked when data should be transmitted to the device.
+ *
+ * If wl_fw_downlad() was called with the size_align parameter set to non-zero,
+ * the pad parameter should be used. If the pad parameter is not 0, additional
+ * data must be transmitted after the data buffer has be sent. Depending on
+ * how the data buffer was first allocated (probably by an TCP/IP stack), it
+ * might be safe or unsafe to continue reading beyond the data buffer to
+ * transmit the additional padding bytes.
+ *
+ * @param data holds a pointer to the data to transmit, the pointer is the
+ *            same as the one passed to wl_tx().
+ * @param len is the number of bytes that should be transmitted, including
+ *            padding.
+ * @param pad is the number of padding bytes to send.
+ *
+ */
+void owl_sdio_tx(const uint8_t *data, uint16_t len, uint8_t pad);
+
+
+/**
+ * This function will be invoked when data should be received from the device.
+ *
+ * @param data should hold the read data upon return.
+ * @param len is the number of bytes to read.
+ *
+ */
+void owl_sdio_rx(uint8_t *data, uint16_t len);
+
+
+/**
+ * Invoked when sdio rx interrupts from the device should be enabled or
+ * disabled. 
+ *
+ * If SDIO_FLAG_POLL was set in wl_spi_init(), then this function can be
+ * left empty.
+ * 
+ * @param enable specifies if interrupts should be enabled or disabled.
+ *
+ */
+void owl_sdio_irq(uint8_t enable);
+
+
+/**
+ * Delay executiom for the specified number of ms. This function will be called
+ * with delays in the 10-20 ms range during fw download and startup of the
+ * Wi-Fi device. This function can be implemented with a simple for-loop if
+ * desired (beware of optimization). The timing does not have to be accurate as
+ * long as the actual delay becomes at least the specified number of ms.
+ *
+ * @param ms is the minimal amount of time to wait [ms].
+ *
+ */
+void owl_sdio_mdelay(uint32_t ms);
+
+
+/**
+ * This function should be called whenever an interrupt is detected. It can
+ * be called from an interrupt context.
+ *
+ * If SDIO_FLAG_POLL was set in owl_sdio_init(), then wl_sdio_irq()
+ * should never be called.
+ *
+ */
+extern void wl_sdio_irq(void);
+
+/*!  @} */
+
+#endif

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/wl_spi.h

@@ -0,0 +1,185 @@
+/*!
+ *  \file wl_spi.h
+ *  \brief SPI interface for wl_api.
+ *  Copyright (C) 2010 HD Wireless AB
+ *
+ *  You should have received a copy of the license along with this library.
+ */
+
+#ifndef WL_SPI_H
+#define WL_SPI_H
+
+#ifndef WITHOUT_STDINT
+#include <stdint.h>
+#endif
+
+/** \defgroup wl_spi SPI Interface
+ *
+ * These functions implement the interface that the wl_api library
+ * needs to work with a SPI transport layer.
+ *
+ * The functions prototyped here must be implemented when porting the
+ * wl_api library to a new platform with a different SPI configuration
+ *
+ * On platforms supported by H&D Wireless these functions are
+ * implemented in the file avr32_spi.c
+ *
+ *  @{
+ */
+
+/**
+ * Maximum transfer size. This will set an upper limit on the len parameter
+ * passed to owl_spi_txrx().
+ *
+ *
+ */ 
+#define MAX_BLOCK_LEN                 512
+
+
+/**
+ * Indicates that the spi driver needs to be polled in order to make
+ * forward progress, i.e. it does not support interrupts through SD pin 8.
+ *
+ * The actual polling will result in owl_spi_txrx() being call to
+ * request status information from the device.
+ *
+ * To activate polling, this flag should be set in owl_spi_init().
+ *
+ * See wl_poll() and wl_register_rx_isr() for more information regarding
+ * polled and interrupt modes.
+ *
+ */
+#define SPI_FLAG_POLL (1 << 0)
+
+
+/**
+ * This function will be invoked when wlan device initialization should be
+ * performed, this happens when the wl_fw_download() function in the transport
+ * group of wl_api is invoked.
+ *
+ * The wifi device requires spi mode 3, i.e. clock polarity high and sample
+ * on second phase. This corresponds to CPOL=1, CPHA=1. Maximum frequency on
+ * spi clock is 30 MHz.
+ *
+ * The function is also responsible for doing any necessary spi initialization
+ * such as allocating gpio's, setting up the SPI master, one time allocations of
+ * dma buffers etc.
+ *
+ *
+ * If the SPB105 device is used, two signals; POWER (pin 10 on SPB105) and
+ * SHUTDOWN (pin 4 on SPB105) might be connected to gpio's on the host.
+ * The GPIO_POWER_PIN is the main power supply to the device. The
+ * GPIO_SHUTDOWN_PIN (active low) should be defined as an input.
+ *
+ * After GPIO_POWER_PIN is pulled high by the host, the device will pull the
+ * GPIO_SHUTDOWN_PIN high once the device is properly powered.
+ *
+ * However, if pin 4 (GPIO_SHUTDOWN_PIN) is not connected to the host, a delay
+ * of up to 250 ms must be added after GPIO_POWER_PIN is pulled high to ensure
+ * that startup is completed. The actual time is usually much shorter, therefore
+ * one might try to reduce the delay for a particualar hardware design.
+ * 
+ * On SPB104, the GPIO_POWER_PIN will be connected to VCC and GPIO_SHUTDOWN_PIN
+ * will be unconnected; hence we have to make sure that we have enough delay
+ * after powering on the host. Since the device power-on usually happens at the
+ * same time as the host power-on, the startup time of the host can be
+ * subtracted from any delay put into owl_spi_init().
+ *
+ * @param flags is an out parameter that should hold any spi flags upon return.
+ *        The avaible flags are prefixed with SPI_FLAG_
+ *
+ * @return 0 on success
+ *         -1 if any error occurs
+ *
+ */
+int owl_spi_init(uint8_t *flags);
+
+
+/**
+ * Invoked when a spi transfer should be performed.
+ * 
+ * All buffers that are allocated by the wl library will have a size that is
+ * aligned to 4. If size-unaligned data is passed to this function, it is
+ * always allocated by the ip stack. If 4-byte size alignment (e.g. for DMA)
+ * is required, 1-3 extra padding bytes can be transmitted after the in buffer.
+ * These bytes must be 0xff.
+ *
+ * Since size-unaligned data always comes from the ip stack, the out ptr is
+ * always NULL for such data.
+ *
+ * @param in points a buffer which holds the data to be transmitted. If NULL,
+ *        then \a len bytes with the value 0xff should be transmitted on the
+ *        bus.
+ * @param out points a buffer should hold the data received from the device. If
+ *        NULL, any received data can be discarded.
+ * @param len is the length of the in and out buffers.
+ *
+ */
+void owl_spi_txrx(const uint8_t *in, uint8_t* out, uint16_t len);
+
+
+/**
+ * Invoked when spi rx interrupts from the device should be enabled or disabled.
+ * Note that the spi interrupts are obtained from pin 8 on SPB104 or pin 3 from
+ * SPB105. This pin can be be connected to a gpio on the host. The irq line
+ * will signal an interrupt on both edges.
+ *
+ * In general, the wifi device will not issue a new interrupt unless the
+ * last interrupt has been handled. Also, during normal operation (i.e after
+ * the complete callback registered in wl_init() has been invoked),
+ * owl_spi_irq() will never be invoked so interrupts will be enabled all
+ * the time. For the SPI-mode, the purpose of owl_spi_irq() is basically to
+ * make sure that the first interrupt (coming after the reset performed in
+ * owl_spi_init()) is ignored.
+ *
+ * If SPI_FLAG_POLL was set in owl_spi_init(), then this function can be
+ * left empty and the wifi device will be used in polled mode. In polled mode,
+ * the interrupt line is not used. Regardless of polled or interrupt-mode,
+ * wl_poll() must be called to ensure progress of the driver.
+ * 
+ * @param enable specifies if interrupts should be enabled or disabled.
+ *
+ */
+void owl_spi_irq(uint8_t enable);
+
+
+/**
+ * Invoked when the spi cs for the wifi device should be enabled. Note that
+ * multiple calls to owl_spi_txrx() might be done during a 'single' chip
+ * select.
+ *
+ * @param enable specifies whether chip select should be asserted or deasserted,
+ *        The chip select signal is active low, so if enable is '1' then the
+ *        chip select connected to the wifi device should be set to '0'.
+ *        
+ */
+void owl_spi_cs(uint8_t enable);
+
+
+/**
+ * Delay executiom for the specified number of ms. This function will be called
+ * with delays in the 10-20 ms range during fw download and startup of the
+ * Wi-Fi device. This function can be implemented with a simple for-loop if
+ * desired (beware of optimization). The timing does not have to be accurate as
+ * long as the actual delay becomes at least the specified number of ms.
+ *
+ * @param ms is the minimal amount of time to wait [ms].
+ *
+ */
+void owl_spi_mdelay(uint32_t ms);
+
+
+/**
+ * This function should be called whenever an interrupt is detected. It can
+ * be called from an interrupt context.
+ *
+ * If SPI_FLAG_POLL was set in owl_spi_init(), then wl_spi_irq()
+ * should never be called.
+ *
+ */
+extern void wl_spi_irq(void);
+
+
+/*!  @} */
+
+#endif

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/COMPONENTS/WIFI/HD/wlap_api.h

@@ -0,0 +1,154 @@
+/*
+ *  Programming interface for wlap_api.
+ *  Copyright (C) 2011 HD Wireless AB
+ *
+ *  You should have received a copy of the license along with this library.
+ */
+
+/*! \file wlap_api.h *************************************************************
+ *
+ * \brief WiFi AP API
+ *
+ * This file provides the wlap_api interface.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  
+ *  \li SPB104 + EVK1100
+ *  \li SPB104 + EVK1101
+ *  \li SPB104 + EVK1104
+ *  \li SPB104 + EVK1105 (SPI)
+ *  \li SPB104 + EVK1105 (SPI + irq)
+ *  \li SPB105 + EVK1105 (SPI)
+ * - AppNote:
+ *
+ * \author               H&D Wireless AB: \n
+ *
+ *****************************************************************************
+ *
+ * \section intro Introduction
+ * This is the documentation for the WiFi AP Driver API \a wlap_api.
+ *
+ * \section files Main Files
+ * - wlap_api.h : WiFi driver interface.
+ * - libwlap_api_*.*.a - Driver library.
+ * 
+ */
+
+#ifndef WLAP_API_H
+#define WLAP_API_H
+ 
+#define WLAP_API_RELEASE_NAME "unknown"
+
+#include <wl_api.h>
+
+/** \defgroup wl_softap Access Point Mode
+ *
+ * \brief Support the WiFi Access Point mode.
+ *
+ *  @{
+ */
+/*
+ * Station representation 
+ *
+ */
+struct wl_sta_t
+{
+        struct wl_mac_addr_t bssid; /**<  The BSSID of the network. */
+        uint8_t queued_pkt_cnt;     /**< Number of queueud packets for 
+                                       this STA. */
+        uint8_t in_ps;              /**< Is the STA in power save mode. */
+        uint8_t aid;                /**< STA AID */
+};
+
+/* Station list representation. Array of pointers to wl_sta_t entries. */
+struct wl_sta_list_t
+{
+        struct wl_sta_t **sta; /**< The list of pointers to stations */
+        size_t cnt;            /**< Number of stations               */
+};
+
+/*! \brief Get the list of currently associated stations (SoftAP).
+ *
+ * Retrieves the list of current stations from 
+ * the driver. 
+ *
+ * This function is not thread safe. It must be called in the
+ * same execution context as wl_poll().
+ *
+ * @param network_list Output buffer. The API call returns
+ *        a pointer to allocated memory containing the network list.
+ * @return
+ * - WL_SUCCESS
+ * - WL_FAILURE.
+ */
+wl_err_t wlap_get_sta_list(struct wl_sta_list_t **network_list);
+
+
+/*! Callback used to read data from a TX packet.
+ * This function is supplied by the user of the API.
+ *
+ * @param dst Destination buffer. The data should be copied
+ *  to this buffer.
+ * @param src_handle Handle to the source packet from where
+ *  the data should be copied. This handle is the same one that
+ *  is passed in parameter \a pkt_handle to \a wl_process_tx().
+ * @param read_len Number of bytes to copy from \a src_handle
+ *  to \a dst.
+ * @param offset The offset in bytes, counting from the
+ *  beginning of the Ethernet header, from where to copy data.
+ * @return
+ *  - The number of bytes copied. This number may be smaller
+ *    than the length requested in \a read_len but it may not
+ *    be shorter than the length of the packet counting from
+ *    \a offset. In other words, if the caller of this function
+ *    receives a return count that is shorter than \a read_len
+ *    he will assume that all packet data has been read.
+ * - < 0 on error.
+ */
+typedef ssize_t (*wl_pkt_read_cb_t)(char *dst,
+                                    void *src_handle,
+                                    size_t read_len,
+                                    int offset);
+
+/*! \brief Register a data access function for TX packets (SoftAP).
+ *
+ * When a TX data packet has a different representation than a single
+ * contiguous buffer in memory then a packet read function must be
+ * implemented and registered with this call. Whenever the library
+ * needs to read packet data it will call this function to do it.
+ *
+ * This function can be ignored if the TX packet representation is
+ * a single contiguous buffer. This function is only needed in SoftAP
+ * mode.
+ *
+ * @param pkt_read_cb Read callback. 
+ * @param ctx Context 
+ */
+void wl_register_pkt_read_cb(wl_pkt_read_cb_t pkt_read_cb);
+
+/*! \brief Start a network using the SoftAP mode.
+ *
+ * This call will cause the WiFi chip to start sending beacons
+ * and accept associations from WiFi stations.
+ *
+ */
+wl_err_t wlap_start_ap(const char *ssid,
+                     const size_t ssid_len,
+                     const uint8_t channel,
+                     const enum wl_auth_mode auth_mode,
+                     const enum wl_enc_type enc_type);
+
+/*! \brief Disconnect a STA (SoftAP)
+ * 
+ * @param bssid The BSSID of the station to disconnect.
+ * @return 
+ *  - WL_SUCCESS
+ *  - WL_FAILURE.
+ */
+wl_err_t wlap_disconnect_sta(const struct wl_mac_addr_t bssid);
+
+
+/*! @} */ /* End wl_softap group */
+
+
+#endif

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/CPU/CYCLE_COUNTER/cycle_counter.h

@@ -0,0 +1,309 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Cycle counter driver.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32UC devices.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _CYCLE_COUNTER_H_
+#define _CYCLE_COUNTER_H_
+
+#include "compiler.h"
+
+
+//! Structure holding private information, automatically initialized by the
+//! cpu_set_timeout() function.
+typedef struct
+{
+  //! The cycle count at the begining of the timeout.
+  unsigned long delay_start_cycle;
+
+  //! The cycle count at the end of the timeout.
+  unsigned long delay_end_cycle;
+
+  //! Enable/disable the timout detection
+  unsigned char timer_state;
+  #define CPU_TIMER_STATE_STARTED 0
+  #define CPU_TIMER_STATE_REACHED 1
+  #define CPU_TIMER_STATE_STOPPED 2
+} t_cpu_time;
+
+
+/*!
+ * \brief Convert milli-seconds into CPU cycles.
+ *
+ * \param  ms:      Number of millisecond.
+ * \param  fcpu_hz: CPU frequency in Hz.
+ *
+ * \return the converted number of CPU cycles.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ U32 cpu_ms_2_cy(unsigned long ms, unsigned long fcpu_hz)
+{
+  return ((unsigned long long)ms * fcpu_hz + 999) / 1000;
+}
+
+
+/*!
+ * \brief Convert micro-seconds into CPU cycles.
+ *
+ * \param  us:      Number of microsecond.
+ * \param  fcpu_hz: CPU frequency in Hz.
+ *
+ * \return the converted number of CPU cycles.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ U32 cpu_us_2_cy(unsigned long us, unsigned long fcpu_hz)
+{
+  return ((unsigned long long)us * fcpu_hz + 999999) / 1000000;
+}
+
+
+/*!
+ * \brief Convert CPU cycles into milli-seconds.
+ *
+ * \param  cy:      Number of CPU cycles.
+ * \param  fcpu_hz: CPU frequency in Hz.
+ *
+ * \return the converted number of milli-second.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ U32 cpu_cy_2_ms(unsigned long cy, unsigned long fcpu_hz)
+{
+  return ((unsigned long long)cy * 1000 + fcpu_hz-1) / fcpu_hz;
+}
+
+
+/*!
+ * \brief Convert CPU cycles into micro-seconds.
+ *
+ * \param  cy:      Number of CPU cycles.
+ * \param  fcpu_hz: CPU frequency in Hz.
+ *
+ * \return the converted number of micro-second.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ U32 cpu_cy_2_us(unsigned long cy, unsigned long fcpu_hz)
+{
+  return ((unsigned long long)cy * 1000000 + fcpu_hz-1) / fcpu_hz;
+}
+
+
+/*!
+ * \brief Set a timer variable.
+ *
+ * Ex:  t_cpu_time timer;
+ *      cpu_set_timeout( cpu_ms_2_cy(10, FOSC0), &timer ); // timeout in 10 ms
+ *      if( cpu_is_timeout(&timer) )
+ *         cpu_stop_timeout(&timer);
+ *         ../..
+ *
+ * \param  delay:   (input) delay in CPU cycles before timeout.
+ * \param  cpu_time: (output) internal information used by the timer API.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void cpu_set_timeout(unsigned long delay, t_cpu_time *cpu_time)
+{
+  cpu_time->delay_start_cycle = Get_system_register(AVR32_COUNT);
+  cpu_time->delay_end_cycle   = cpu_time->delay_start_cycle + delay;
+  cpu_time->timer_state       = CPU_TIMER_STATE_STARTED;
+}
+
+
+/*!
+ * \brief Test if a timer variable reached its timeout.
+ *
+ * Once the timeout is reached, the function will always return TRUE,
+ * until the cpu_stop_timeout() function is called.
+ *
+ * Ex:  t_cpu_time timer;
+ *      cpu_set_timeout( 10, FOSC0, &timer ); // timeout in 10 ms
+ *      if( cpu_is_timeout(&timer) )
+ *         cpu_stop_timeout(&timer);
+ *         ../..
+ *
+ * \param  cpu_time:   (input) internal information used by the timer API.
+ *
+ * \return TRUE if timeout occured, otherwise FALSE.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ unsigned long cpu_is_timeout(t_cpu_time *cpu_time)
+{
+  unsigned long current_cycle_count = Get_system_register(AVR32_COUNT);
+
+  if( cpu_time->timer_state==CPU_TIMER_STATE_STOPPED )
+    return FALSE;
+
+  // Test if the timeout as already occured.
+  else if (cpu_time->timer_state == CPU_TIMER_STATE_REACHED)
+    return TRUE;
+
+  // If the ending cycle count of this timeout is wrapped, ...
+  else if (cpu_time->delay_start_cycle > cpu_time->delay_end_cycle)
+  {
+    if (current_cycle_count < cpu_time->delay_start_cycle && current_cycle_count > cpu_time->delay_end_cycle)
+    {
+      cpu_time->timer_state = CPU_TIMER_STATE_REACHED;
+      return TRUE;
+    }
+    return FALSE;
+  }
+  else
+  {
+    if (current_cycle_count < cpu_time->delay_start_cycle || current_cycle_count > cpu_time->delay_end_cycle)
+    {
+      cpu_time->timer_state = CPU_TIMER_STATE_REACHED;
+      return TRUE;
+    }
+    return FALSE;
+  }
+}
+
+
+/*!
+ * \brief Stop a timeout detection.
+ *
+ * Ex:  t_cpu_time timer;
+ *      cpu_set_timeout( 10, FOSC0, &timer ); // timeout in 10 ms
+ *      if( cpu_is_timeout(&timer) )
+ *         cpu_stop_timeout(&timer);
+ *         ../..
+ *
+ * \param  cpu_time:   (input) internal information used by the timer API.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void cpu_stop_timeout(t_cpu_time *cpu_time)
+{
+  cpu_time->timer_state = CPU_TIMER_STATE_STOPPED;
+}
+
+
+/*!
+ * \brief Test if a timer is stopped.
+ *
+ * \param  cpu_time:   (input) internal information used by the timer API.
+ *
+ * \return TRUE if timer is stopped, otherwise FALSE.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ unsigned long cpu_is_timer_stopped(t_cpu_time *cpu_time)
+{
+
+  if( cpu_time->timer_state==CPU_TIMER_STATE_STOPPED )
+    return TRUE;
+  else
+    return FALSE;
+}
+
+
+/*!
+ * \brief Waits during at least the specified delay (in millisecond) before returning.
+ *
+ * \param  delay:   Number of millisecond to wait.
+ * \param  fcpu_hz: CPU frequency in Hz.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void cpu_delay_ms(unsigned long delay, unsigned long fcpu_hz)
+{
+  t_cpu_time timer;
+  cpu_set_timeout( cpu_ms_2_cy(delay, fcpu_hz), &timer);
+  while( !cpu_is_timeout(&timer) );
+}
+
+/*!
+ * \brief Waits during at least the specified delay (in microsecond) before returning.
+ *
+ * \param  delay:   Number of microsecond to wait.
+ * \param  fcpu_hz: CPU frequency in Hz.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void cpu_delay_us(unsigned long delay, unsigned long fcpu_hz)
+{
+  t_cpu_time timer;
+  cpu_set_timeout( cpu_us_2_cy(delay, fcpu_hz), &timer);
+  while( !cpu_is_timeout(&timer) );
+}
+
+/*!
+ * \brief Waits during at least the specified delay (in CPU cycles) before returning.
+ *
+ * \param  delay:   Number of CPU cycles to wait.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void cpu_delay_cy(unsigned long delay)
+{
+  t_cpu_time timer;
+  cpu_set_timeout( delay, &timer);
+  while( !cpu_is_timeout(&timer) );
+}
+
+
+#define Get_sys_count()     ( Get_system_register(AVR32_COUNT)        )
+#define Set_sys_count(x)    ( Set_system_register(AVR32_COUNT,   (x)) )
+#define Get_sys_compare()   ( Get_system_register(AVR32_COMPARE)      )
+#define Set_sys_compare(x)  ( Set_system_register(AVR32_COMPARE, (x)) )
+
+
+#endif // _CYCLE_COUNTER_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC/smc.c

@@ -0,0 +1,995 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief SMC on EBI driver for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a SMC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include "compiler.h"
+#include "preprocessor.h"
+#include "gpio.h"
+#include "smc.h"
+
+// Configure the SM Controller with SM setup and timing information for all chip select
+#define SMC_CS_SETUP(ncs) { \
+  U32 nwe_setup    = ((NWE_SETUP    * hsb_mhz_up + 999) / 1000); \
+  U32 ncs_wr_setup = ((NCS_WR_SETUP * hsb_mhz_up + 999) / 1000); \
+  U32 nrd_setup    = ((NRD_SETUP    * hsb_mhz_up + 999) / 1000); \
+  U32 ncs_rd_setup = ((NCS_RD_SETUP * hsb_mhz_up + 999) / 1000); \
+  U32 nwe_pulse    = ((NWE_PULSE    * hsb_mhz_up + 999) / 1000); \
+  U32 ncs_wr_pulse = ((NCS_WR_PULSE * hsb_mhz_up + 999) / 1000); \
+  U32 nrd_pulse    = ((NRD_PULSE    * hsb_mhz_up + 999) / 1000); \
+  U32 ncs_rd_pulse = ((NCS_RD_PULSE * hsb_mhz_up + 999) / 1000); \
+  U32 nwe_cycle    = ((NWE_CYCLE    * hsb_mhz_up + 999) / 1000); \
+  U32 nrd_cycle    = ((NRD_CYCLE    * hsb_mhz_up + 999) / 1000); \
+                                                                 \
+  /* Some coherence checks...                             */     \
+  /* Ensures CS is active during Rd or Wr                 */     \
+  if( ncs_rd_setup + ncs_rd_pulse < nrd_setup + nrd_pulse )      \
+    ncs_rd_pulse = nrd_setup + nrd_pulse - ncs_rd_setup;         \
+  if( ncs_wr_setup + ncs_wr_pulse < nwe_setup + nwe_pulse )      \
+    ncs_wr_pulse = nwe_setup + nwe_pulse - ncs_wr_setup;         \
+                                                                 \
+  /* ncs_hold = n_cycle - ncs_setup - ncs_pulse           */     \
+  /* n_hold   = n_cycle - n_setup - n_pulse               */     \
+  /*                                                      */     \
+  /* All holds parameters must be positive or null, so:   */     \
+  /* nwe_cycle shall be >= ncs_wr_setup + ncs_wr_pulse    */     \
+  if( nwe_cycle < ncs_wr_setup + ncs_wr_pulse )                  \
+    nwe_cycle = ncs_wr_setup + ncs_wr_pulse;                     \
+                                                                 \
+  /* nwe_cycle shall be >= nwe_setup + nwe_pulse          */     \
+  if( nwe_cycle < nwe_setup + nwe_pulse )                        \
+    nwe_cycle = nwe_setup + nwe_pulse;                           \
+                                                                 \
+  /* nrd_cycle shall be >= ncs_rd_setup + ncs_rd_pulse    */     \
+  if( nrd_cycle < ncs_rd_setup + ncs_rd_pulse )                  \
+    nrd_cycle = ncs_rd_setup + ncs_rd_pulse;                     \
+                                                                 \
+  /* nrd_cycle shall be >= nrd_setup + nrd_pulse          */     \
+  if( nrd_cycle < nrd_setup + nrd_pulse )                        \
+    nrd_cycle = nrd_setup + nrd_pulse;                           \
+                                                                 \
+  AVR32_SMC.cs[ncs].setup = (nwe_setup    << AVR32_SMC_SETUP0_NWE_SETUP_OFFSET) | \
+                            (ncs_wr_setup << AVR32_SMC_SETUP0_NCS_WR_SETUP_OFFSET) | \
+                            (nrd_setup    << AVR32_SMC_SETUP0_NRD_SETUP_OFFSET) | \
+                            (ncs_rd_setup << AVR32_SMC_SETUP0_NCS_RD_SETUP_OFFSET); \
+  AVR32_SMC.cs[ncs].pulse = (nwe_pulse    << AVR32_SMC_PULSE0_NWE_PULSE_OFFSET) | \
+                            (ncs_wr_pulse << AVR32_SMC_PULSE0_NCS_WR_PULSE_OFFSET) | \
+                            (nrd_pulse    << AVR32_SMC_PULSE0_NRD_PULSE_OFFSET) | \
+                            (ncs_rd_pulse << AVR32_SMC_PULSE0_NCS_RD_PULSE_OFFSET); \
+  AVR32_SMC.cs[ncs].cycle = (nwe_cycle    << AVR32_SMC_CYCLE0_NWE_CYCLE_OFFSET) | \
+                            (nrd_cycle    << AVR32_SMC_CYCLE0_NRD_CYCLE_OFFSET); \
+  AVR32_SMC.cs[ncs].mode = (((NCS_CONTROLLED_READ) ? AVR32_SMC_MODE0_READ_MODE_NCS_CONTROLLED : \
+                           AVR32_SMC_MODE0_READ_MODE_NRD_CONTROLLED) << AVR32_SMC_MODE0_READ_MODE_OFFSET) | \
+                       +    (((NCS_CONTROLLED_WRITE) ? AVR32_SMC_MODE0_WRITE_MODE_NCS_CONTROLLED : \
+                           AVR32_SMC_MODE0_WRITE_MODE_NWE_CONTROLLED) << AVR32_SMC_MODE0_WRITE_MODE_OFFSET) | \
+                           (NWAIT_MODE << AVR32_SMC_MODE0_EXNW_MODE_OFFSET) | \
+                           (((SMC_8_BIT_CHIPS) ? AVR32_SMC_MODE0_BAT_BYTE_WRITE : \
+                           AVR32_SMC_MODE0_BAT_BYTE_SELECT) << AVR32_SMC_MODE0_BAT_OFFSET) | \
+                           (((SMC_DBW <= 8 ) ? AVR32_SMC_MODE0_DBW_8_BITS  : \
+                           (SMC_DBW <= 16) ? AVR32_SMC_MODE0_DBW_16_BITS : \
+                           AVR32_SMC_MODE0_DBW_32_BITS) << AVR32_SMC_MODE0_DBW_OFFSET) | \
+                           (TDF_CYCLES << AVR32_SMC_MODE0_TDF_CYCLES_OFFSET) | \
+                           (TDF_OPTIM << AVR32_SMC_MODE0_TDF_MODE_OFFSET) | \
+                           (PAGE_MODE << AVR32_SMC_MODE0_PMEN_OFFSET) | \
+                           (PAGE_SIZE << AVR32_SMC_MODE0_PS_OFFSET); \
+  smc_tab_cs_size[ncs] = (U8)EXT_SM_SIZE; \
+  }
+
+static U8 smc_tab_cs_size[6];
+
+static void smc_enable_muxed_pins(void);
+
+
+void smc_init(unsigned long hsb_hz)
+{
+  unsigned long hsb_mhz_up = (hsb_hz + 999999) / 1000000;
+
+//! Whether to use the NCS0 pin
+#ifdef SMC_USE_NCS0
+  #include SMC_COMPONENT_CS0
+
+  // Setup SMC for NCS0
+  SMC_CS_SETUP(0)
+
+  #ifdef SMC_DBW_GLOBAL
+    #if (SMC_DBW_GLOBAL < SMC_DBW)
+        #undef  SMC_DBW_GLOBAL
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+    #endif
+  #else
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+  #endif
+
+  #ifdef SMC_8_BIT_CHIPS_GLOBAL
+    #if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
+        #undef  SMC_8_BIT_CHIPS_GLOBAL
+        #if     (SMC_8_BIT_CHIPS == TRUE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+        #elif   (SMC_8_BIT_CHIPS == FALSE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+        #else
+          #error  error in SMC_8_BIT_CHIPS size
+        #endif
+    #endif
+  #else
+      #if     (SMC_8_BIT_CHIPS == TRUE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+      #elif   (SMC_8_BIT_CHIPS == FALSE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+      #else
+        #error  error in SMC_8_BIT_CHIPS size
+      #endif
+  #endif
+
+  #ifdef NWAIT_MODE_GLOBAL
+    #if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
+        #undef  NWAIT_MODE_GLOBAL
+        #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+        #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+        #else
+          #error  error in NWAIT_MODE size
+        #endif
+    #endif
+  #else
+      #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+      #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+      #else
+        #error  error in NWAIT_MODE size
+      #endif
+  #endif
+
+  #undef EXT_SM_SIZE
+  #undef SMC_DBW
+  #undef SMC_8_BIT_CHIPS
+  #undef NWE_SETUP
+  #undef NCS_WR_SETUP
+  #undef NRD_SETUP
+  #undef NCS_RD_SETUP
+  #undef NCS_WR_PULSE
+  #undef NWE_PULSE
+  #undef NCS_RD_PULSE
+  #undef NRD_PULSE
+  #undef NCS_WR_HOLD
+  #undef NWE_HOLD
+  #undef NWE_CYCLE
+  #undef NCS_RD_HOLD
+  #undef NRD_CYCLE
+  #undef TDF_CYCLES
+  #undef TDF_OPTIM
+  #undef PAGE_MODE
+  #undef PAGE_SIZE
+  #undef NCS_CONTROLLED_READ
+  #undef NCS_CONTROLLED_WRITE
+  #undef NWAIT_MODE
+#endif
+
+
+//! Whether to use the NCS1 pin
+#ifdef SMC_USE_NCS1
+  #include SMC_COMPONENT_CS1
+
+  // Enable SM mode for CS1 if necessary.
+  AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR] &= ~(1 << AVR32_EBI_SDRAM_CS);
+  AVR32_HMATRIX.sfr[AVR32_EBI_HMATRIX_NR];
+
+  // Setup SMC for NCS1
+  SMC_CS_SETUP(1)
+
+  #ifdef SMC_DBW_GLOBAL
+    #if (SMC_DBW_GLOBAL < SMC_DBW)
+        #undef  SMC_DBW_GLOBAL
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+    #endif
+  #else
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+  #endif
+
+  #ifdef SMC_8_BIT_CHIPS_GLOBAL
+    #if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
+        #undef  SMC_8_BIT_CHIPS_GLOBAL
+        #if     (SMC_8_BIT_CHIPS == TRUE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+        #elif   (SMC_8_BIT_CHIPS == FALSE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+        #else
+          #error  error in SMC_8_BIT_CHIPS size
+        #endif
+    #endif
+  #else
+      #if     (SMC_8_BIT_CHIPS == TRUE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+      #elif   (SMC_8_BIT_CHIPS == FALSE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+      #else
+        #error  error in SMC_8_BIT_CHIPS size
+      #endif
+  #endif
+
+  #ifdef NWAIT_MODE_GLOBAL
+    #if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
+        #undef  NWAIT_MODE_GLOBAL
+        #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+        #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+        #else
+          #error  error in NWAIT_MODE size
+        #endif
+    #endif
+  #else
+      #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+      #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+      #else
+        #error  error in NWAIT_MODE size
+      #endif
+  #endif
+
+  #undef EXT_SM_SIZE
+  #undef SMC_DBW
+  #undef SMC_8_BIT_CHIPS
+  #undef NWE_SETUP
+  #undef NCS_WR_SETUP
+  #undef NRD_SETUP
+  #undef NCS_RD_SETUP
+  #undef NCS_WR_PULSE
+  #undef NWE_PULSE
+  #undef NCS_RD_PULSE
+  #undef NRD_PULSE
+  #undef NCS_WR_HOLD
+  #undef NWE_HOLD
+  #undef NWE_CYCLE
+  #undef NCS_RD_HOLD
+  #undef NRD_CYCLE
+  #undef TDF_CYCLES
+  #undef TDF_OPTIM
+  #undef PAGE_MODE
+  #undef PAGE_SIZE
+  #undef NCS_CONTROLLED_READ
+  #undef NCS_CONTROLLED_WRITE
+  #undef NWAIT_MODE
+#endif
+
+//! Whether to use the NCS2 pin
+#ifdef SMC_USE_NCS2
+  #include SMC_COMPONENT_CS2
+
+  // Setup SMC for NCS2
+  SMC_CS_SETUP(2)
+
+  #ifdef SMC_DBW_GLOBAL
+    #if (SMC_DBW_GLOBAL < SMC_DBW)
+        #undef  SMC_DBW_GLOBAL
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+    #endif
+  #else
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+  #endif
+
+  #ifdef SMC_8_BIT_CHIPS_GLOBAL
+    #if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
+        #undef  SMC_8_BIT_CHIPS_GLOBAL
+        #if     (SMC_8_BIT_CHIPS == TRUE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+        #elif   (SMC_8_BIT_CHIPS == FALSE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+        #else
+          #error  error in SMC_8_BIT_CHIPS size
+        #endif
+    #endif
+  #else
+      #if     (SMC_8_BIT_CHIPS == TRUE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+      #elif   (SMC_8_BIT_CHIPS == FALSE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+      #else
+        #error  error in SMC_8_BIT_CHIPS size
+      #endif
+  #endif
+
+  #ifdef NWAIT_MODE_GLOBAL
+    #if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
+        #undef  NWAIT_MODE_GLOBAL
+        #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+        #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+        #else
+          #error  error in NWAIT_MODE size
+        #endif
+    #endif
+  #else
+      #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+      #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+      #else
+        #error  error in NWAIT_MODE size
+      #endif
+  #endif
+
+
+  #undef EXT_SM_SIZE
+  #undef SMC_DBW
+  #undef SMC_8_BIT_CHIPS
+  #undef NWE_SETUP
+  #undef NCS_WR_SETUP
+  #undef NRD_SETUP
+  #undef NCS_RD_SETUP
+  #undef NCS_WR_PULSE
+  #undef NWE_PULSE
+  #undef NCS_RD_PULSE
+  #undef NRD_PULSE
+  #undef NCS_WR_HOLD
+  #undef NWE_HOLD
+  #undef NWE_CYCLE
+  #undef NCS_RD_HOLD
+  #undef NRD_CYCLE
+  #undef TDF_CYCLES
+  #undef TDF_OPTIM
+  #undef PAGE_MODE
+  #undef PAGE_SIZE
+  #undef NCS_CONTROLLED_READ
+  #undef NCS_CONTROLLED_WRITE
+  #undef NWAIT_MODE
+#endif
+
+//! Whether to use the NCS3 pin
+#ifdef SMC_USE_NCS3
+  #include SMC_COMPONENT_CS3
+
+  // Setup SMC for NCS3
+  SMC_CS_SETUP(3)
+
+  #ifdef SMC_DBW_GLOBAL
+    #if (SMC_DBW_GLOBAL < SMC_DBW)
+        #undef  SMC_DBW_GLOBAL
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+    #endif
+  #else
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+  #endif
+
+  #ifdef SMC_8_BIT_CHIPS_GLOBAL
+    #if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
+        #undef  SMC_8_BIT_CHIPS_GLOBAL
+        #if     (SMC_8_BIT_CHIPS == TRUE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+        #elif   (SMC_8_BIT_CHIPS == FALSE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+        #else
+          #error  error in SMC_8_BIT_CHIPS size
+        #endif
+    #endif
+  #else
+      #if     (SMC_8_BIT_CHIPS == TRUE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+      #elif   (SMC_8_BIT_CHIPS == FALSE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+      #else
+        #error  error in SMC_8_BIT_CHIPS size
+      #endif
+  #endif
+
+  #ifdef NWAIT_MODE_GLOBAL
+    #if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
+        #undef  NWAIT_MODE_GLOBAL
+        #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+        #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+        #else
+          #error  error in NWAIT_MODE size
+        #endif
+    #endif
+  #else
+      #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+      #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+      #else
+        #error  error in NWAIT_MODE size
+      #endif
+  #endif
+
+
+  #undef EXT_SM_SIZE
+  #undef SMC_DBW
+  #undef SMC_8_BIT_CHIPS
+  #undef NWE_SETUP
+  #undef NCS_WR_SETUP
+  #undef NRD_SETUP
+  #undef NCS_RD_SETUP
+  #undef NCS_WR_PULSE
+  #undef NWE_PULSE
+  #undef NCS_RD_PULSE
+  #undef NRD_PULSE
+  #undef NCS_WR_HOLD
+  #undef NWE_HOLD
+  #undef NWE_CYCLE
+  #undef NCS_RD_HOLD
+  #undef NRD_CYCLE
+  #undef TDF_CYCLES
+  #undef TDF_OPTIM
+  #undef PAGE_MODE
+  #undef PAGE_SIZE
+  #undef NCS_CONTROLLED_READ
+  #undef NCS_CONTROLLED_WRITE
+  #undef NWAIT_MODE
+#endif
+
+//! Whether to use the NCS4 pin
+#ifdef SMC_USE_NCS4
+  #include SMC_COMPONENT_CS4
+
+  // Setup SMC for NCS4
+  SMC_CS_SETUP(4)
+
+  #ifdef SMC_DBW_GLOBAL
+    #if (SMC_DBW_GLOBAL < SMC_DBW)
+        #undef  SMC_DBW_GLOBAL
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+    #endif
+  #else
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+  #endif
+
+  #ifdef SMC_8_BIT_CHIPS_GLOBAL
+    #if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
+        #undef  SMC_8_BIT_CHIPS_GLOBAL
+        #if     (SMC_8_BIT_CHIPS == TRUE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+        #elif   (SMC_8_BIT_CHIPS == FALSE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+        #else
+          #error  error in SMC_8_BIT_CHIPS size
+        #endif
+    #endif
+  #else
+      #if     (SMC_8_BIT_CHIPS == TRUE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+      #elif   (SMC_8_BIT_CHIPS == FALSE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+      #else
+        #error  error in SMC_8_BIT_CHIPS size
+      #endif
+  #endif
+
+  #ifdef NWAIT_MODE_GLOBAL
+    #if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
+        #undef  NWAIT_MODE_GLOBAL
+        #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+        #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+        #else
+          #error  error in NWAIT_MODE size
+        #endif
+    #endif
+  #else
+      #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+      #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+      #else
+        #error  error in NWAIT_MODE size
+      #endif
+  #endif
+
+
+  #undef EXT_SM_SIZE
+  #undef SMC_DBW
+  #undef SMC_8_BIT_CHIPS
+  #undef NWE_SETUP
+  #undef NCS_WR_SETUP
+  #undef NRD_SETUP
+  #undef NCS_RD_SETUP
+  #undef NCS_WR_PULSE
+  #undef NWE_PULSE
+  #undef NCS_RD_PULSE
+  #undef NRD_PULSE
+  #undef NCS_WR_HOLD
+  #undef NWE_HOLD
+  #undef NWE_CYCLE
+  #undef NCS_RD_HOLD
+  #undef NRD_CYCLE
+  #undef TDF_CYCLES
+  #undef TDF_OPTIM
+  #undef PAGE_MODE
+  #undef PAGE_SIZE
+  #undef NCS_CONTROLLED_READ
+  #undef NCS_CONTROLLED_WRITE
+  #undef NWAIT_MODE
+#endif
+
+//! Whether to use the NCS5 pin
+#ifdef SMC_USE_NCS5
+  #include SMC_COMPONENT_CS5
+
+  // Setup SMC for NCS5
+  SMC_CS_SETUP(5)
+
+  #ifdef SMC_DBW_GLOBAL
+    #if (SMC_DBW_GLOBAL < SMC_DBW)
+        #undef  SMC_DBW_GLOBAL
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+    #endif
+  #else
+        #if     (SMC_DBW == 8)
+            #define SMC_DBW_GLOBAL                  8
+        #elif   (SMC_DBW == 16)
+            #define SMC_DBW_GLOBAL                  16
+        #elif   (SMC_DBW == 32)
+            #define SMC_DBW_GLOBAL                  32
+        #else
+          #error  error in SMC_DBW size
+        #endif
+  #endif
+
+  #ifdef SMC_8_BIT_CHIPS_GLOBAL
+    #if (SMC_8_BIT_CHIPS_GLOBAL < SMC_8_BIT)
+        #undef  SMC_8_BIT_CHIPS_GLOBAL
+        #if     (SMC_8_BIT_CHIPS == TRUE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+        #elif   (SMC_8_BIT_CHIPS == FALSE)
+          #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+        #else
+          #error  error in SMC_8_BIT_CHIPS size
+        #endif
+    #endif
+  #else
+      #if     (SMC_8_BIT_CHIPS == TRUE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            TRUE
+      #elif   (SMC_8_BIT_CHIPS == FALSE)
+        #define SMC_8_BIT_CHIPS_GLOBAL            FALSE
+      #else
+        #error  error in SMC_8_BIT_CHIPS size
+      #endif
+  #endif
+
+  #ifdef NWAIT_MODE_GLOBAL
+    #if (NWAIT_MODE_GLOBAL < NWAIT_MODE)
+        #undef  NWAIT_MODE_GLOBAL
+        #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+        #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+          #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+        #else
+          #error  error in NWAIT_MODE size
+        #endif
+    #endif
+  #else
+      #if     (NWAIT_MODE == AVR32_SMC_EXNW_MODE_DISABLED)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_DISABLED
+      #elif   (NWAIT_MODE == AVR32_SMC_EXNW_MODE_FROZEN)
+        #define NWAIT_MODE_GLOBAL            AVR32_SMC_EXNW_MODE_FROZEN
+      #else
+        #error  error in NWAIT_MODE size
+      #endif
+  #endif
+
+
+  #undef EXT_SM_SIZE
+  #undef SMC_DBW
+  #undef SMC_8_BIT_CHIPS
+  #undef NWE_SETUP
+  #undef NCS_WR_SETUP
+  #undef NRD_SETUP
+  #undef NCS_RD_SETUP
+  #undef NCS_WR_PULSE
+  #undef NWE_PULSE
+  #undef NCS_RD_PULSE
+  #undef NRD_PULSE
+  #undef NCS_WR_HOLD
+  #undef NWE_HOLD
+  #undef NWE_CYCLE
+  #undef NCS_RD_HOLD
+  #undef NRD_CYCLE
+  #undef TDF_CYCLES
+  #undef TDF_OPTIM
+  #undef PAGE_MODE
+  #undef PAGE_SIZE
+  #undef NCS_CONTROLLED_READ
+  #undef NCS_CONTROLLED_WRITE
+  #undef NWAIT_MODE
+#endif
+  // Put the multiplexed MCU pins used for the SM under control of the SMC.
+  smc_enable_muxed_pins();
+}
+
+/*! \brief Puts the multiplexed MCU pins used for the SMC
+ *
+ */
+static void smc_enable_muxed_pins(void)
+{
+  static const gpio_map_t SMC_EBI_GPIO_MAP =
+  {
+    // Enable data pins.
+#ifdef EBI_DATA_0
+    {ATPASTE2(EBI_DATA_0,_PIN),ATPASTE2(EBI_DATA_0,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_1
+    {ATPASTE2(EBI_DATA_1,_PIN),ATPASTE2(EBI_DATA_1,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_2
+    {ATPASTE2(EBI_DATA_2,_PIN),ATPASTE2(EBI_DATA_2,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_3
+    {ATPASTE2(EBI_DATA_3,_PIN),ATPASTE2(EBI_DATA_3,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_4
+    {ATPASTE2(EBI_DATA_4,_PIN),ATPASTE2(EBI_DATA_4,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_5
+    {ATPASTE2(EBI_DATA_5,_PIN),ATPASTE2(EBI_DATA_5,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_6
+    {ATPASTE2(EBI_DATA_6,_PIN),ATPASTE2(EBI_DATA_6,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_7
+    {ATPASTE2(EBI_DATA_7,_PIN),ATPASTE2(EBI_DATA_7,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_8
+    {ATPASTE2(EBI_DATA_8,_PIN),ATPASTE2(EBI_DATA_8,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_9
+    {ATPASTE2(EBI_DATA_9,_PIN),ATPASTE2(EBI_DATA_9,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_10
+    {ATPASTE2(EBI_DATA_10,_PIN),ATPASTE2(EBI_DATA_10,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_11
+    {ATPASTE2(EBI_DATA_11,_PIN),ATPASTE2(EBI_DATA_11,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_12
+    {ATPASTE2(EBI_DATA_12,_PIN),ATPASTE2(EBI_DATA_12,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_13
+    {ATPASTE2(EBI_DATA_13,_PIN),ATPASTE2(EBI_DATA_13,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_14
+    {ATPASTE2(EBI_DATA_14,_PIN),ATPASTE2(EBI_DATA_14,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_15
+    {ATPASTE2(EBI_DATA_15,_PIN),ATPASTE2(EBI_DATA_15,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_16
+    {ATPASTE2(EBI_DATA_16,_PIN),ATPASTE2(EBI_DATA_16,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_17
+    {ATPASTE2(EBI_DATA_17,_PIN),ATPASTE2(EBI_DATA_17,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_18
+    {ATPASTE2(EBI_DATA_18,_PIN),ATPASTE2(EBI_DATA_18,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_19
+    {ATPASTE2(EBI_DATA_19,_PIN),ATPASTE2(EBI_DATA_19,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_20
+    {ATPASTE2(EBI_DATA_20,_PIN),ATPASTE2(EBI_DATA_20,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_21
+    {ATPASTE2(EBI_DATA_21,_PIN),ATPASTE2(EBI_DATA_21,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_22
+    {ATPASTE2(EBI_DATA_22,_PIN),ATPASTE2(EBI_DATA_22,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_23
+    {ATPASTE2(EBI_DATA_23,_PIN),ATPASTE2(EBI_DATA_23,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_24
+    {ATPASTE2(EBI_DATA_24,_PIN),ATPASTE2(EBI_DATA_24,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_25
+    {ATPASTE2(EBI_DATA_25,_PIN),ATPASTE2(EBI_DATA_25,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_26
+    {ATPASTE2(EBI_DATA_26,_PIN),ATPASTE2(EBI_DATA_26,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_27
+    {ATPASTE2(EBI_DATA_27,_PIN),ATPASTE2(EBI_DATA_27,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_28
+    {ATPASTE2(EBI_DATA_28,_PIN),ATPASTE2(EBI_DATA_28,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_29
+    {ATPASTE2(EBI_DATA_29,_PIN),ATPASTE2(EBI_DATA_29,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_30
+    {ATPASTE2(EBI_DATA_30,_PIN),ATPASTE2(EBI_DATA_30,_FUNCTION)},
+#endif
+#ifdef EBI_DATA_31
+    {ATPASTE2(EBI_DATA_31,_PIN),ATPASTE2(EBI_DATA_31,_FUNCTION)},
+#endif
+
+    // Enable address pins.
+#if SMC_DBW_GLOBAL <= 8
+#ifdef EBI_ADDR_0
+    {ATPASTE2(EBI_ADDR_0,_PIN),ATPASTE2(EBI_ADDR_0,_FUNCTION)},
+#endif
+#endif
+#if SMC_DBW_GLOBAL <= 16
+#ifdef EBI_ADDR_1
+    {ATPASTE2(EBI_ADDR_1,_PIN),ATPASTE2(EBI_ADDR_1,_FUNCTION)},
+#endif
+#endif
+
+#ifdef EBI_ADDR_2
+    {ATPASTE2(EBI_ADDR_2,_PIN),ATPASTE2(EBI_ADDR_2,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_3
+    {ATPASTE2(EBI_ADDR_3,_PIN),ATPASTE2(EBI_ADDR_3,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_4
+    {ATPASTE2(EBI_ADDR_4,_PIN),ATPASTE2(EBI_ADDR_4,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_5
+    {ATPASTE2(EBI_ADDR_5,_PIN),ATPASTE2(EBI_ADDR_5,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_6
+    {ATPASTE2(EBI_ADDR_6,_PIN),ATPASTE2(EBI_ADDR_6,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_7
+    {ATPASTE2(EBI_ADDR_7,_PIN),ATPASTE2(EBI_ADDR_7,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_8
+    {ATPASTE2(EBI_ADDR_8,_PIN),ATPASTE2(EBI_ADDR_8,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_9
+    {ATPASTE2(EBI_ADDR_9,_PIN),ATPASTE2(EBI_ADDR_9,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_10
+    {ATPASTE2(EBI_ADDR_10,_PIN),ATPASTE2(EBI_ADDR_10,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_11
+    {ATPASTE2(EBI_ADDR_11,_PIN),ATPASTE2(EBI_ADDR_11,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_12
+    {ATPASTE2(EBI_ADDR_12,_PIN),ATPASTE2(EBI_ADDR_12,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_13
+    {ATPASTE2(EBI_ADDR_13,_PIN),ATPASTE2(EBI_ADDR_13,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_14
+    {ATPASTE2(EBI_ADDR_14,_PIN),ATPASTE2(EBI_ADDR_14,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_15
+    {ATPASTE2(EBI_ADDR_15,_PIN),ATPASTE2(EBI_ADDR_15,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_16
+    {ATPASTE2(EBI_ADDR_16,_PIN),ATPASTE2(EBI_ADDR_16,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_17
+    {ATPASTE2(EBI_ADDR_17,_PIN),ATPASTE2(EBI_ADDR_17,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_18
+    {ATPASTE2(EBI_ADDR_18,_PIN),ATPASTE2(EBI_ADDR_18,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_19
+    {ATPASTE2(EBI_ADDR_19,_PIN),ATPASTE2(EBI_ADDR_19,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_20
+    {ATPASTE2(EBI_ADDR_20,_PIN),ATPASTE2(EBI_ADDR_20,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_21
+    {ATPASTE2(EBI_ADDR_21,_PIN),ATPASTE2(EBI_ADDR_21,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_22
+    {ATPASTE2(EBI_ADDR_22,_PIN),ATPASTE2(EBI_ADDR_22,_FUNCTION)},
+#endif
+#ifdef EBI_ADDR_23
+    {ATPASTE2(EBI_ADDR_23,_PIN),ATPASTE2(EBI_ADDR_23,_FUNCTION)},
+#endif
+
+#if SMC_DBW_GLOBAL <= 8
+  #undef SMC_8_BIT_CHIPS
+  #define SMC_8_BIT_CHIPS   TRUE
+#endif
+
+    // Enable data mask pins.
+#if !SMC_8_BIT_CHIPS_GLOBAL
+#ifdef EBI_ADDR_0
+    {ATPASTE2(EBI_ADDR_0,_PIN),ATPASTE2(EBI_ADDR_0,_FUNCTION)},
+#endif
+#endif
+#ifdef EBI_NWE0
+    {ATPASTE2(EBI_NWE0,_PIN),ATPASTE2(EBI_NWE0,_FUNCTION)},
+#endif
+
+#if SMC_DBW_GLOBAL >= 16
+  #ifdef EBI_NWE1
+      {ATPASTE2(EBI_NWE1,_PIN),ATPASTE2(EBI_NWE1,_FUNCTION)},
+  #endif
+  #if SMC_DBW_GLOBAL >= 32
+    #ifdef EBI_ADDR_1
+        {ATPASTE2(EBI_ADDR_1,_PIN),ATPASTE2(EBI_ADDR_1,_FUNCTION)},
+    #endif
+    #ifdef EBI_NWE3
+        {ATPASTE2(EBI_NWE3,_PIN),ATPASTE2(EBI_NWE3,_FUNCTION)},
+    #endif
+  #endif
+#endif
+    #ifdef EBI_NRD
+        {ATPASTE2(EBI_NRD,_PIN),ATPASTE2(EBI_NRD,_FUNCTION)},
+    #endif
+
+    // Enable control pins.
+#if NWAIT_MODE_GLOBAL != AVR32_SMC_EXNW_MODE_DISABLED
+    #ifdef EBI_NWAIT
+        {ATPASTE2(EBI_NWAIT,_PIN),ATPASTE2(EBI_NWAIT,_FUNCTION)},
+    #endif
+#endif
+#ifdef SMC_USE_NCS0
+    #ifdef EBI_NCS_0
+        {ATPASTE2(EBI_NCS_0,_PIN),ATPASTE2(EBI_NCS_0,_FUNCTION)},
+    #endif
+#endif
+#ifdef SMC_USE_NCS1
+    #ifdef EBI_NCS_1
+        {ATPASTE2(EBI_NCS_1,_PIN),ATPASTE2(EBI_NCS_1,_FUNCTION)},
+    #endif
+#endif
+#ifdef SMC_USE_NCS2
+    #ifdef EBI_NCS_2
+        {ATPASTE2(EBI_NCS_2,_PIN),ATPASTE2(EBI_NCS_2,_FUNCTION)},
+    #endif
+#endif
+#ifdef SMC_USE_NCS3
+    #ifdef EBI_NCS_3
+        {ATPASTE2(EBI_NCS_3,_PIN),ATPASTE2(EBI_NCS_3,_FUNCTION)},
+    #endif
+#endif
+#ifdef SMC_USE_NCS4
+    #ifdef EBI_NCS_4
+        {ATPASTE2(EBI_NCS_4,_PIN),ATPASTE2(EBI_NCS_4,_FUNCTION)},
+    #endif
+#endif
+#ifdef SMC_USE_NCS5
+    #ifdef EBI_NCS_5
+        {ATPASTE2(EBI_NCS_5,_PIN),ATPASTE2(EBI_NCS_5,_FUNCTION)},
+    #endif
+#endif
+ };
+
+  gpio_enable_module(SMC_EBI_GPIO_MAP, sizeof(SMC_EBI_GPIO_MAP) / sizeof(SMC_EBI_GPIO_MAP[0]));
+}
+
+unsigned char smc_get_cs_size(unsigned char cs)
+{
+  return smc_tab_cs_size[cs];
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/EBI/SMC/smc.h

@@ -0,0 +1,68 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief SMC on EBI driver for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a SMC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _SMC_H_
+#define _SMC_H_
+
+#include <avr32/io.h>
+
+#include "compiler.h"
+#include "conf_ebi.h"
+
+/*! \brief Initializes the AVR32 SMC module and the connected SRAM(s).
+ * \param hsb_hz HSB frequency in Hz (the HSB frequency is applied to the SMC).
+ * \note Each access to the SMC address space validates the mode of the SMC
+ *       and generates an operation corresponding to this mode.
+ */
+extern void smc_init(unsigned long hsb_hz);
+
+/*! \brief Return the size of the peripheral connected  .
+ *  \param cs The chip select value
+ */
+extern unsigned char smc_get_cs_size(unsigned char cs);
+
+#endif  // _SMC_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/EIC/eic.c

@@ -0,0 +1,183 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief EIC driver for AVR32 UC3.
+ *
+ * AVR32 External Interrupt Controller driver module.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an EIC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+#include "preprocessor.h"
+#include "eic.h"
+
+
+
+void eic_init(volatile avr32_eic_t *eic, const eic_options_t *opt, unsigned int nb_lines)
+{
+  int i;
+  for (i = 0; i < nb_lines; i++)
+  {
+    // Set up mode level
+    eic->mode = (opt[i].eic_mode == 1) ? (eic->mode | (1 << opt[i].eic_line)) : (eic->mode & ~(1 << opt[i].eic_line));
+    // Set up edge type
+    eic->edge = (opt[i].eic_edge == 1) ? (eic->edge | (1 << opt[i].eic_line)) : (eic->edge & ~(1 << opt[i].eic_line));
+    // Set up level
+    eic->level = (opt[i].eic_level == 1) ? (eic->level | (1 << opt[i].eic_line)) : (eic->level & ~(1 << opt[i].eic_line));
+    // Set up if filter is used
+    eic->filter = (opt[i].eic_filter == 1) ? (eic->filter | (1 << opt[i].eic_line)) : (eic->filter & ~(1 << opt[i].eic_line));
+    // Set up which mode is used : asynchronous mode/ synchronous mode
+    eic->async = (opt[i].eic_async == 1) ? (eic->async | (1 << opt[i].eic_line)) : (eic->async & ~(1 << opt[i].eic_line));
+  }
+}
+
+void eic_enable_lines(volatile avr32_eic_t *eic, unsigned int mask_lines)
+{
+  eic->en = mask_lines;
+}
+
+void eic_enable_line(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  // Enable line line_number
+  eic->en = 1 << line_number;
+}
+
+void eic_disable_lines(volatile avr32_eic_t *eic, unsigned int mask_lines)
+{
+  eic->dis = mask_lines;
+}
+
+void eic_disable_line(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  // Disable line line_number
+  eic->dis = 1 << line_number;
+}
+
+Bool eic_is_line_enabled(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  return (eic->ctrl & (1 << line_number)) != 0;
+}
+
+void eic_enable_interrupt_lines(volatile avr32_eic_t *eic, unsigned int mask_lines)
+{
+  eic->ier = mask_lines;
+}
+
+void eic_enable_interrupt_line(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  // Enable line line_number
+  eic->ier = 1 << line_number;
+}
+
+void eic_disable_interrupt_lines(volatile avr32_eic_t *eic, unsigned int mask_lines)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  eic->idr = mask_lines;
+  eic->imr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+void eic_disable_interrupt_line(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  // Disable line line_number
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  eic->idr = 1 << line_number;
+  eic->imr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+Bool eic_is_interrupt_line_enabled(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  return (eic->imr & (1 << line_number)) != 0;
+}
+
+void eic_clear_interrupt_lines(volatile avr32_eic_t *eic, unsigned int mask_lines)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  eic->icr = mask_lines;
+  eic->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+void eic_clear_interrupt_line(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  // Clear line line_number
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  eic->icr = 1 << line_number;
+  eic->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+Bool eic_is_interrupt_line_pending(volatile avr32_eic_t *eic, unsigned int line_number)
+{
+  return (eic->isr & (1 << line_number)) != 0;
+}
+
+#if !defined(AVR32_EIC_301_H_INCLUDED)
+void eic_enable_interrupt_scan(volatile avr32_eic_t *eic,unsigned int presc)
+{
+  // Enable SCAN function with PRESC value
+  eic->scan |= (presc << AVR32_EIC_SCAN_PRESC_OFFSET) | (1 << AVR32_EIC_SCAN_EN_OFFSET);
+}
+
+void eic_disable_interrupt_scan(volatile avr32_eic_t *eic)
+{
+  // Disable SCAN function
+  eic->scan = 0 << AVR32_EIC_SCAN_EN_OFFSET;
+}
+
+unsigned long eic_get_interrupt_pad_scan(volatile avr32_eic_t *eic)
+{
+  // Return pad number that causes interrupt
+  return(eic->scan>>AVR32_EIC_SCAN_PIN_OFFSET);
+}
+#endif

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/EIC/eic.h

@@ -0,0 +1,275 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief EIC driver for AVR32 UC3.
+ *
+ * AVR32 External Interrupt Controller driver module.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an EIC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _EIC_H_
+#define _EIC_H_
+
+#include "compiler.h"
+
+/*! \name External Interrupt lines
+ */
+//! @{
+#if (UC3A || UC3B)  
+#define EXT_INT0    AVR32_EIC_INT0 //!< Line 0
+#define EXT_INT1    AVR32_EIC_INT1 //!< Line 1
+#define EXT_INT2    AVR32_EIC_INT2 //!< Line 2
+#define EXT_INT3    AVR32_EIC_INT3 //!< Line 3
+#define EXT_INT4    AVR32_EIC_INT4 //!< Line 4
+#define EXT_INT5    AVR32_EIC_INT5 //!< Line 5
+#define EXT_INT6    AVR32_EIC_INT6 //!< Line 6
+#define EXT_INT7    AVR32_EIC_INT7 //!< Line 7
+#define EXT_NMI     AVR32_EIC_NMI  //!< Line 8
+#else
+#define EXT_INT0    AVR32_EIC_INT1  //!< Line 0
+#define EXT_INT1    AVR32_EIC_INT2 //!< Line 1
+#define EXT_INT2    AVR32_EIC_INT3 //!< Line 2
+#define EXT_INT3    AVR32_EIC_INT4 //!< Line 3
+#define EXT_INT4    AVR32_EIC_INT5 //!< Line 4
+#define EXT_INT5    AVR32_EIC_INT6 //!< Line 5
+#define EXT_INT6    AVR32_EIC_INT7 //!< Line 6
+#define EXT_INT7    AVR32_EIC_INT8 //!< Line 7
+#define EXT_NMI     AVR32_EIC_NMI  //!< Line 8
+
+#endif
+
+//! @}
+
+/*! \name Mode Trigger Options
+ */
+//! @{
+#define EIC_MODE_EDGE_TRIGGERED   AVR32_EIC_EDGE_IRQ //!<
+#define EIC_MODE_LEVEL_TRIGGERED  AVR32_EIC_LEVEL_IRQ //!<
+//! @}
+
+/*! \name Edge level Options
+ */
+//! @{
+#define EIC_EDGE_FALLING_EDGE     AVR32_EIC_FALLING_EDGE //!<
+#define EIC_EDGE_RISING_EDGE      AVR32_EIC_RISING_EDGE //!<
+//! @}
+
+/*! \name Level Options
+ */
+//! @{
+#define EIC_LEVEL_LOW_LEVEL       AVR32_EIC_LOW_LEVEL //!<
+#define EIC_LEVEL_HIGH_LEVEL      AVR32_EIC_HIGH_LEVEL //!<
+//! @}
+
+/*! \name Filter Options
+ */
+//! @{
+#define EIC_FILTER_ENABLED        AVR32_EIC_FILTER_ON //!<
+#define EIC_FILTER_DISABLED       AVR32_EIC_FILTER_OFF //!<
+//! @}
+
+/*! \name Synch Mode Options
+ */
+//! @{
+#define EIC_SYNCH_MODE            AVR32_EIC_SYNC //!<
+#define EIC_ASYNCH_MODE           AVR32_EIC_USE_ASYNC //!<
+//! @}
+
+//! Configuration parameters of the EIC module.
+typedef struct
+{
+  //!Line
+  unsigned char eic_line;
+
+  //! Mode : EDGE_LEVEL or TRIGGER_LEVEL
+  unsigned char eic_mode;
+
+  //! Edge : FALLING_EDGE or RISING_EDGE
+  unsigned char eic_edge;
+
+  //! Level :  LOW_LEVEL or HIGH_LEVEL
+  unsigned char eic_level;
+
+  //! Filter:  NOT_FILTERED or FILTERED
+  unsigned char eic_filter;
+
+  //! Async:  SYNC mode or ASYNC
+  unsigned char eic_async;
+
+} eic_options_t;
+
+
+/*! \brief Init the EIC driver.
+ *
+ * \param eic Base address of the EIC module
+ * \param opt Configuration parameters of the EIC module (see \ref eic_options_t)
+ * \param nb_lines Number of lines to consider, equal to size of opt buffer
+ */
+extern void eic_init(volatile avr32_eic_t *eic, const eic_options_t *opt, unsigned int nb_lines);
+
+/*! \brief Enable the EIC driver.
+ *
+ * \param eic Base address of the EIC module
+ * \param mask_lines Mask for current selected lines
+ */
+extern void eic_enable_lines(volatile avr32_eic_t *eic, unsigned int mask_lines);
+
+/*! \brief Enable the EIC driver.
+ *
+ * \param eic Base address of the EIC module
+ * \param line_number Line number to enable
+ */
+extern void eic_enable_line(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \brief Disable the EIC driver.
+ *
+ * \param eic Base address of the EIC module
+ * \param mask_lines Mask for current selected lines
+ */
+extern void eic_disable_lines(volatile avr32_eic_t *eic, unsigned int mask_lines);
+
+/*! \brief Disable the EIC driver.
+ *
+ * \param eic Base address of the EIC module
+ * \param line_number Line number to disable
+ */
+extern void eic_disable_line(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \brief Tells whether an EIC line is enabled.
+ *
+ * \param eic Base address of the EIC module
+ * \param line_number Line number to test
+ *
+ * \return Whether an EIC line is enabled.
+ */
+extern Bool eic_is_line_enabled(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \name Interrupt Control Functions
+ */
+//! @{
+
+/*! \brief Enable the interrupt feature of the EIC.
+ *
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ * \param mask_lines Mask for current selected lines
+ */
+extern void eic_enable_interrupt_lines(volatile avr32_eic_t *eic, unsigned int mask_lines);
+
+/*! \brief Enable the interrupt feature of the EIC.
+ *
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ * \param line_number Line number to enable
+ */
+extern void eic_enable_interrupt_line(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \brief Disable the interrupt feature of the EIC.
+ *
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ * \param mask_lines Mask for current selected lines
+ */
+extern void eic_disable_interrupt_lines(volatile avr32_eic_t *eic, unsigned int mask_lines);
+
+/*! \brief Disable the interrupt feature of the EIC.
+ *
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ * \param line_number Line number to disable
+ */
+extern void eic_disable_interrupt_line(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \brief Tells whether an EIC interrupt line is enabled.
+ *
+ * \param eic Base address of the EIC module
+ * \param line_number Line number to test
+ *
+ * \return Whether an EIC interrupt line is enabled.
+ */
+extern Bool eic_is_interrupt_line_enabled(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \brief Clear the interrupt flag.
+ *         Call this function once you've handled the interrupt.
+ * 
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ * \param mask_lines Mask for current selected lines
+ */
+extern void eic_clear_interrupt_lines(volatile avr32_eic_t *eic, unsigned int mask_lines);
+
+/*! \brief Clear the interrupt flag.
+ *         Call this function once you've handled the interrupt.
+ * 
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ * \param line_number Line number to clear
+ */
+extern void eic_clear_interrupt_line(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \brief Tells whether an EIC interrupt line is pending.
+ *
+ * \param eic Base address of the EIC module
+ * \param line_number Line number to test
+ *
+ * \return Whether an EIC interrupt line is pending.
+ */
+extern Bool eic_is_interrupt_line_pending(volatile avr32_eic_t *eic, unsigned int line_number);
+
+/*! \brief Enable the interrupt scan feature of the EIC.
+ *
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ * \param presc Prescale select for the keypad scan rate in the range [0,31].
+ */
+extern void eic_enable_interrupt_scan(volatile avr32_eic_t *eic, unsigned int presc);
+
+/*! \brief Disable the interrupt scan feature of the EIC.
+ *
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ */
+extern void eic_disable_interrupt_scan(volatile avr32_eic_t *eic);
+
+/*! \brief Return scan pad number that causes interrupt.
+ *
+ * \param eic Base address of the EIC (i.e. &AVR32_EIC).
+ */
+extern unsigned long eic_get_interrupt_pad_scan(volatile avr32_eic_t *eic);
+
+//! @}
+
+
+#endif  // _EIC_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.c

@@ -0,0 +1,458 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief GPIO driver for AVR32 UC3.
+ *
+ * This file defines a useful set of functions for the GPIO.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a GPIO module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include "gpio.h"
+
+//! GPIO module instance.
+#define GPIO  AVR32_GPIO
+
+
+/*! \name Peripheral Bus Interface
+ */
+//! @{
+
+
+int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size)
+{
+  int status = GPIO_SUCCESS;
+  unsigned int i;
+
+  for (i = 0; i < size; i++)
+  {
+    status |= gpio_enable_module_pin(gpiomap->pin, gpiomap->function);
+    gpiomap++;
+  }
+
+  return status;
+}
+
+
+int gpio_enable_module_pin(unsigned int pin, unsigned int function)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  // Enable the correct function.
+  switch (function)
+  {
+  case 0: // A function.
+    gpio_port->pmr0c = 1 << (pin & 0x1F);
+    gpio_port->pmr1c = 1 << (pin & 0x1F);
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+    gpio_port->pmr2c = 1 << (pin & 0x1F);
+#endif
+    break;
+
+  case 1: // B function.
+    gpio_port->pmr0s = 1 << (pin & 0x1F);
+    gpio_port->pmr1c = 1 << (pin & 0x1F);
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+    gpio_port->pmr2c = 1 << (pin & 0x1F);
+#endif
+    break;
+
+  case 2: // C function.
+    gpio_port->pmr0c = 1 << (pin & 0x1F);
+    gpio_port->pmr1s = 1 << (pin & 0x1F);
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+    gpio_port->pmr2c = 1 << (pin & 0x1F);
+#endif
+    break;
+
+  case 3: // D function.
+    gpio_port->pmr0s = 1 << (pin & 0x1F);
+    gpio_port->pmr1s = 1 << (pin & 0x1F);
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+    gpio_port->pmr2c = 1 << (pin & 0x1F);
+#endif
+    break;
+
+#if defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+  case 4: // E function.
+    gpio_port->pmr0c = 1 << (pin & 0x1F);
+    gpio_port->pmr1c = 1 << (pin & 0x1F);
+    gpio_port->pmr2s = 1 << (pin & 0x1F);
+    break;
+    
+  case 5: // F function.
+    gpio_port->pmr0s = 1 << (pin & 0x1F);
+    gpio_port->pmr1c = 1 << (pin & 0x1F);
+    gpio_port->pmr2s = 1 << (pin & 0x1F);
+    break;
+    
+  case 6: // G function.
+    gpio_port->pmr0c = 1 << (pin & 0x1F);
+    gpio_port->pmr1s = 1 << (pin & 0x1F);
+    gpio_port->pmr2s = 1 << (pin & 0x1F);
+    break;
+    
+  case 7: // H function.
+    gpio_port->pmr0s = 1 << (pin & 0x1F);
+    gpio_port->pmr1s = 1 << (pin & 0x1F);
+    gpio_port->pmr2s = 1 << (pin & 0x1F);
+    break;
+#endif
+
+  default:
+    return GPIO_INVALID_ARGUMENT;
+  }
+
+  // Disable GPIO control.
+  gpio_port->gperc = 1 << (pin & 0x1F);
+
+  return GPIO_SUCCESS;
+}
+
+
+void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size)
+{
+  unsigned int i;
+
+  for (i = 0; i < size; i++)
+  {
+    gpio_enable_gpio_pin(gpiomap->pin);
+    gpiomap++;
+  }
+}
+
+
+void gpio_enable_gpio_pin(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->oderc = 1 << (pin & 0x1F);
+  gpio_port->gpers = 1 << (pin & 0x1F);
+}
+
+
+// The open-drain mode is not synthesized on the current AVR32 products.
+// If one day some AVR32 products have this feature, the corresponding part
+// numbers should be listed in the #if below.
+// Note that other functions are available in this driver to use pins with open
+// drain in GPIO mode. The advantage of the open-drain mode functions over these
+// other functions is that they can be used not only in GPIO mode but also in
+// module mode.
+#if 0
+
+
+void gpio_enable_pin_open_drain(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->odmers = 1 << (pin & 0x1F);
+}
+
+
+void gpio_disable_pin_open_drain(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->odmerc = 1 << (pin & 0x1F);
+}
+
+
+#endif
+
+
+void gpio_enable_pin_pull_up(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->puers = 1 << (pin & 0x1F);
+#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+  gpio_port->pderc = 1 << (pin & 0x1F);
+#endif
+}
+
+
+void gpio_disable_pin_pull_up(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->puerc = 1 << (pin & 0x1F);
+}
+
+#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.
+
+/*! \brief Enables the pull-down resistor of a pin.
+ *
+ * \param pin The pin number.
+ */
+void gpio_enable_pin_pull_down(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->puerc = 1 << (pin & 0x1F);
+  gpio_port->pders = 1 << (pin & 0x1F);
+}
+
+/*! \brief Disables the pull-down resistor of a pin.
+ *
+ * \param pin The pin number.
+ */
+void gpio_disable_pin_pull_down(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->pderc = 1 << (pin & 0x1F);
+}
+
+/*! \brief Enables the buskeeper functionality on a pin.
+ *
+ * \param pin The pin number.
+ */
+void gpio_enable_pin_buskeeper(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->puers = 1 << (pin & 0x1F);
+  gpio_port->pders = 1 << (pin & 0x1F);
+}
+
+/*! \brief Disables the buskeeper functionality on a pin.
+ *
+ * \param pin The pin number.
+ */
+void gpio_disable_pin_buskeeper(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->puerc = 1 << (pin & 0x1F);
+  gpio_port->pderc = 1 << (pin & 0x1F);
+}
+
+#endif
+
+int gpio_get_pin_value(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  return (gpio_port->pvr >> (pin & 0x1F)) & 1;
+}
+
+
+int gpio_get_gpio_pin_output_value(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  return (gpio_port->ovr >> (pin & 0x1F)) & 1;
+}
+
+
+int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  return ((gpio_port->oder >> (pin & 0x1F)) & 1) ^ 1;
+}
+
+
+void gpio_set_gpio_pin(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  gpio_port->ovrs  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 1.
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
+}
+
+
+void gpio_clr_gpio_pin(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  gpio_port->ovrc  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
+}
+
+
+void gpio_tgl_gpio_pin(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  gpio_port->ovrt  = 1 << (pin & 0x1F); // Toggle the I/O line.
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
+}
+
+
+void gpio_set_gpio_open_drain_pin(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  gpio_port->oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
+}
+
+
+void gpio_clr_gpio_open_drain_pin(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  gpio_port->ovrc  = 1 << (pin & 0x1F); // Value to be driven on the I/O line: 0.
+  gpio_port->oders = 1 << (pin & 0x1F); // The GPIO output driver is enabled for that pin.
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
+}
+
+
+void gpio_tgl_gpio_open_drain_pin(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  gpio_port->ovrc  = 1 << (pin & 0x1F); // Value to be driven on the I/O line if the GPIO output driver is enabled: 0.
+  gpio_port->odert = 1 << (pin & 0x1F); // The GPIO output driver is toggled for that pin.
+  gpio_port->gpers = 1 << (pin & 0x1F); // The GPIO module controls that pin.
+}
+
+
+void gpio_enable_pin_glitch_filter(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->gfers = 1 << (pin & 0x1F);
+}
+
+
+void gpio_disable_pin_glitch_filter(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->gferc = 1 << (pin & 0x1F);
+}
+
+/*! \brief Configure the edge detector of an input pin
+ *
+ * \param pin The pin number.
+ * \param mode The edge detection mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE
+ *             or \ref GPIO_FALLING_EDGE).
+ *
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
+ */
+static int gpio_configure_edge_detector(unsigned int pin, unsigned int mode)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  
+  // Configure the edge detector.
+  switch (mode)
+  {
+  case GPIO_PIN_CHANGE:
+    gpio_port->imr0c = 1 << (pin & 0x1F);
+    gpio_port->imr1c = 1 << (pin & 0x1F);
+    break;
+
+  case GPIO_RISING_EDGE:
+    gpio_port->imr0s = 1 << (pin & 0x1F);
+    gpio_port->imr1c = 1 << (pin & 0x1F);
+    break;
+
+  case GPIO_FALLING_EDGE:
+    gpio_port->imr0c = 1 << (pin & 0x1F);
+    gpio_port->imr1s = 1 << (pin & 0x1F);
+    break;
+
+  default:
+    return GPIO_INVALID_ARGUMENT;
+  }
+
+  return GPIO_SUCCESS;
+}
+
+
+int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode)
+{
+  volatile avr32_gpio_port_t  *gpio_port = &GPIO.port[pin >> 5];
+
+  // Enable the glitch filter.
+  gpio_port->gfers = 1 << (pin & 0x1F);
+
+  // Configure the edge detector.
+  if(GPIO_INVALID_ARGUMENT == gpio_configure_edge_detector(pin, mode))
+    return(GPIO_INVALID_ARGUMENT);
+
+  // Enable interrupt.
+  gpio_port->iers = 1 << (pin & 0x1F);
+
+  return GPIO_SUCCESS;
+}
+
+
+void gpio_disable_pin_interrupt(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->ierc = 1 << (pin & 0x1F);
+}
+
+
+int gpio_get_pin_interrupt_flag(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  return (gpio_port->ifr >> (pin & 0x1F)) & 1;
+}
+
+
+void gpio_clear_pin_interrupt_flag(unsigned int pin)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+  gpio_port->ifrc = 1 << (pin & 0x1F);
+}
+
+
+//#
+//# Peripheral Event System Support.
+//#
+#if UC3L
+int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf)
+{
+  volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin >> 5];
+
+  if(TRUE == use_igf)
+  {
+    // Enable the glitch filter.
+    gpio_port->gfers = 1 << (pin & 0x1F);
+  }
+  else
+  {
+    // Disable the glitch filter.
+    gpio_port->gferc = 1 << (pin & 0x1F);
+  }
+
+  // Configure the edge detector.
+  return(gpio_configure_edge_detector(pin, mode));
+}
+
+#endif
+
+//! @}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/GPIO/gpio.h

@@ -0,0 +1,583 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief GPIO header for AVR32 UC3.
+ *
+ * This file contains basic GPIO driver functions.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a GPIO module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include <avr32/io.h>
+#include "compiler.h"
+
+/*! \name Return Values of the GPIO API
+ */
+//! @{
+#define GPIO_SUCCESS            0 //!< Function successfully completed.
+#define GPIO_INVALID_ARGUMENT   1 //!< Input parameters are out of range.
+//! @}
+
+
+/*! \name Interrupt Trigger Modes
+ */
+//! @{
+#define GPIO_PIN_CHANGE         0 //!< Interrupt triggered upon pin change.
+#define GPIO_RISING_EDGE        1 //!< Interrupt triggered upon rising edge.
+#define GPIO_FALLING_EDGE       2 //!< Interrupt triggered upon falling edge.
+//! @}
+
+
+//! A type definition of pins and modules connectivity.
+typedef struct
+{
+  unsigned char pin;              //!< Module pin.
+  unsigned char function;         //!< Module function.
+} gpio_map_t[];
+
+
+/*! \name Peripheral Bus Interface
+ *
+ * Low-speed interface with a non-deterministic number of clock cycles per
+ * access.
+ *
+ * This interface operates with lower clock frequencies (fPB <= fCPU), and its
+ * timing is not deterministic since it needs to access a shared bus which may
+ * be heavily loaded.
+ *
+ * \note This interface is immediately available without initialization.
+ */
+//! @{
+
+/*! \brief Enables specific module modes for a set of pins.
+ *
+ * \param gpiomap The pin map.
+ * \param size The number of pins in \a gpiomap.
+ *
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
+ */
+extern int gpio_enable_module(const gpio_map_t gpiomap, unsigned int size);
+
+/*! \brief Enables a specific module mode for a pin.
+ *
+ * \param pin The pin number.\n
+ *            Refer to the product header file `uc3x.h' (where x is the part
+ *            number; e.g. x = a0512) for module pins. E.g., to enable a PWM
+ *            channel output, the pin number can be AVR32_PWM_3_PIN for PWM
+ *            channel 3.
+ * \param function The pin function.\n
+ *                 Refer to the product header file `uc3x.h' (where x is the
+ *                 part number; e.g. x = a0512) for module pin functions. E.g.,
+ *                 to enable a PWM channel output, the pin function can be
+ *                 AVR32_PWM_3_FUNCTION for PWM channel 3.
+ *
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
+ */
+extern int gpio_enable_module_pin(unsigned int pin, unsigned int function);
+
+/*! \brief Enables the GPIO mode of a set of pins.
+ *
+ * \param gpiomap The pin map.
+ * \param size The number of pins in \a gpiomap.
+ */
+extern void gpio_enable_gpio(const gpio_map_t gpiomap, unsigned int size);
+
+/*! \brief Enables the GPIO mode of a pin.
+ *
+ * \param pin The pin number.\n
+ *            Refer to the product header file `uc3x.h' (where x is the part
+ *            number; e.g. x = a0512) for pin definitions. E.g., to enable the
+ *            GPIO mode of PX21, AVR32_PIN_PX21 can be used. Module pins such as
+ *            AVR32_PWM_3_PIN for PWM channel 3 can also be used to release
+ *            module pins for GPIO.
+ */
+extern void gpio_enable_gpio_pin(unsigned int pin);
+
+// The open-drain mode is not synthesized on the current AVR32 products.
+// If one day some AVR32 products have this feature, the corresponding part
+// numbers should be listed in the #if below.
+// Note that other functions are available in this driver to use pins with open
+// drain in GPIO mode. The advantage of the open-drain mode functions over these
+// other functions is that they can be used not only in GPIO mode but also in
+// module mode.
+#if 0
+
+/*! \brief Enables the open-drain mode of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_enable_pin_open_drain(unsigned int pin);
+
+/*! \brief Disables the open-drain mode of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_disable_pin_open_drain(unsigned int pin);
+
+#endif
+
+/*! \brief Enables the pull-up resistor of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_enable_pin_pull_up(unsigned int pin);
+
+/*! \brief Disables the pull-up resistor of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_disable_pin_pull_up(unsigned int pin);
+
+#if defined(AVR32_GPIO_200_H_INCLUDED) || defined(AVR32_GPIO_210_H_INCLUDED) || defined(AVR32_GPIO_211_H_INCLUDED)
+// Added support of Pull-up Resistor, Pull-down Resistor and Buskeeper Control.
+
+/*! \brief Enables the pull-down resistor of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_enable_pin_pull_down(unsigned int pin);
+
+/*! \brief Disables the pull-down resistor of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_disable_pin_pull_down(unsigned int pin);
+
+/*! \brief Enables the buskeeper functionality on a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_enable_pin_buskeeper(unsigned int pin);
+
+/*! \brief Disables the buskeeper functionality on a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_disable_pin_buskeeper(unsigned int pin);
+
+#endif
+
+/*! \brief Returns the value of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \return The pin value.
+ */
+extern int gpio_get_pin_value(unsigned int pin);
+
+/*! \brief Returns the output value set for a GPIO pin.
+ *
+ * \param pin The pin number.
+ *
+ * \return The pin output value.
+ *
+ * \note This function must be used in conjunction with \ref gpio_set_gpio_pin,
+ *       \ref gpio_clr_gpio_pin and \ref gpio_tgl_gpio_pin.
+ */
+extern int gpio_get_gpio_pin_output_value(unsigned int pin);
+
+/*! \brief Returns the output value set for a GPIO pin using open drain.
+ *
+ * \param pin The pin number.
+ *
+ * \return The pin output value.
+ *
+ * \note This function must be used in conjunction with
+ *       \ref gpio_set_gpio_open_drain_pin, \ref gpio_clr_gpio_open_drain_pin
+ *       and \ref gpio_tgl_gpio_open_drain_pin.
+ */
+extern int gpio_get_gpio_open_drain_pin_output_value(unsigned int pin);
+
+/*! \brief Drives a GPIO pin to 1.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_set_gpio_pin(unsigned int pin);
+
+/*! \brief Drives a GPIO pin to 0.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_clr_gpio_pin(unsigned int pin);
+
+/*! \brief Toggles a GPIO pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_tgl_gpio_pin(unsigned int pin);
+
+/*! \brief Drives a GPIO pin to 1 using open drain.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_set_gpio_open_drain_pin(unsigned int pin);
+
+/*! \brief Drives a GPIO pin to 0 using open drain.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_clr_gpio_open_drain_pin(unsigned int pin);
+
+/*! \brief Toggles a GPIO pin using open drain.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_tgl_gpio_open_drain_pin(unsigned int pin);
+
+/*! \brief Enables the glitch filter of a pin.
+ *
+ * When the glitch filter is enabled, a glitch with duration of less than 1
+ * clock cycle is automatically rejected, while a pulse with duration of 2 clock
+ * cycles or more is accepted. For pulse durations between 1 clock cycle and 2
+ * clock cycles, the pulse may or may not be taken into account, depending on
+ * the precise timing of its occurrence. Thus for a pulse to be guaranteed
+ * visible it must exceed 2 clock cycles, whereas for a glitch to be reliably
+ * filtered out, its duration must not exceed 1 clock cycle. The filter
+ * introduces 2 clock cycles latency.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_enable_pin_glitch_filter(unsigned int pin);
+
+/*! \brief Disables the glitch filter of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_disable_pin_glitch_filter(unsigned int pin);
+
+/*! \brief Enables the interrupt of a pin with the specified settings.
+ *
+ * \param pin The pin number.
+ * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
+ *             \ref GPIO_FALLING_EDGE).
+ *
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
+ */
+extern int gpio_enable_pin_interrupt(unsigned int pin, unsigned int mode);
+
+/*! \brief Disables the interrupt of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_disable_pin_interrupt(unsigned int pin);
+
+/*! \brief Gets the interrupt flag of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \return The pin interrupt flag.
+ */
+extern int gpio_get_pin_interrupt_flag(unsigned int pin);
+
+/*! \brief Clears the interrupt flag of a pin.
+ *
+ * \param pin The pin number.
+ */
+extern void gpio_clear_pin_interrupt_flag(unsigned int pin);
+
+//! @}
+
+
+#if (defined AVR32_GPIO_LOCAL_ADDRESS)
+/*! \name Local Bus Interface
+ *
+ * High-speed interface with only one clock cycle per access.
+ *
+ * This interface operates with high clock frequency (fCPU), and its timing is
+ * deterministic since it does not need to access a shared bus which may be
+ * heavily loaded.
+ *
+ * \warning To use this interface, the clock frequency of the peripheral bus on
+ *          which the GPIO peripheral is connected must be set to the CPU clock
+ *          frequency (fPB = fCPU).
+ *
+ * \note This interface has to be initialized in order to be available.
+ */
+//! @{
+
+/*! \brief Enables the local bus interface for GPIO.
+ *
+ * \note This function must have been called at least once before using other
+ *       functions in this interface.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_init(void)
+{
+  Set_system_register(AVR32_CPUCR,
+                      Get_system_register(AVR32_CPUCR) | AVR32_CPUCR_LOCEN_MASK);
+}
+
+/*! \brief Enables the output driver of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_enable_pin_output_driver(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
+}
+
+/*! \brief Disables the output driver of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_disable_pin_output_driver(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
+}
+
+/*! \brief Returns the value of a pin.
+ *
+ * \param pin The pin number.
+ *
+ * \return The pin value.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ int gpio_local_get_pin_value(unsigned int pin)
+{
+  return (AVR32_GPIO_LOCAL.port[pin >> 5].pvr >> (pin & 0x1F)) & 1;
+}
+
+/*! \brief Drives a GPIO pin to 1.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin nor its output
+ *       driver. \ref gpio_enable_gpio_pin and
+ *       \ref gpio_local_enable_pin_output_driver can be called for this
+ *       purpose.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_set_gpio_pin(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrs = 1 << (pin & 0x1F);
+}
+
+/*! \brief Drives a GPIO pin to 0.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin nor its output
+ *       driver. \ref gpio_enable_gpio_pin and
+ *       \ref gpio_local_enable_pin_output_driver can be called for this
+ *       purpose.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_clr_gpio_pin(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
+}
+
+/*! \brief Toggles a GPIO pin.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init must have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin nor its output
+ *       driver. \ref gpio_enable_gpio_pin and
+ *       \ref gpio_local_enable_pin_output_driver can be called for this
+ *       purpose.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_tgl_gpio_pin(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrt = 1 << (pin & 0x1F);
+}
+
+/*! \brief Initializes the configuration of a GPIO pin so that it can be used
+ *         with GPIO open-drain functions.
+ *
+ * \note This function must have been called at least once before using
+ *       \ref gpio_local_set_gpio_open_drain_pin,
+ *       \ref gpio_local_clr_gpio_open_drain_pin or
+ *       \ref gpio_local_tgl_gpio_open_drain_pin.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_init_gpio_open_drain_pin(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].ovrc = 1 << (pin & 0x1F);
+}
+
+/*! \brief Drives a GPIO pin to 1 using open drain.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
+ *       have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_set_gpio_open_drain_pin(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].oderc = 1 << (pin & 0x1F);
+}
+
+/*! \brief Drives a GPIO pin to 0 using open drain.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
+ *       have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_clr_gpio_open_drain_pin(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].oders = 1 << (pin & 0x1F);
+}
+
+/*! \brief Toggles a GPIO pin using open drain.
+ *
+ * \param pin The pin number.
+ *
+ * \note \ref gpio_local_init and \ref gpio_local_init_gpio_open_drain_pin must
+ *       have been called beforehand.
+ *
+ * \note This function does not enable the GPIO mode of the pin.
+ *       \ref gpio_enable_gpio_pin can be called for this purpose.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_local_tgl_gpio_open_drain_pin(unsigned int pin)
+{
+  AVR32_GPIO_LOCAL.port[pin >> 5].odert = 1 << (pin & 0x1F);
+}
+
+//! @}
+#endif // AVR32_GPIO_LOCAL_ADDRESS
+
+#if UC3L
+//! @{
+/*! \name Peripheral Event System support
+ *
+ * The GPIO can be programmed to output peripheral events whenever an interrupt
+ * condition is detected, such as pin value change, or only when a rising or
+ * falling edge is detected.
+ *
+ */
+
+/*! \brief Enables the peripheral event generation of a pin.
+ *
+ * \param pin The pin number.
+ *
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_enable_pin_periph_event(unsigned int pin)
+{
+  AVR32_GPIO.port[pin >> 5].oderc = 1 << (pin & 0x1F); // The GPIO output driver is disabled for that pin.
+  AVR32_GPIO.port[pin >> 5].evers = 1 << (pin & 0x1F);
+}
+
+/*! \brief Disables the peripheral event generation of a pin.
+ *
+ * \param pin The pin number.
+ *
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ void gpio_disable_pin_periph_event(unsigned int pin)
+{
+  AVR32_GPIO.port[pin >> 5].everc = 1 << (pin & 0x1F);
+}
+
+/*! \brief Configure the peripheral event trigger mode of a pin
+ *
+ * \param pin The pin number.
+ * \param mode The trigger mode (\ref GPIO_PIN_CHANGE, \ref GPIO_RISING_EDGE or
+ *             \ref GPIO_FALLING_EDGE).
+ * \param use_igf use the Input Glitch Filter (TRUE) or not (FALSE).
+ *
+ * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT.
+ */
+extern int gpio_configure_pin_periph_event_mode(unsigned int pin, unsigned int mode, unsigned int use_igf);
+
+//! @}
+#endif
+
+
+#endif  // _GPIO_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/exception.x

@@ -0,0 +1,239 @@
+/* This file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#if !__AVR32_UC__ && !__AVR32_AP__
+  #error Implementation of the AVR32 architecture not supported by the INTC driver.
+#endif
+
+
+#include <avr32/io.h>
+
+
+//! @{
+//! \verbatim
+
+
+  .section  .exception, "ax", @progbits
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  .balign 0x200
+
+  // Export symbol.
+  .global _evba
+  .type _evba, @function
+_evba:
+
+        .org  0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        .org  0x004
+        // TLB Multiple Hit.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        .org  0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        .org  0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        .org  0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        .org  0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        .org  0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        .org  0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        .org  0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        .org  0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        .org  0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        .org  0x02C
+        // Floating-Point: UNUSED IN AVR32UC and AVR32AP.
+_handle_Floating_Point:
+        rjmp $
+
+        .org  0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        .org  0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        .org  0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        .org  0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        .org  0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        .org  0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        .org  0x050
+        // ITLB Miss.
+_handle_ITLB_Miss:
+        rjmp $
+
+        .org  0x060
+        // DTLB Miss (Read).
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        .org  0x070
+        // DTLB Miss (Write).
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        .org  0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        rjmp $
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  .balign 4
+
+  .irp    priority, 0, 1, 2, 3
+_int\priority:
+#if __AVR32_UC__
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry. No other register is saved by hardware.
+#elif __AVR32_AP__
+  // PC and SR are automatically saved in respectively RAR_INTx and RSR_INTx by
+  // the CPU upon interrupt entry. No other register is saved by hardware.
+  pushm   r8-r12, lr
+#endif
+  mov     r12, \priority  // Pass the int_level parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0          // Get the pointer to the interrupt handler returned by the function.
+#if __AVR32_UC__
+  movne   pc, r12         // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+#elif __AVR32_AP__
+  breq    spint\priority  // If this was a spurious interrupt (R12 == NULL), branch.
+  st.w    --sp, r12       // Push the pointer to the interrupt handler onto the system stack since no register may be altered.
+  popm    r8-r12, lr, pc  // Restore registers and jump to the handler.
+spint\priority:
+  popm    r8-r12, lr
+#endif
+  rete                    // If this was a spurious interrupt (R12 == NULL), return from event handler.
+  .endr
+
+
+// Constant data area.
+
+  .balign 4
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  .global ipr_val
+  .type ipr_val, @object
+ipr_val:
+  .word (AVR32_INTC_INT0 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int0 - _evba),\
+        (AVR32_INTC_INT1 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int1 - _evba),\
+        (AVR32_INTC_INT2 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int2 - _evba),\
+        (AVR32_INTC_INT3 << AVR32_INTC_IPR_INTLEVEL_OFFSET) | (_int3 - _evba)
+
+
+//! \endverbatim
+//! @}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.c

@@ -0,0 +1,214 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief INTC driver for AVR32 UC3.
+ *
+ * AVR32 Interrupt Controller driver module.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+#include "preprocessor.h"
+#include "intc.h"
+
+// define _evba from exception.S
+extern void _evba;
+
+//! Values to store in the interrupt priority registers for the various interrupt priority levels.
+extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
+
+//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space.
+//! Each line handler table contains a set of pointers to interrupt handlers.
+#if (defined __GNUC__)
+#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
+static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
+#elif (defined __ICCAVR32__)
+#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
+static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
+#endif
+MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
+#undef DECL_INT_LINE_HANDLER_TABLE
+
+//! Table containing for each interrupt group the number of interrupt request
+//! lines and a pointer to the table of interrupt line handlers.
+static const struct
+{
+  unsigned int num_irqs;
+  volatile __int_handler *_int_line_handler_table;
+} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
+{
+#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
+  {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
+  MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
+#undef INSERT_INT_LINE_HANDLER_TABLE
+};
+
+
+/*! \brief Default interrupt handler.
+ *
+ * \note Taken and adapted from Newlib.
+ */
+#if (defined __GNUC__)
+__attribute__((__interrupt__))
+#elif (defined __ICCAVR32__)
+__interrupt
+#endif
+static void _unhandled_interrupt(void)
+{
+  // Catch unregistered interrupts.
+  while (TRUE);
+}
+
+
+/*! \brief Gets the interrupt handler of the current event at the \a int_level
+ *         interrupt priority level (called from exception.S).
+ *
+ * \param int_level Interrupt priority level to handle.
+ *
+ * \return Interrupt handler to execute.
+ *
+ * \note Taken and adapted from Newlib.
+ */
+__int_handler _get_interrupt_handler(unsigned int int_level)
+{
+  // ICR3 is mapped first, ICR0 last.
+  // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to
+  // pass a single argument to a function.
+  unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
+  unsigned int int_req = AVR32_INTC.irr[int_grp];
+
+  // As an interrupt may disappear while it is being fetched by the CPU
+  // (spurious interrupt caused by a delayed response from an MCU peripheral to
+  // an interrupt flag clear or interrupt disable instruction), check if there
+  // are remaining interrupt lines to process.
+  // If a spurious interrupt occurs, the status register (SR) contains an
+  // execution mode and interrupt level masks corresponding to a level 0
+  // interrupt, whatever the interrupt priority level causing the spurious
+  // event. This behavior has been chosen because a spurious interrupt has not
+  // to be a priority one and because it may not cause any trouble to other
+  // interrupts.
+  // However, these spurious interrupts place the hardware in an unstable state
+  // and could give problems in other/future versions of the CPU, so the
+  // software has to be written so that they never occur. The only safe way of
+  // achieving this is to always clear or disable peripheral interrupts with the
+  // following sequence:
+  // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
+  // 2: Perform the bus access to the peripheral register that clears or
+  //    disables the interrupt.
+  // 3: Wait until the interrupt has actually been cleared or disabled by the
+  //    peripheral. This is usually performed by reading from a register in the
+  //    same peripheral (it DOES NOT have to be the same register that was
+  //    accessed in step 2, but it MUST be in the same peripheral), what takes
+  //    bus system latencies into account, but peripheral internal latencies
+  //    (generally 0 cycle) also have to be considered.
+  // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
+  // Note that steps 1 and 4 are useless inside interrupt handlers as the
+  // corresponding interrupt level is automatically masked by IxM (unless IxM is
+  // explicitly cleared by the software).
+  //
+  // Get the right IRQ handler.
+  //
+  // If several interrupt lines are active in the group, the interrupt line with
+  // the highest number is selected. This is to be coherent with the
+  // prioritization of interrupt groups performed by the hardware interrupt
+  // controller.
+  //
+  // If no handler has been registered for the pending interrupt,
+  // _unhandled_interrupt will be selected thanks to the initialization of
+  // _int_line_handler_table_x by INTC_init_interrupts.
+  //
+  // exception.S will provide the interrupt handler with a clean interrupt stack
+  // frame, with nothing more pushed onto the stack. The interrupt handler must
+  // manage the `rete' instruction, what can be done thanks to pure assembly,
+  // inline assembly or the `__attribute__((__interrupt__))' C function
+  // attribute.
+  return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
+}
+
+//! Init EVBA address. This sequence might also be done in the UTILS/STARTUP/GCC/crt0.S
+static __inline__ void INTC_init_evba(void)
+{
+  Set_system_register(AVR32_EVBA, (int)&_evba );
+}
+
+void INTC_init_interrupts(void)
+{
+  unsigned int int_grp, int_req;
+
+  INTC_init_evba();
+
+  // For all interrupt groups,
+  for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
+  {
+    // For all interrupt request lines of each group,
+    for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
+    {
+      // Assign _unhandled_interrupt as default interrupt handler.
+      _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
+    }
+
+    // Set the interrupt group priority register to its default value.
+    // By default, all interrupt groups are linked to the interrupt priority
+    // level 0 and to the interrupt vector _int0.
+    AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
+  }
+}
+
+
+void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)
+{
+  // Determine the group of the IRQ.
+  unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
+
+  // Store in _int_line_handler_table_x the pointer to the interrupt handler, so
+  // that _get_interrupt_handler can retrieve it when the interrupt is vectored.
+  _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
+
+  // Program the corresponding IPRX register to set the interrupt priority level
+  // and the interrupt vector offset that will be fetched by the core interrupt
+  // system.
+  // NOTE: The _intx functions are intermediate assembly functions between the
+  // core interrupt system and the user interrupt handler.
+  AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/INTC/intc.h

@@ -0,0 +1,100 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief INTC driver for AVR32 UC3.
+ *
+ * AVR32 Interrupt Controller driver module.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _INTC_H_
+#define _INTC_H_
+
+#include "compiler.h"
+
+
+//! Maximal number of interrupt request lines per group.
+#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP             32
+
+//! Number of interrupt priority levels.
+#define AVR32_INTC_NUM_INT_LEVELS                   (1 << AVR32_INTC_IPR_INTLEVEL_SIZE)
+
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+//! Pointer to interrupt handler.
+#if (defined __GNUC__)
+typedef void (*__int_handler)(void);
+#elif (defined __ICCAVR32__)
+typedef void (__interrupt *__int_handler)(void);
+#endif
+
+
+/*! \brief Initializes the hardware interrupt controller driver.
+ *
+ * \note Taken and adapted from Newlib.
+ */
+extern void INTC_init_interrupts(void);
+
+/*! \brief Registers an interrupt handler.
+ *
+ * \param handler   Interrupt handler to register.
+ * \param irq       IRQ of the interrupt handler to register.
+ * \param int_level Interrupt priority level to assign to the group of this IRQ.
+ *
+ * \warning The interrupt handler must manage the `rete' instruction, what can
+ *          be done thanks to pure assembly, inline assembly or the
+ *          `__attribute__((__interrupt__))' C function attribute.
+ *
+ * \warning If several interrupt handlers of a same group are registered with
+ *          different priority levels, only the latest priority level set will
+ *          be effective.
+ *
+ * \note Taken and adapted from Newlib.
+ */
+extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level);
+
+#endif  // __AVR32_ABI_COMPILER__
+
+
+#endif  // _INTC_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA/pdca.c

@@ -0,0 +1,296 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief PDCA driver for AVR32 UC3.
+ *
+ * This file defines a useful set of functions for the PDCA interface on AVR32
+ * devices.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a PDCA module.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include "compiler.h"
+#include "pdca.h"
+
+
+volatile avr32_pdca_channel_t *pdca_get_handler(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = &AVR32_PDCA.channel[pdca_ch_number];
+
+  if (pdca_ch_number >= AVR32_PDCA_CHANNEL_LENGTH)
+    return (volatile avr32_pdca_channel_t *)PDCA_INVALID_ARGUMENT;
+
+  return pdca_channel;
+}
+
+
+int pdca_init_channel(unsigned int pdca_ch_number, const pdca_channel_options_t *opt)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_disable_interrupt_transfer_complete(pdca_ch_number); // disable channel interrupt
+  pdca_disable_interrupt_reload_counter_zero(pdca_ch_number); // disable channel interrupt
+
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  pdca_channel->mar = (unsigned long)opt->addr;
+  pdca_channel->tcr = opt->size;
+  pdca_channel->psr = opt->pid;
+  pdca_channel->marr = (unsigned long)opt->r_addr;
+  pdca_channel->tcrr = opt->r_size;
+  pdca_channel->mr =
+#if (defined AVR32_PDCA_120_H_INCLUDED ) || (defined AVR32_PDCA_121_H_INCLUDED ) || (defined AVR32_PDCA_122_H_INCLUDED )
+opt->etrig << AVR32_PDCA_ETRIG_OFFSET |
+#endif // #ifdef AVR32_PDCA_120_H_INCLUDED
+                     opt->transfer_size << AVR32_PDCA_SIZE_OFFSET;
+  pdca_channel->cr = AVR32_PDCA_ECLR_MASK;
+  pdca_channel->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+
+  return PDCA_SUCCESS;
+}
+
+
+unsigned int pdca_get_channel_status(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  return (pdca_channel->sr & AVR32_PDCA_TEN_MASK) != 0;
+}
+
+
+void pdca_disable(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  // Disable transfer
+  pdca_channel->cr = AVR32_PDCA_TDIS_MASK;
+
+}
+
+
+void pdca_enable(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  // Enable transfer
+  pdca_channel->cr = AVR32_PDCA_TEN_MASK;
+}
+
+
+unsigned int pdca_get_load_size(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  return pdca_channel->tcr;
+}
+
+
+void pdca_load_channel(unsigned int pdca_ch_number, volatile void *addr, unsigned int size)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  pdca_channel->mar = (unsigned long)addr;
+  pdca_channel->tcr = size;
+  pdca_channel->cr = AVR32_PDCA_ECLR_MASK;
+  pdca_channel->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+unsigned int pdca_get_reload_size(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  return pdca_channel->tcrr;
+}
+
+
+void pdca_reload_channel(unsigned int pdca_ch_number, volatile void *addr, unsigned int size)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  // set up next memory address
+  pdca_channel->marr = (unsigned long)addr;
+  // set up next memory size
+  pdca_channel->tcrr = size;
+  pdca_channel->cr = AVR32_PDCA_ECLR_MASK;
+  pdca_channel->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void pdca_set_peripheral_select(unsigned int pdca_ch_number, unsigned int pid)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_channel->psr = pid;
+}
+
+
+void pdca_set_transfer_size(unsigned int pdca_ch_number, unsigned int transfer_size)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_channel->mr = (pdca_channel->mr & ~AVR32_PDCA_SIZE_MASK) |
+                     transfer_size << AVR32_PDCA_SIZE_OFFSET;
+}
+
+
+#if (defined AVR32_PDCA_120_H_INCLUDED ) || (defined AVR32_PDCA_121_H_INCLUDED ) || (defined AVR32_PDCA_122_H_INCLUDED )
+
+
+void pdca_disable_event_trigger(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_channel->mr &= ~AVR32_PDCA_ETRIG_MASK;
+}
+
+
+void pdca_enable_event_trigger(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_channel->mr |= AVR32_PDCA_ETRIG_MASK;
+}
+
+
+#endif // #ifdef AVR32_PDCA_120_H_INCLUDED
+
+
+void pdca_disable_interrupt_transfer_error(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  pdca_channel->idr = AVR32_PDCA_TERR_MASK;
+  pdca_channel->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void pdca_enable_interrupt_transfer_error(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_channel->ier = AVR32_PDCA_TERR_MASK;
+}
+
+
+void pdca_disable_interrupt_transfer_complete(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  pdca_channel->idr = AVR32_PDCA_TRC_MASK;
+  pdca_channel->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void pdca_enable_interrupt_transfer_complete(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_channel->ier = AVR32_PDCA_TRC_MASK;
+}
+
+
+void pdca_disable_interrupt_reload_counter_zero(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  pdca_channel->idr = AVR32_PDCA_RCZ_MASK;
+  pdca_channel->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void pdca_enable_interrupt_reload_counter_zero(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  pdca_channel->ier = AVR32_PDCA_RCZ_MASK;
+}
+
+
+unsigned long pdca_get_transfer_status(unsigned int pdca_ch_number)
+{
+  // get the correct channel pointer
+  volatile avr32_pdca_channel_t *pdca_channel = pdca_get_handler(pdca_ch_number);
+
+  return pdca_channel->isr;
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PDCA/pdca.h

@@ -0,0 +1,251 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief PDCA driver for AVR32 UC3.
+ *
+ * This file defines a useful set of functions for the PDCA interface on AVR32
+ * devices.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a PDCA module.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _PDCA_H_
+#define _PDCA_H_
+
+#include <avr32/io.h>
+
+
+//! Size of PDCA transfer: byte.
+#define PDCA_TRANSFER_SIZE_BYTE               AVR32_PDCA_BYTE
+
+//! Size of PDCA transfer: half-word.
+#define PDCA_TRANSFER_SIZE_HALF_WORD          AVR32_PDCA_HALF_WORD
+
+//! Size of PDCA transfer: word.
+#define PDCA_TRANSFER_SIZE_WORD               AVR32_PDCA_WORD
+
+/*! \name PDCA Driver Status Codes
+ */
+//! @{
+#define PDCA_SUCCESS 0
+#define PDCA_INVALID_ARGUMENT -1
+//! @}
+
+/*! \name PDCA Transfer Status Codes
+ */
+//! @{
+#define PDCA_TRANSFER_ERROR                   AVR32_PDCA_TERR_MASK
+#define PDCA_TRANSFER_COMPLETE                AVR32_PDCA_TRC_MASK
+#define PDCA_TRANSFER_COUNTER_RELOAD_IS_ZERO  AVR32_PDCA_RCZ_MASK
+//! @}
+
+
+//! PDCA channel options.
+typedef struct
+{
+  //! Memory address.
+  volatile  void         *addr          ;
+  //! Transfer counter.
+            unsigned int  size          ;
+  //! Next memory address.
+  volatile  void         *r_addr        ;
+  //! Next transfer counter.
+            unsigned int  r_size        ;
+  //! Select peripheral ID.
+            unsigned int  pid           ;
+  //! Select the size of the transfer (byte, half-word or word).
+            unsigned int  transfer_size ;
+#if (defined AVR32_PDCA_120_H_INCLUDED ) || (defined AVR32_PDCA_121_H_INCLUDED ) || (defined AVR32_PDCA_122_H_INCLUDED )
+// Note: the options in this preprocessor section are only available from the PDCA IP version 1.2.0 on.
+  //! Enable (\c 1) or disable (\c 0) the transfer upon event trigger.
+            unsigned char etrig         ;
+#endif // #ifdef AVR32_PDCA_120_H_INCLUDED
+} pdca_channel_options_t;
+
+
+/*! \brief Get PDCA channel handler
+ *
+ * \param pdca_ch_number  PDCA channel
+ *
+ * \return channel handled or PDCA_INVALID_ARGUMENT
+ */
+extern volatile avr32_pdca_channel_t *pdca_get_handler(unsigned int pdca_ch_number);
+
+/*! \brief Set the channel configuration
+ *
+ * \param pdca_ch_number PDCA channel
+ * \param opt channel option
+ */
+extern int pdca_init_channel(unsigned int pdca_ch_number, const pdca_channel_options_t *opt);
+
+/*! \brief Get the PDCA channel transfer enable status
+ *
+ * \param pdca_ch_number PDCA channel
+ *
+ * \return \c 1 if channel transfer is enabled, else \c 0
+ */
+extern unsigned int pdca_get_channel_status(unsigned int pdca_ch_number);
+
+/*! \brief Disable the PDCA for the given channel
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_disable(unsigned int pdca_ch_number);
+
+/*! \brief Enable the PDCA for the given channel
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_enable(unsigned int pdca_ch_number);
+
+/*! \brief Get PDCA channel load size (or remaining size if transfer started)
+ *
+ * \param pdca_ch_number PDCA channel
+ *
+ * \return size           current size to transfer
+ */
+extern unsigned int pdca_get_load_size(unsigned int pdca_ch_number);
+
+/*! \brief Set PDCA channel load values
+ *
+ * \param pdca_ch_number PDCA channel
+ * \param addr           address where data to load are stored
+ * \param size           size of the data block to load
+ */
+extern void pdca_load_channel(unsigned int pdca_ch_number, volatile void *addr, unsigned int size);
+
+/*! \brief Get PDCA channel reload size
+ *
+ * \param pdca_ch_number PDCA channel
+ *
+ * \return size           current reload size
+ */
+extern unsigned int pdca_get_reload_size(unsigned int pdca_ch_number);
+
+/*! \brief Set PDCA channel reload values
+ *
+ * \param pdca_ch_number PDCA channel
+ * \param addr           address where data to load are stored
+ * \param size           size of the data block to load
+ */
+extern void pdca_reload_channel(unsigned int pdca_ch_number, volatile void *addr, unsigned int size);
+
+/*! \brief Set the peripheral function to use with the PDCA channel
+ *
+ * \param pdca_ch_number PDCA channel
+ * \param pid the peripheral ID
+ */
+extern void pdca_set_peripheral_select(unsigned int pdca_ch_number, unsigned int pid);
+
+/*! \brief Set the size of the transfer
+ *
+ * \param pdca_ch_number PDCA channel
+ * \param transfer_size size of the transfer (byte, half-word or word)
+ */
+extern void pdca_set_transfer_size(unsigned int pdca_ch_number, unsigned int transfer_size);
+
+#if (defined AVR32_PDCA_120_H_INCLUDED ) || (defined AVR32_PDCA_121_H_INCLUDED ) || (defined AVR32_PDCA_122_H_INCLUDED )
+// Note: the functions in this preprocessor section are only available from the PDCA IP version 1.2.0 on.
+
+/*! \brief Disable the event-triggered transfer feature
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_disable_event_trigger(unsigned int pdca_ch_number);
+
+/*! \brief Enable the event-triggered transfer feature
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_enable_event_trigger(unsigned int pdca_ch_number);
+
+#endif // #ifdef AVR32_PDCA_120_H_INCLUDED
+
+/*! \brief Disable PDCA transfer error interrupt
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_disable_interrupt_transfer_error(unsigned int pdca_ch_number);
+
+/*! \brief Enable PDCA transfer error interrupt
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_enable_interrupt_transfer_error(unsigned int pdca_ch_number);
+
+/*! \brief Disable PDCA transfer interrupt when completed (ie TCR and TCRR are both zero)
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_disable_interrupt_transfer_complete(unsigned int pdca_ch_number);
+
+/*! \brief Enable PDCA transfer interrupt when completed (ie TCR and TCRR are both zero)
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_enable_interrupt_transfer_complete(unsigned int pdca_ch_number);
+
+/*! \brief Disable PDCA transfer interrupt when TCRR reaches zero
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_disable_interrupt_reload_counter_zero(unsigned int pdca_ch_number);
+
+/*! \brief Enable PDCA transfer interrupt when TCRR reaches zero
+ *
+ * \param pdca_ch_number PDCA channel
+ */
+extern void pdca_enable_interrupt_reload_counter_zero(unsigned int pdca_ch_number);
+
+/*! \brief Get PDCA channel transfer status
+ *
+ * \param pdca_ch_number PDCA channel
+ *
+ * \return PDCA transfer status with the following bit-masks:\n
+ *           - \c PDCA_TRANSFER_ERROR;\n
+ *           - \c PDCA_TRANSFER_COMPLETE;\n
+ *           - \c PDCA_TRANSFER_COUNTER_RELOAD_IS_ZERO.
+ */
+extern unsigned long pdca_get_transfer_status(unsigned int pdca_ch_number);
+
+
+#endif  // _PDCA_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.c

@@ -0,0 +1,546 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Power Manager driver.
+ *
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include "compiler.h"
+#include "pm.h"
+
+
+/*! \name PM Writable Bit-Field Registers
+ */
+//! @{
+
+typedef union
+{
+  unsigned long                 mcctrl;
+  avr32_pm_mcctrl_t             MCCTRL;
+} u_avr32_pm_mcctrl_t;
+
+typedef union
+{
+  unsigned long                 cksel;
+  avr32_pm_cksel_t              CKSEL;
+} u_avr32_pm_cksel_t;
+
+typedef union
+{
+  unsigned long                 pll;
+  avr32_pm_pll_t                PLL;
+} u_avr32_pm_pll_t;
+
+typedef union
+{
+  unsigned long                 oscctrl0;
+  avr32_pm_oscctrl0_t           OSCCTRL0;
+} u_avr32_pm_oscctrl0_t;
+
+typedef union
+{
+  unsigned long                 oscctrl1;
+  avr32_pm_oscctrl1_t           OSCCTRL1;
+} u_avr32_pm_oscctrl1_t;
+
+typedef union
+{
+  unsigned long                 oscctrl32;
+  avr32_pm_oscctrl32_t          OSCCTRL32;
+} u_avr32_pm_oscctrl32_t;
+
+typedef union
+{
+  unsigned long                 ier;
+  avr32_pm_ier_t                IER;
+} u_avr32_pm_ier_t;
+
+typedef union
+{
+  unsigned long                 idr;
+  avr32_pm_idr_t                IDR;
+} u_avr32_pm_idr_t;
+
+typedef union
+{
+  unsigned long                 icr;
+  avr32_pm_icr_t                ICR;
+} u_avr32_pm_icr_t;
+
+typedef union
+{
+  unsigned long                 gcctrl;
+  avr32_pm_gcctrl_t             GCCTRL;
+} u_avr32_pm_gcctrl_t;
+
+typedef union
+{
+  unsigned long                 rccr;
+  avr32_pm_rccr_t               RCCR;
+} u_avr32_pm_rccr_t;
+
+typedef union
+{
+  unsigned long                 bgcr;
+  avr32_pm_bgcr_t               BGCR;
+} u_avr32_pm_bgcr_t;
+
+typedef union
+{
+  unsigned long                 vregcr;
+  avr32_pm_vregcr_t             VREGCR;
+} u_avr32_pm_vregcr_t;
+
+typedef union
+{
+  unsigned long                 bod;
+  avr32_pm_bod_t                BOD;
+} u_avr32_pm_bod_t;
+
+//! @}
+
+
+/*! \brief Sets the mode of the oscillator 0.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x).
+ */
+static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)
+{
+  // Read
+  u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
+  // Modify
+  u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;
+  // Write
+  pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
+}
+
+
+void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)
+{
+  pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);
+}
+
+
+void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)
+{
+  pm_set_osc0_mode(pm, (fosc0 <  900000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 :
+                       (fosc0 < 3000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 :
+                       (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
+                                           AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);
+}
+
+
+void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)
+{
+  pm_enable_clk0_no_wait(pm, startup);
+  pm_wait_for_clk0_ready(pm);
+}
+
+
+void pm_disable_clk0(volatile avr32_pm_t *pm)
+{
+  pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;
+}
+
+
+void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
+{
+  // Read register
+  u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
+  // Modify
+  u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;
+  // Write back
+  pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
+
+  pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;
+}
+
+
+void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)
+{
+  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));
+}
+
+
+/*! \brief Sets the mode of the oscillator 1.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x).
+ */
+static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)
+{
+  // Read
+  u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
+  // Modify
+  u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;
+  // Write
+  pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
+}
+
+
+void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)
+{
+  pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);
+}
+
+
+void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)
+{
+  pm_set_osc1_mode(pm, (fosc1 <  900000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 :
+                       (fosc1 < 3000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 :
+                       (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
+                                           AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);
+}
+
+
+void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)
+{
+  pm_enable_clk1_no_wait(pm, startup);
+  pm_wait_for_clk1_ready(pm);
+}
+
+
+void pm_disable_clk1(volatile avr32_pm_t *pm)
+{
+  pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;
+}
+
+
+void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
+{
+  // Read register
+  u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
+  // Modify
+  u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;
+  // Write back
+  pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
+
+  pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;
+}
+
+
+void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)
+{
+  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));
+}
+
+
+/*! \brief Sets the mode of the 32-kHz oscillator.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x).
+ */
+static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)
+{
+  // Read
+  u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
+  // Modify
+  u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;
+  // Write
+  pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
+}
+
+
+void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)
+{
+  pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);
+}
+
+
+void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)
+{
+  pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);
+}
+
+
+void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)
+{
+  pm_enable_clk32_no_wait(pm, startup);
+  pm_wait_for_clk32_ready(pm);
+}
+
+
+void pm_disable_clk32(volatile avr32_pm_t *pm)
+{
+  pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;
+}
+
+
+void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
+{
+  // Read register
+  u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
+  // Modify
+  u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;
+  u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;
+  // Write back
+  pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
+}
+
+
+void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
+{
+  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));
+}
+
+
+void pm_cksel(volatile avr32_pm_t *pm,
+              unsigned int pbadiv,
+              unsigned int pbasel,
+              unsigned int pbbdiv,
+              unsigned int pbbsel,
+              unsigned int hsbdiv,
+              unsigned int hsbsel)
+{
+  u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};
+
+  u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;
+  u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;
+  u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;
+  u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;
+  u_avr32_pm_cksel.CKSEL.pbasel = pbasel;
+  u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;
+  u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;
+  u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;
+
+  pm->cksel = u_avr32_pm_cksel.cksel;
+
+  // Wait for ckrdy bit and then clear it
+  while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
+}
+
+
+void pm_gc_setup(volatile avr32_pm_t *pm,
+                  unsigned int gc,
+                  unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
+                  unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
+                  unsigned int diven,
+                  unsigned int div)
+{
+  u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};
+
+  u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;
+  u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;
+  u_avr32_pm_gcctrl.GCCTRL.diven  = diven;
+  u_avr32_pm_gcctrl.GCCTRL.div    = div;
+
+  pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;
+}
+
+
+void pm_gc_enable(volatile avr32_pm_t *pm,
+                  unsigned int gc)
+{
+  pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;
+}
+
+
+void pm_gc_disable(volatile avr32_pm_t *pm,
+                   unsigned int gc)
+{
+  pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;
+}
+
+
+void pm_pll_setup(volatile avr32_pm_t *pm,
+                  unsigned int pll,
+                  unsigned int mul,
+                  unsigned int div,
+                  unsigned int osc,
+                  unsigned int lockcount)
+{
+  u_avr32_pm_pll_t u_avr32_pm_pll = {0};
+
+  u_avr32_pm_pll.PLL.pllosc   = osc;
+  u_avr32_pm_pll.PLL.plldiv   = div;
+  u_avr32_pm_pll.PLL.pllmul   = mul;
+  u_avr32_pm_pll.PLL.pllcount = lockcount;
+
+  pm->pll[pll] = u_avr32_pm_pll.pll;
+}
+
+
+void pm_pll_set_option(volatile avr32_pm_t *pm,
+                       unsigned int pll,
+                       unsigned int pll_freq,
+                       unsigned int pll_div2,
+                       unsigned int pll_wbwdisable)
+{
+  u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};
+  u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);
+  pm->pll[pll] = u_avr32_pm_pll.pll;
+}
+
+
+unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,
+                               unsigned int pll)
+{
+  return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;
+}
+
+
+void pm_pll_enable(volatile avr32_pm_t *pm,
+                  unsigned int pll)
+{
+  pm->pll[pll] |= AVR32_PM_PLLEN_MASK;
+}
+
+
+void pm_pll_disable(volatile avr32_pm_t *pm,
+                  unsigned int pll)
+{
+  pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;
+}
+
+
+void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
+{
+  while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));
+}
+
+
+void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
+{
+  while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));
+}
+
+
+void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
+{
+  // Read
+  u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
+  // Modify
+  u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;
+  // Write back
+  pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;
+}
+
+
+void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
+{
+  pm_enable_osc0_crystal(pm, fosc0);            // Enable the Osc0 in crystal mode
+  pm_enable_clk0(pm, startup);                  // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
+  pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);  // Then switch main clock to Osc0
+}
+
+
+void pm_bod_enable_irq(volatile avr32_pm_t *pm)
+{
+  pm->ier = AVR32_PM_IER_BODDET_MASK;
+}
+
+
+void pm_bod_disable_irq(volatile avr32_pm_t *pm)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  pm->idr = AVR32_PM_IDR_BODDET_MASK;
+  pm->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void pm_bod_clear_irq(volatile avr32_pm_t *pm)
+{
+  pm->icr = AVR32_PM_ICR_BODDET_MASK;
+}
+
+
+unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)
+{
+  return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);
+}
+
+
+unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)
+{
+  return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);
+}
+
+
+unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)
+{
+  return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;
+}
+
+
+unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp)
+{
+  return pm->gplp[gplp];
+}
+
+
+void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value)
+{
+  pm->gplp[gplp] = value;
+}
+
+
+long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module)
+{
+  unsigned long domain = module>>5;
+  unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain);
+
+  // Implementation-specific shortcut: the ckMASK registers are contiguous and
+  // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
+
+  *regptr |= (1<<(module%32));
+
+  return PASS;
+}
+
+long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module)
+{
+  unsigned long domain = module>>5;
+  unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain);
+
+  // Implementation-specific shortcut: the ckMASK registers are contiguous and
+  // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
+
+  *regptr &= ~(1<<(module%32));
+
+  return PASS;
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm.h

@@ -0,0 +1,493 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Power Manager driver.
+ *
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _PM_H_
+#define _PM_H_
+
+#include <avr32/io.h>
+#include "compiler.h"
+#include "preprocessor.h"
+
+
+/*! \brief Sets the MCU in the specified sleep mode.
+ *
+ * \param mode Sleep mode:
+ *   \arg \c AVR32_PM_SMODE_IDLE: Idle;
+ *   \arg \c AVR32_PM_SMODE_FROZEN: Frozen;
+ *   \arg \c AVR32_PM_SMODE_STANDBY: Standby;
+ *   \arg \c AVR32_PM_SMODE_STOP: Stop;
+ *   \arg \c AVR32_PM_SMODE_DEEP_STOP: DeepStop;
+ *   \arg \c AVR32_PM_SMODE_STATIC: Static.
+ */
+#define SLEEP(mode)   {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
+
+
+//! Input and output parameters when initializing PM clocks using pm_configure_clocks().
+typedef struct
+{
+  //! CPU frequency (input/output argument).
+  unsigned long cpu_f;
+
+  //! PBA frequency (input/output argument).
+  unsigned long pba_f;
+
+  //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
+  unsigned long osc0_f;
+
+  //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
+  unsigned long osc0_startup;
+} pm_freq_param_t;
+
+#define PM_FREQ_STATUS_FAIL   (-1)
+#define PM_FREQ_STATUS_OK     (0)
+
+
+/*! \brief Gets the MCU reset cause.
+ *
+ * \param pm Base address of the Power Manager instance (i.e. &AVR32_PM).
+ *
+ * \return The MCU reset cause which can be masked with the
+ *         \c AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.
+ */
+#if (defined __GNUC__)
+__attribute__((__always_inline__))
+#endif
+extern __inline__ unsigned int pm_get_reset_cause(volatile avr32_pm_t *pm)
+{
+  return pm->rcause;
+}
+
+
+/*!
+ * \brief This function will enable the external clock mode of the oscillator 0.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the crystal mode of the oscillator 0.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param fosc0 Oscillator 0 crystal frequency (Hz)
+ */
+extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0);
+
+
+/*!
+ * \brief This function will enable the oscillator 0 to be used with a startup time.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
+ */
+extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup);
+
+
+/*!
+ * \brief This function will disable the oscillator 0.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_disable_clk0(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the oscillator 0 to be used with no startup time.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
+ */
+extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
+
+
+/*!
+ * \brief This function will wait until the Osc0 clock is ready.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the external clock mode of the oscillator 1.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the crystal mode of the oscillator 1.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param fosc1 Oscillator 1 crystal frequency (Hz)
+ */
+extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1);
+
+
+/*!
+ * \brief This function will enable the oscillator 1 to be used with a startup time.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
+ */
+extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup);
+
+
+/*!
+ * \brief This function will disable the oscillator 1.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_disable_clk1(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the oscillator 1 to be used with no startup time.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.
+ */
+extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
+
+
+/*!
+ * \brief This function will wait until the Osc1 clock is ready.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the external clock mode of the 32-kHz oscillator.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the crystal mode of the 32-kHz oscillator.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the oscillator 32 to be used with a startup time.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
+ */
+extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup);
+
+
+/*!
+ * \brief This function will disable the oscillator 32.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_disable_clk32(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will enable the oscillator 32 to be used with no startup time.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.
+ */
+extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup);
+
+
+/*!
+ * \brief This function will wait until the osc32 clock is ready.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will select all the power manager clocks.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param pbadiv Peripheral Bus A clock divisor enable
+ * \param pbasel Peripheral Bus A select
+ * \param pbbdiv Peripheral Bus B clock divisor enable
+ * \param pbbsel Peripheral Bus B select
+ * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
+ * \param hsbsel High Speed Bus select (CPU clock = HSB clock )
+ */
+extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel);
+
+
+/*!
+ * \brief This function will setup a generic clock.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param gc generic clock number (0 for gc0...)
+ * \param osc_or_pll Use OSC (=0) or PLL (=1)
+ * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1
+ * \param diven Generic clock divisor enable
+ * \param div Generic clock divisor
+ */
+extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div);
+
+
+/*!
+ * \brief This function will enable a generic clock.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param gc generic clock number (0 for gc0...)
+ */
+extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc);
+
+
+/*!
+ * \brief This function will disable a generic clock.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param gc generic clock number (0 for gc0...)
+ */
+extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc);
+
+
+/*!
+ * \brief This function will setup a PLL.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)
+ * \param mul PLL MUL in the PLL formula
+ * \param div PLL DIV in the PLL formula
+ * \param osc OSC number (0 for osc0, 1 for osc1)
+ * \param lockcount PLL lockount
+ */
+extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount);
+
+
+/*!
+ * \brief This function will set a PLL option.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)
+ * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
+ * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
+ * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
+ */
+extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int  pll_freq, unsigned int  pll_div2, unsigned int  pll_wbwdisable);
+
+
+/*!
+ * \brief This function will get a PLL option.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)
+ * \return       Option
+ */
+extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll);
+
+
+/*!
+ * \brief This function will enable a PLL.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)
+ */
+extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll);
+
+
+/*!
+ * \brief This function will disable a PLL.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param pll PLL number(0 for PLL0, 1 for PLL1)
+ */
+extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll);
+
+
+/*!
+ * \brief This function will wait for PLL0 locked
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will wait for PLL1 locked
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ */
+extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief This function will switch the power manager main clock.
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.
+ */
+extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock);
+
+
+/*!
+ * \brief Switch main clock to clock Osc0 (crystal mode)
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param fosc0 Oscillator 0 crystal frequency (Hz)
+ * \param startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.
+ */
+extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup);
+
+
+/*! \brief Enables the Brown-Out Detector interrupt.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ */
+extern void pm_bod_enable_irq(volatile avr32_pm_t *pm);
+
+
+/*! \brief Disables the Brown-Out Detector interrupt.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ */
+extern void pm_bod_disable_irq(volatile avr32_pm_t *pm);
+
+
+/*! \brief Clears the Brown-Out Detector interrupt flag.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ */
+extern void pm_bod_clear_irq(volatile avr32_pm_t *pm);
+
+
+/*! \brief Gets the Brown-Out Detector interrupt flag.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ *
+ * \retval 0 No BOD interrupt.
+ * \retval 1 BOD interrupt pending.
+ */
+extern unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm);
+
+
+/*! \brief Gets the Brown-Out Detector interrupt enable status.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ *
+ * \retval 0 BOD interrupt disabled.
+ * \retval 1 BOD interrupt enabled.
+ */
+extern unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm);
+
+
+/*! \brief Gets the triggering threshold of the Brown-Out Detector.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
+ *
+ * \return Triggering threshold of the BOD. See the electrical characteristics
+ *         in the part datasheet for actual voltage levels.
+ */
+extern unsigned long pm_bod_get_level(volatile avr32_pm_t *pm);
+
+
+/*!
+ * \brief Read the content of the PM GPLP registers
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
+ *
+ * \return The content of the chosen GPLP register.
+ */
+extern unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp);
+
+
+/*!
+ * \brief Write into the PM GPLP registers
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
+ * \param value Value to write
+ */
+extern void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value);
+
+
+/*! \brief Enable the clock of a module.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param module The module to clock (use one of the defines in the part-specific
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
+ *
+ * \return Status.
+ *   \retval 0  Success.
+ *   \retval <0 An error occured.
+ */
+extern long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module);
+
+/*! \brief Disable the clock of a module.
+ *
+ * \param pm Base address of the Power Manager (i.e. &AVR32_PM)
+ * \param module The module to shut down (use one of the defines in the part-specific
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
+ *
+ * \return Status.
+ *   \retval 0  Success.
+ *   \retval <0 An error occured.
+ */
+extern long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module);
+
+
+
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
+ *         according to the user wishes.
+ *
+ * This function needs some parameters stored in a pm_freq_param_t structure:
+ *  - cpu_f and pba_f are the wanted frequencies,
+ *  - osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
+ *  - osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).
+ *
+ * The function will then configure the clocks using the following rules:
+ *  - It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order
+ *    to satisfy the CPU frequency,
+ *  - It optimizes the configuration depending the various divide stages,
+ *  - Then, the PBA frequency is configured from the CPU freq.
+ *  - Note that HSB and PBB are configured with the same frequency as CPU.
+ *  - Note also that the number of wait states of the flash read accesses is automatically set-up depending
+ *    the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.
+ *
+ * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
+ *
+ * \param param    pointer on the configuration structure.
+ *
+ * \retval PM_FREQ_STATUS_OK    Mode successfully initialized.
+ * \retval PM_FREQ_STATUS_FAIL  The configuration can not be done.
+ */
+extern int pm_configure_clocks(pm_freq_param_t *param);
+
+
+/*! \brief Automatically configure the USB clock.
+ *
+ * USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming
+ * a 12 MHz crystal is connected to it.
+ */
+extern void pm_configure_usb_clock(void);
+
+
+#endif  // _PM_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/pm_conf_clocks.c

@@ -0,0 +1,268 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Power Manager clocks configuration helper.
+ *
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include <string.h>
+#include "compiler.h"
+#include "pm.h"
+
+extern void flashc_set_wait_state(unsigned int wait_state);
+#if (defined AVR32_FLASHC_210_H_INCLUDED)
+extern void flashc_issue_command(unsigned int command, int page_number);
+#endif
+
+
+#define PM_MAX_MUL                ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1)
+
+
+int pm_configure_clocks(pm_freq_param_t *param)
+{
+  // Supported frequencies:
+  // Fosc0 mul div PLL div2_en cpu_f pba_f   Comment
+  //  12   15   1  192     1     12    12
+  //  12    9   3   40     1     20    20    PLL out of spec
+  //  12   15   1  192     1     24    12
+  //  12    9   1  120     1     30    15
+  //  12    9   3   40     0     40    20    PLL out of spec
+  //  12   15   1  192     1     48    12
+  //  12   15   1  192     1     48    24
+  //  12    8   1  108     1     54    27
+  //  12    9   1  120     1     60    15
+  //  12    9   1  120     1     60    30
+  //  12   10   1  132     1     66    16.5
+  //
+  unsigned long in_cpu_f  = param->cpu_f;
+  unsigned long in_osc0_f = param->osc0_f;
+  unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
+  unsigned long pll_freq, rest;
+  Bool b_div2_pba, b_div2_cpu;
+
+  // Switch to external Oscillator 0
+  pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
+
+  // Start with CPU freq config
+  if (in_cpu_f == in_osc0_f)
+  {
+    param->cpu_f = in_osc0_f;
+    param->pba_f = in_osc0_f;
+    return PM_FREQ_STATUS_OK;
+  }
+  else if (in_cpu_f < in_osc0_f)
+  {
+    // TBD
+  }
+
+  rest = in_cpu_f % in_osc0_f;
+
+  for (div = 1; div < 32; div++)
+  {
+    if ((div * rest) % in_osc0_f == 0)
+      break;
+  }
+  if (div == 32)
+    return PM_FREQ_STATUS_FAIL;
+
+  mul = (in_cpu_f * div) / in_osc0_f;
+
+  if (mul > PM_MAX_MUL)
+    return PM_FREQ_STATUS_FAIL;
+
+  // export 2power from PLL div to div2_cpu
+  while (!(div % 2))
+  {
+    div /= 2;
+    div2_cpu++;
+  }
+
+  // Here we know the mul and div parameter of the PLL config.
+  // . Check out if the PLL has a valid in_cpu_f.
+  // . Try to have for the PLL frequency (VCO output) the highest possible value
+  //   to reduce jitter.
+  while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
+  {
+    if (2 * mul > PM_MAX_MUL)
+      break;
+    mul *= 2;
+    div2_cpu++;
+  }
+
+  if (div2_cpu != 0)
+  {
+    div2_cpu--;
+    div2_en = 1;
+  }
+
+  pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
+
+  // Update real CPU Frequency
+  param->cpu_f = pll_freq / (1 << div2_cpu);
+  mul--;
+
+  pm_pll_setup(&AVR32_PM
+  , 0   // pll
+  , mul // mul
+  , div // div
+  , 0   // osc
+  , 16  // lockcount
+  );
+
+  pm_pll_set_option(&AVR32_PM
+  , 0 // pll
+  // PLL clock is lower than 160MHz: need to set pllopt.
+  , (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq
+  , div2_en // pll_div2
+  , 0 // pll_wbwdisable
+  );
+
+  rest = pll_freq;
+  while (rest > AVR32_PM_PBA_MAX_FREQ ||
+         rest != param->pba_f)
+  {
+    div2_pba++;
+    rest = pll_freq / (1 << div2_pba);
+    if (rest < param->pba_f)
+      break;
+  }
+
+  // Update real PBA Frequency
+  param->pba_f = pll_freq / (1 << div2_pba);
+
+  // Enable PLL0
+  pm_pll_enable(&AVR32_PM, 0);
+
+  // Wait for PLL0 locked
+  pm_wait_for_pll0_locked(&AVR32_PM);
+
+  if (div2_cpu)
+  {
+    b_div2_cpu = TRUE;
+    div2_cpu--;
+  }
+  else
+    b_div2_cpu = FALSE;
+
+  if (div2_pba)
+  {
+    b_div2_pba = TRUE;
+    div2_pba--;
+  }
+  else
+    b_div2_pba = FALSE;
+
+  pm_cksel(&AVR32_PM
+  , b_div2_pba, div2_pba // PBA
+  , b_div2_cpu, div2_cpu // PBB
+  , b_div2_cpu, div2_cpu // HSB
+  );
+
+  if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
+  {
+    flashc_set_wait_state(1);
+#if (defined AVR32_FLASHC_210_H_INCLUDED)
+    if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
+    else
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
+#endif
+  }
+  else
+  {
+    flashc_set_wait_state(0);
+#if (defined AVR32_FLASHC_210_H_INCLUDED)
+    if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
+    else
+      flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
+#endif
+  }
+
+  pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
+
+  return PM_FREQ_STATUS_OK;
+}
+
+
+void pm_configure_usb_clock(void)
+{
+#if UC3A3
+
+  // Setup USB GCLK.
+  pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc
+                  0,                  // osc_or_pll: use Osc (if 0) or PLL (if 1)
+                  0,                  // pll_osc: select Osc0/PLL0 or Osc1/PLL1
+                  0,                  // diven
+                  0);                 // div
+
+  // Enable USB GCLK.
+  pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
+#else
+  // Use 12MHz from OSC0 and generate 96 MHz
+  pm_pll_setup(&AVR32_PM, 1,  // pll.
+	  7,   // mul.
+	  1,   // div.
+	  0,   // osc.
+	  16); // lockcount.
+
+  pm_pll_set_option(&AVR32_PM, 1, // pll.
+	  1,  // pll_freq: choose the range 80-180MHz.
+	  1,  // pll_div2.
+	  0); // pll_wbwdisable.
+
+  // start PLL1 and wait forl lock
+  pm_pll_enable(&AVR32_PM, 1);
+
+  // Wait for PLL1 locked.
+  pm_wait_for_pll1_locked(&AVR32_PM);
+
+  pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB,  // gc.
+            1,  // osc_or_pll: use Osc (if 0) or PLL (if 1).
+            1,  // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
+            0,  // diven.
+            0); // div.
+  pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
+#endif
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.c

@@ -0,0 +1,566 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief High-level library abstracting features such as oscillators/pll/dfll
+ *        configuration, clock configuration, System-sensible parameters
+ *        configuration, buses clocks configuration, sleep mode, reset.
+ *
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+#include "power_clocks_lib.h"
+
+
+//! Device-specific data
+#if UC3L
+static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD declaration
+#endif
+
+#if UC3C
+static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param); // FORWARD declaration
+#endif
+
+long int pcl_configure_clocks(pcl_freq_param_t *param)
+{
+#ifndef AVR32_PM_VERSION_RESETVALUE
+  // Implementation for UC3A, UC3A3, UC3B parts.
+  return(pm_configure_clocks(param));
+#else
+  #ifdef AVR32_PM_410_H_INCLUDED
+    // Implementation for UC3C parts.
+    return(pcl_configure_clocks_uc3c(param));
+  #else
+    // Implementation for UC3L parts.
+    return(pcl_configure_clocks_uc3l(param));
+  #endif
+#endif
+}
+
+
+//! Device-specific implementation
+#if UC3L
+// FORWARD declaration
+static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src,
+                                                  unsigned long main_clock_freq_hz,
+                                                  pcl_freq_param_t *param);
+
+long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param)
+{
+  // Supported main clock sources: PCL_MC_RCSYS
+
+  // Supported synchronous clocks frequencies if RCSYS is the main clock source:
+  // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
+
+  // NOTE: by default, this implementation doesn't perform thorough checks on the
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that fCPU >= fPBx
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
+    return(-1);
+#endif
+
+#ifdef AVR32SFW_INPUT_CHECK
+    // Verify that the target frequencies are reachable.
+    if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
+      || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
+      return(-1);
+#endif
+
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
+}
+
+
+long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)
+{
+  // Supported main clock sources: PCL_MC_RC120M
+
+  // Supported synchronous clocks frequencies if RC120M is the main clock source:
+  // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
+
+  // NOTE: by default, this implementation doesn't perform thorough checks on the
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that fCPU >= fPBx
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
+    return(-1);
+#endif
+
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that the target frequencies are reachable.
+  if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
+    || (param->pbb_f > SCIF_RC120M_FREQ_HZ))
+    return(-1);
+#endif
+
+  // Start the 120MHz internal RCosc (RC120M) clock
+  scif_start_rc120M();
+
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
+}
+
+
+long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)
+{
+  // Supported main clock sources: PCL_MC_OSC0
+
+  // Supported synchronous clocks frequencies if OSC0 is the main clock source:
+  // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
+  // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
+
+  // NOTE: by default, this implementation doesn't perform thorough checks on the
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+
+  unsigned long               main_clock_freq;
+
+
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that fCPU >= fPBx
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
+    return(-1);
+#endif
+
+  main_clock_freq = param->osc0_f;
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that the target frequencies are reachable.
+  if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
+    || (param->pbb_f > main_clock_freq))
+    return(-1);
+#endif
+  // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
+  scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
+  // Enable the OSC0
+  scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
+
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
+}
+
+
+long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)
+{
+  // Supported main clock sources: PCL_MC_DFLL
+
+  // Supported synchronous clocks frequencies if DFLL is the main clock source:
+  // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
+  // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
+
+  // NOTE: by default, this implementation doesn't perform thorough checks on the
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+
+  unsigned long   main_clock_freq;
+  scif_gclk_opt_t *pgc_dfllif_ref_opt;
+
+
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that fCPU >= fPBx
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
+    return(-1);
+#endif
+
+  main_clock_freq = param->dfll_f;
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that the target DFLL output frequency is in the correct range.
+  if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
+    return(-1);
+  // Verify that the target frequencies are reachable.
+  if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
+    || (param->pbb_f > main_clock_freq))
+    return(-1);
+#endif
+  pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params;
+  // Implementation note: this implementation configures the DFLL in closed-loop
+  // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF
+  // as a reference (RCSYS being used as the generic clock source, undivided).
+  scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE);
+
+  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
+}
+
+
+static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param)
+{
+  // Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M
+
+  // Supported synchronous clocks frequencies if RCSYS is the main clock source:
+  // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
+
+  // Supported synchronous clocks frequencies if RC120M is the main clock source:
+  // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
+
+  // Supported synchronous clocks frequencies if OSC0 is the main clock source:
+  // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
+  // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
+
+  // Supported synchronous clocks frequencies if DFLL is the main clock source:
+  // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
+  // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
+
+  // NOTE: by default, this implementation doesn't perform thorough checks on the
+  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+
+
+#ifdef AVR32SFW_INPUT_CHECK
+  // Verify that fCPU >= fPBx
+  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
+    return(-1);
+#endif
+
+  if(PCL_MC_RCSYS == param->main_clk_src)
+  {
+    return(pcl_configure_clocks_rcsys(param));
+  }
+  else if(PCL_MC_RC120M == param->main_clk_src)
+  {
+    return(pcl_configure_clocks_rc120m(param));
+  }
+  else if(PCL_MC_OSC0 == param->main_clk_src)
+  {
+    return(pcl_configure_clocks_osc0(param));
+  }
+  else // PCL_MC_DFLL0 == param->main_clk_src
+  {
+    return(pcl_configure_clocks_dfll0(param));
+  }
+}
+
+static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
+{
+  //#
+  //# Set the Synchronous clock division ratio for each clock domain
+  //#
+  pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
+
+  //#
+  //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
+  //#
+#if UC3L
+    flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
+#elif UC3C
+    flashc_set_flash_waitstate_and_readmode(param->cpu_f);
+#endif
+
+
+  //#
+  //# Switch the main clock source to the selected clock.
+  //#
+  pm_set_mclk_source(main_clk_src);
+
+  return PASS;
+}
+
+#endif // UC3L device-specific implementation
+
+//! UC3C Device-specific implementation
+#if UC3C
+static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
+{
+  #define PM_MAX_MUL                         ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
+  #define AVR32_PM_PBA_MAX_FREQ              66000000
+  #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ   240000000
+  #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ   160000000
+
+    // Implementation for  UC3C parts.
+        // Supported frequencies:
+        // Fosc0 mul div PLL div2_en cpu_f pba_f   Comment
+        //  12   15   1  192     1     12    12
+        //  12    9   3   40     1     20    20    PLL out of spec
+        //  12   15   1  192     1     24    12
+        //  12    9   1  120     1     30    15
+        //  12    9   3   40     0     40    20    PLL out of spec
+        //  12   15   1  192     1     48    12
+        //  12   15   1  192     1     48    24
+        //  12    8   1  108     1     54    27
+        //  12    9   1  120     1     60    15
+        //  12    9   1  120     1     60    30
+        //  12   10   1  132     1     66    16.5
+        //
+        unsigned long in_cpu_f  = param->cpu_f;
+        unsigned long in_osc0_f = param->osc0_f;
+        unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
+        unsigned long pll_freq, rest;
+        Bool b_div2_pba, b_div2_cpu;
+
+        // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
+        scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
+        // Enable the OSC0
+        scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
+        // Set the main clock source as being OSC0.
+        pm_set_mclk_source(PM_CLK_SRC_OSC0);
+
+        // Start with CPU freq config
+        if (in_cpu_f == in_osc0_f)
+        {
+          param->cpu_f = in_osc0_f;
+          param->pba_f = in_osc0_f;
+          return PASS;
+        }
+        else if (in_cpu_f < in_osc0_f)
+        {
+          // TBD
+        }
+
+        rest = in_cpu_f % in_osc0_f;
+
+        for (div = 1; div < 32; div++)
+        {
+          if ((div * rest) % in_osc0_f == 0)
+            break;
+        }
+        if (div == 32)
+          return FAIL;
+
+        mul = (in_cpu_f * div) / in_osc0_f;
+
+        if (mul > PM_MAX_MUL)
+          return FAIL;
+
+        // export 2power from PLL div to div2_cpu
+        while (!(div % 2))
+        {
+          div /= 2;
+          div2_cpu++;
+        }
+
+        // Here we know the mul and div parameter of the PLL config.
+        // . Check out if the PLL has a valid in_cpu_f.
+        // . Try to have for the PLL frequency (VCO output) the highest possible value
+        //   to reduce jitter.
+        while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
+        {
+          if (2 * mul > PM_MAX_MUL)
+            break;
+          mul *= 2;
+          div2_cpu++;
+        }
+
+        if (div2_cpu != 0)
+        {
+          div2_cpu--;
+          div2_en = 1;
+        }
+
+        pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
+
+        // Update real CPU Frequency
+        param->cpu_f = pll_freq / (1 << div2_cpu);
+        mul--;
+
+        scif_pll_opt_t opt;
+
+        opt.osc = SCIF_OSC0,     // Sel Osc0 or Osc1
+        opt.lockcount = 16,      // lockcount in main clock for the PLL wait lock
+        opt.div = div,             // DIV=1 in the formula
+        opt.mul = mul,             // MUL=7 in the formula
+        opt.pll_div2 = div2_en,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
+        opt.pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
+        opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
+
+
+        scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
+
+        /* Enable PLL0 */
+        scif_pll_enable(SCIF_PLL0);
+
+        /* Wait for PLL0 locked */
+        scif_wait_for_pll_locked(SCIF_PLL0) ;
+
+        rest = pll_freq;
+        while (rest > AVR32_PM_PBA_MAX_FREQ ||
+               rest != param->pba_f)
+        {
+          div2_pba++;
+          rest = pll_freq / (1 << div2_pba);
+          if (rest < param->pba_f)
+            break;
+        }
+
+        // Update real PBA Frequency
+        param->pba_f = pll_freq / (1 << div2_pba);
+
+
+        if (div2_cpu)
+        {
+          b_div2_cpu = TRUE;
+          div2_cpu--;
+        }
+        else
+          b_div2_cpu = FALSE;
+
+        if (div2_pba)
+        {
+          b_div2_pba = TRUE;
+          div2_pba--;
+        }
+        else
+          b_div2_pba = FALSE;
+
+        if (b_div2_cpu == TRUE )
+        {
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
+        }
+        if (b_div2_pba == TRUE )
+        {
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
+          pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
+        }
+
+        // Set Flashc Wait State
+        flashc_set_flash_waitstate_and_readmode(param->cpu_f);
+
+        // Set the main clock source as being PLL0.
+        pm_set_mclk_source(PM_CLK_SRC_PLL0);
+
+        return PASS;
+}
+#endif // UC3C device-specific implementation
+
+long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
+{
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Implementation for UC3A, UC3A3, UC3B parts.
+  if(PCL_OSC0 == osc)
+  {
+    // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
+    // enable the OSC0, set the main clock source as being OSC0.
+    pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
+  }
+  else
+  {
+    return PCL_NOT_SUPPORTED;
+  }
+#else
+// Implementation for UC3C, UC3L parts.
+  #if AVR32_PM_VERSION_RESETVALUE < 0x400
+    return PCL_NOT_SUPPORTED;
+  #else
+  if(PCL_OSC0 == osc)
+  {
+    // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
+    scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
+    // Enable the OSC0
+    scif_enable_osc(SCIF_OSC0, startup, true);
+    // Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
+#if UC3L
+    flashcdw_set_flash_waitstate_and_readmode(fcrystal);
+#elif UC3C
+    flashc_set_flash_waitstate_and_readmode(fcrystal);
+#endif
+    // Set the main clock source as being OSC0.
+    pm_set_mclk_source(PM_CLK_SRC_OSC0);
+  }
+  else
+  {
+    return PCL_NOT_SUPPORTED;
+  }
+  #endif
+#endif
+  return PASS;
+}
+
+long int pcl_configure_usb_clock(void)
+{
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Implementation for UC3A, UC3A3, UC3B parts.
+  pm_configure_usb_clock();
+  return PASS;
+#else
+  #ifdef AVR32_PM_410_H_INCLUDED
+    const scif_pll_opt_t opt = {
+              .osc = SCIF_OSC0,     // Sel Osc0 or Osc1
+              .lockcount = 16,      // lockcount in main clock for the PLL wait lock
+              .div = 1,             // DIV=1 in the formula
+              .mul = 5,             // MUL=7 in the formula
+              .pll_div2 = 1,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
+              .pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
+              .pll_freq = 1,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
+    };
+
+    /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
+    scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
+
+    /* Enable PLL1 */
+    scif_pll_enable(SCIF_PLL1);
+
+    /* Wait for PLL1 locked */
+    scif_wait_for_pll_locked(SCIF_PLL1) ;
+
+  // Implementation for UC3C parts.
+    // Setup the generic clock for USB
+    scif_gc_setup(AVR32_SCIF_GCLK_USB,
+                  SCIF_GCCTRL_PLL1,
+                  AVR32_SCIF_GC_NO_DIV_CLOCK,
+                  0);
+    // Now enable the generic clock
+    scif_gc_enable(AVR32_SCIF_GCLK_USB);
+    return PASS;
+  #else
+      return PCL_NOT_SUPPORTED;
+  #endif
+#endif
+}
+
+
+#if UC3L
+#else
+void pcl_write_gplp(unsigned long gplp, unsigned long value)
+{
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Implementation for UC3A, UC3A3, UC3B parts.
+  pm_write_gplp(&AVR32_PM,gplp,value);
+#else
+  scif_write_gplp(gplp,value);
+#endif
+}
+
+unsigned long pcl_read_gplp(unsigned long gplp)
+{
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Implementation for UC3A, UC3A3, UC3B parts.
+  return pm_read_gplp(&AVR32_PM,gplp);
+#else
+  return scif_read_gplp(gplp);
+#endif
+}
+#endif

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/PM/power_clocks_lib.h

@@ -0,0 +1,379 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief High-level library abstracting features such as oscillators/pll/dfll
+ *        configuration, clock configuration, System-sensible parameters
+ *        configuration, buses clocks configuration, sleep mode, reset.
+ *
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _POWER_CLOCKS_LIB_H_
+#define _POWER_CLOCKS_LIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <avr32/io.h>
+#include "compiler.h"
+
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Support for UC3A, UC3A3, UC3B parts.
+  #include "pm.h"
+#else
+//! Device-specific data
+#if UC3L 
+  #include "pm_uc3l.h"
+  #include "scif_uc3l.h"
+  #include "flashcdw.h"
+#elif UC3C
+  #include "pm_uc3c.h"
+  #include "scif_uc3c.h"
+  #include "flashc.h"
+#endif
+#endif
+
+/*! \name Clocks Management
+ */
+//! @{
+
+//! The different oscillators
+typedef enum
+{
+  PCL_OSC0  = 0,
+  PCL_OSC1  = 1
+} pcl_osc_t;
+
+//! The different DFLLs
+typedef enum
+{
+  PCL_DFLL0  = 0,
+  PCL_DFLL1  = 1
+} pcl_dfll_t;
+
+//! Possible Main Clock Sources
+typedef enum
+{
+  PCL_MC_RCSYS,      // Default main clock source, supported by all (aka Slow Clock)
+  PCL_MC_OSC0,       // Supported by all
+  PCL_MC_OSC1,       // Supported by UC3C only
+  PCL_MC_OSC0_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference)
+  PCL_MC_OSC1_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference)
+  PCL_MC_OSC0_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC0 as reference)
+  PCL_MC_OSC1_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC1 as reference)
+  PCL_MC_DFLL0,      // Supported by UC3L
+  PCL_MC_DFLL1,      // Not supported yet
+  PCL_MC_RC120M,     // Supported by UC3L, UC3C
+  PCL_MC_RC8M,       // Supported by UC3C
+  PCL_MC_CRIPOSC     // Supported by UC3C
+} pcl_mainclk_t;
+
+//! Input and output parameters to configure clocks with pcl_configure_clocks().
+// NOTE: regarding the frequency settings, always abide by the datasheet rules and min & max supported frequencies.
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Support for UC3A, UC3A3, UC3B parts.
+#define pcl_freq_param_t  pm_freq_param_t // See pm.h
+#else
+// Support for UC3C, UC3L parts.
+typedef struct
+{
+  //! Main clock source selection (input argument).
+  pcl_mainclk_t main_clk_src;
+
+  //! Target CPU frequency (input/output argument).
+  unsigned long cpu_f;
+
+  //! Target PBA frequency (input/output argument).
+  unsigned long pba_f;
+
+  //! Target PBB frequency (input/output argument).
+  unsigned long pbb_f;
+
+  //! Target PBC frequency (input/output argument).
+  unsigned long pbc_f;
+
+  //! Oscillator 0's external crystal(or external clock) frequency (board dependant) (input argument).
+  unsigned long osc0_f;
+
+  //! Oscillator 0's external crystal(or external clock) startup time: AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC (input argument).
+  unsigned long osc0_startup;
+
+  //! DFLL target frequency (input/output argument) (NOTE: the bigger, the most stable the frequency)
+  unsigned long dfll_f;
+  
+  //! Other parameters that might be necessary depending on the device (implementation-dependent).
+  // For the UC3L DFLL setup, this parameter should be pointing to a structure of
+  // type (scif_gclk_opt_t *).
+  void *pextra_params;
+} pcl_freq_param_t;
+#endif
+
+//! Define "not supported" for the lib.
+#define PCL_NOT_SUPPORTED (-10000)
+
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks
+ *
+ * This function needs some parameters stored in a pcl_freq_param_t structure:
+ *  - main_clk_src is the id of the main clock source to use,
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies,
+ *  - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
+ *  - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
+ *  - dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll.
+ *
+ * The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
+ *
+ * \note: since it is dynamically computing the appropriate field values of the
+ * configuration registers from the parameters structure, this function is not
+ * optimal in terms of code size. For a code size optimal solution, it is better
+ * to create a new function from pcl_configure_clocks() and modify it to use
+ * preprocessor computation from pre-defined target frequencies.
+ *
+ * \param param    pointer on the configuration structure.
+ *
+ * \retval 0   Success.
+ * \retval <0  The configuration cannot be performed.
+ */
+extern long int pcl_configure_clocks(pcl_freq_param_t *param);
+
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.
+ *
+ * This function needs some parameters stored in a pcl_freq_param_t structure:
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies
+ *
+ * Supported main clock sources: PCL_MC_RCSYS
+ *
+ * Supported synchronous clocks frequencies:
+ * 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
+ *
+ * \note: by default, this implementation doesn't perform thorough checks on the
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+ *
+ * \note: since it is dynamically computing the appropriate field values of the
+ * configuration registers from the parameters structure, this function is not
+ * optimal in terms of code size. For a code size optimal solution, it is better
+ * to create a new function from pcl_configure_clocks_rcsys() and modify it to use
+ * preprocessor computation from pre-defined target frequencies.
+ *
+ * \param param    pointer on the configuration structure.
+ *
+ * \retval 0   Success.
+ * \retval <0  The configuration cannot be performed.
+ */
+extern long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param);
+
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.
+ *
+ * This function needs some parameters stored in a pcl_freq_param_t structure:
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies
+ *
+ * Supported main clock sources: PCL_MC_RC120M
+ *
+ * Supported synchronous clocks frequencies:
+ * 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
+ *
+ * \note: by default, this implementation doesn't perform thorough checks on the
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+ *
+ * \note: since it is dynamically computing the appropriate field values of the
+ * configuration registers from the parameters structure, this function is not
+ * optimal in terms of code size. For a code size optimal solution, it is better
+ * to create a new function from pcl_configure_clocks_rc120m() and modify it to
+ * use preprocessor computation from pre-defined target frequencies.
+ *
+ * \param param    pointer on the configuration structure.
+ *
+ * \retval 0   Success.
+ * \retval <0  The configuration cannot be performed.
+ */
+extern long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param);
+
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock
+ *
+ * This function needs some parameters stored in a pcl_freq_param_t structure:
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies,
+ *  - osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
+ *  - osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
+ *
+ * Supported main clock sources: PCL_MC_OSC0
+ *
+ * Supported synchronous clocks frequencies:
+ * (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
+ * 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
+ *
+ * \note: by default, this implementation doesn't perform thorough checks on the
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+ *
+ * \note: since it is dynamically computing the appropriate field values of the
+ * configuration registers from the parameters structure, this function is not
+ * optimal in terms of code size. For a code size optimal solution, it is better
+ * to create a new function from pcl_configure_clocks_osc0() and modify it to use
+ * preprocessor computation from pre-defined target frequencies.
+ *
+ * \param param    pointer on the configuration structure.
+ *
+ * \retval 0   Success.
+ * \retval <0  The configuration cannot be performed.
+ */
+extern long int pcl_configure_clocks_osc0(pcl_freq_param_t *param);
+
+/*! \brief Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock
+ *
+ * This function needs some parameters stored in a pcl_freq_param_t structure:
+ *  - cpu_f and pba_f and pbb_f are the wanted frequencies,
+ *  - dfll_f is the target DFLL frequency to set-up
+ *
+ * \note: when the DFLL0 is to be used as main source clock for the synchronous clocks,
+ *  the target frequency of the DFLL should be chosen to be as high as possible
+ *  within the specification range (for stability reasons); the target cpu and pbx
+ *  frequencies will then be reached by appropriate division ratio.
+ *
+ * Supported main clock sources: PCL_MC_DFLL0
+ *
+ * Supported synchronous clocks frequencies:
+ * (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
+ * 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
+ *
+ * \note: by default, this implementation doesn't perform thorough checks on the
+ *        input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
+ *
+ * \note: since it is dynamically computing the appropriate field values of the
+ * configuration registers from the parameters structure, this function is not
+ * optimal in terms of code size. For a code size optimal solution, it is better
+ * to create a new function from pcl_configure_clocks_dfll0() and modify it to
+ * use preprocessor computation from pre-defined target frequencies.
+ *
+ * \param param    pointer on the configuration structure.
+ *
+ * \retval 0   Success.
+ * \retval <0  The configuration cannot be performed.
+ */
+extern long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param);
+
+/*! \brief Switch the main clock source to Osc0 configured in crystal mode
+ *
+ * \param osc The oscillator to enable and switch to.
+ * \param fcrystal Oscillator external crystal frequency (Hz)
+ * \param startup Oscillator startup time.
+ *
+ * \return Status.
+ *   \retval 0  Success.
+ *   \retval <0 An error occured.
+ */
+extern long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup);
+
+/*! \brief Enable the clock of a module.
+ *
+ * \param module The module to clock (use one of the defines in the part-specific
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"
+ * or look in the module section).
+ *
+ * \return Status.
+ *   \retval 0  Success.
+ *   \retval <0 An error occured.
+ */
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Implementation for UC3A, UC3A3, UC3B parts.
+#define pcl_enable_module(module) pm_enable_module(&AVR32_PM, module)
+#else
+// Implementation for UC3C, UC3L parts.
+#define pcl_enable_module(module) pm_enable_module(module)
+#endif
+
+/*! \brief Disable the clock of a module.
+ *
+ * \param module The module to shut down (use one of the defines in the part-specific
+ * header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the
+ * clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks"
+ * or look in the module section).
+ *
+ * \return Status.
+ *   \retval 0  Success.
+ *   \retval <0 An error occured.
+ */
+#ifndef AVR32_PM_VERSION_RESETVALUE
+// Implementation for UC3A, UC3A3, UC3B parts.
+#define pcl_disable_module(module)  pm_disable_module(&AVR32_PM, module)
+#else
+// Implementation for UC3C, UC3L parts.
+#define pcl_disable_module(module)  pm_disable_module(module)
+#endif
+
+/*! \brief Configure the USB Clock
+ *
+ *
+ * \return Status.
+ *   \retval 0  Success.
+ *   \retval <0 An error occured.
+ */
+extern long int pcl_configure_usb_clock(void);
+
+//! @}
+
+/*! \name Power Management
+ */
+//! @{
+/*!
+ * \brief Read the content of the GPLP registers
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
+ *
+ * \return The content of the chosen GPLP register.
+ */
+extern unsigned long pcl_read_gplp(unsigned long gplp);
+
+
+/*!
+ * \brief Write into the GPLP registers
+ * \param gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
+ * \param value Value to write
+ */
+extern void pcl_write_gplp(unsigned long gplp, unsigned long value);
+
+//! @}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // _POWER_CLOCKS_LIB_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/RTC/rtc.c

@@ -0,0 +1,213 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief RTC driver for AVR32 UC3.
+ *
+ * AVR32 Real Time Counter driver module.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an RTC and a PM module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+#include "pm.h"
+#include "rtc.h"
+
+
+int rtc_is_busy(volatile avr32_rtc_t *rtc)
+{
+  return (rtc->ctrl & AVR32_RTC_CTRL_BUSY_MASK) != 0;
+}
+
+
+int rtc_init(volatile avr32_rtc_t *rtc, unsigned char osc_type, unsigned char psel)
+{
+  // If exit, it means that the configuration has not been set correctly
+  if (osc_type > (1 << AVR32_RTC_CTRL_CLK32_SIZE) - 1 ||
+      psel > (1 << AVR32_RTC_CTRL_PSEL_SIZE) - 1)
+    return 0;
+
+  // If we use the 32-kHz oscillator, we have to enable it first
+  if (osc_type == RTC_OSC_32KHZ)
+  {
+    // Select the 32-kHz oscillator crystal
+    pm_enable_osc32_crystal(&AVR32_PM);
+    // Enable the 32-kHz clock
+    pm_enable_clk32_no_wait(&AVR32_PM, AVR32_PM_OSCCTRL32_STARTUP_0_RCOSC);
+  }
+
+  // Wait until the rtc CTRL register is up-to-date
+  while (rtc_is_busy(rtc));
+
+  // Set the new RTC configuration
+  rtc->ctrl = osc_type << AVR32_RTC_CTRL_CLK32_OFFSET |
+              psel << AVR32_RTC_CTRL_PSEL_OFFSET |
+              AVR32_RTC_CTRL_CLKEN_MASK;
+
+  // Wait until write is done
+  while (rtc_is_busy(rtc));
+
+  // Set the counter value to 0
+  rtc_set_value(rtc, 0x00000000);
+  // Set the top value to 0xFFFFFFFF
+  rtc_set_top_value(rtc, 0xFFFFFFFF);
+
+  return 1;
+}
+
+
+void rtc_set_value(volatile avr32_rtc_t *rtc, unsigned long val)
+{
+  // Wait until we can write into the VAL register
+  while (rtc_is_busy(rtc));
+  // Set the new val value
+  rtc->val = val;
+  // Wait until write is done
+  while (rtc_is_busy(rtc));
+}
+
+
+unsigned long rtc_get_value(volatile avr32_rtc_t *rtc)
+{
+  return rtc->val;
+}
+
+
+void rtc_enable_wake_up(volatile avr32_rtc_t *rtc)
+{
+  // Wait until the rtc CTRL register is up-to-date
+  while (rtc_is_busy(rtc));
+  // Enable the wake up of the RTC
+  rtc->ctrl |= AVR32_RTC_CTRL_WAKE_EN_MASK;
+  // Wait until write is done
+  while (rtc_is_busy(rtc));
+}
+
+
+void rtc_disable_wake_up(volatile avr32_rtc_t *rtc)
+{
+  // Wait until the rtc CTRL register is up-to-date
+  while (rtc_is_busy(rtc));
+  // Disable the wake up of the RTC
+  rtc->ctrl &= ~AVR32_RTC_CTRL_WAKE_EN_MASK;
+  // Wait until write is done
+  while (rtc_is_busy(rtc));
+}
+
+
+void rtc_enable(volatile avr32_rtc_t *rtc)
+{
+  // Wait until the rtc CTRL register is up-to-date
+  while (rtc_is_busy(rtc));
+  // Enable the RTC
+  rtc->ctrl |= AVR32_RTC_CTRL_EN_MASK;
+  // Wait until write is done
+  while (rtc_is_busy(rtc));
+}
+
+
+void rtc_disable(volatile avr32_rtc_t *rtc)
+{
+  // Wait until the rtc CTRL register is up-to-date
+  while (rtc_is_busy(rtc));
+  // Disable the RTC
+  rtc->ctrl &= ~AVR32_RTC_CTRL_EN_MASK;
+  // Wait until write is done
+  while (rtc_is_busy(rtc));
+}
+
+
+void rtc_enable_interrupt(volatile avr32_rtc_t *rtc)
+{
+  rtc->ier = AVR32_RTC_IER_TOPI_MASK;
+}
+
+
+void rtc_disable_interrupt(volatile avr32_rtc_t *rtc)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  rtc->idr = AVR32_RTC_IDR_TOPI_MASK;
+  rtc->imr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void rtc_clear_interrupt(volatile avr32_rtc_t *rtc)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  rtc->icr = AVR32_RTC_ICR_TOPI_MASK;
+  rtc->isr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+}
+
+
+void rtc_set_top_value(volatile avr32_rtc_t *rtc, unsigned long top)
+{
+  // Wait until we can write into the VAL register
+  while (rtc_is_busy(rtc));
+  // Set the new val value
+  rtc->top = top;
+  // Wait until write is done
+  while (rtc_is_busy(rtc));
+}
+
+
+unsigned long rtc_get_top_value(volatile avr32_rtc_t *rtc)
+{
+  return rtc->top;
+}
+
+
+int rtc_interrupt_enabled(volatile avr32_rtc_t *rtc)
+{
+  return (rtc->imr & AVR32_RTC_IMR_TOPI_MASK) != 0;
+}
+
+
+int rtc_is_interrupt(volatile avr32_rtc_t *rtc)
+{
+  return (rtc->isr & AVR32_RTC_ISR_TOPI_MASK) != 0;
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/RTC/rtc.h

@@ -0,0 +1,191 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief RTC driver for AVR32 UC3.
+ *
+ * AVR32 Real Time Counter driver module.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an RTC and a PM module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _RTC_H_
+#define _RTC_H_
+
+#include "compiler.h"
+#include <avr32/io.h>
+
+
+/*! \name Oscillator Types
+ */
+//! @{
+#define RTC_OSC_32KHZ    1
+#define RTC_OSC_RC       0
+//! @}
+
+/*! \name Predefined PSEL Values
+ */
+//! @{
+
+//! The PSEL value to set the RTC source clock (after the prescaler) to 1 Hz,
+//! when using an external 32-kHz crystal.
+#define RTC_PSEL_32KHZ_1HZ    14
+
+//! The PSEL value to set the RTC source clock (after the prescaler) to 1.76 Hz,
+//! when using the internal RC oscillator (~ 115 kHz).
+#define RTC_PSEL_RC_1_76HZ    15
+
+//! @}
+
+
+/*!
+ * \brief This function will initialise the RTC module.
+ *        If you use the 32 KHz oscillator, it will enable this module.
+ *        This function also set the top value of the RTC to 0xFFFFFFFF
+ *        and the value to 0.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \param osc_type The oscillator you want to use. If you need a better
+ *        accuracy, use the 32 KHz oscillator (i.e. RTC_OSC_32KHZ).
+ * \param psel The preselector value for the corresponding oscillator (4-bits).
+ *        To obtain this value, you can use this formula:
+ *        psel = log(Fosc/Frtc)/log(2)-1, where Fosc is the frequency of the
+ *        oscillator you are using (32 KHz or 115 KHz) and Frtc the frequency
+ *        desired.
+ * \return 1 if the initialisation succeds otherwize it will return 0.
+ */
+extern int rtc_init(volatile avr32_rtc_t *rtc, unsigned char osc_type, unsigned char psel);
+
+/*!
+ * \brief Enable the RTC.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ */
+extern void rtc_enable(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Disable the RTC.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ */
+extern void rtc_disable(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Enable the wake up feature of the RTC.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ */
+extern void rtc_enable_wake_up(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Disable the wake up feature of the RTC.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ */
+extern void rtc_disable_wake_up(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Enable the interrupt feature of the RTC.
+ *        An interrupt is raised when the value of the RTC
+ *        is equal to its top value.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ */
+extern void rtc_enable_interrupt(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Disable the interrupt feature of the RTC.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ */
+extern void rtc_disable_interrupt(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Clear the interrupt flag.
+ *        Call this function once you handled the interrupt.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ */
+extern void rtc_clear_interrupt(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Get the status of interrupts.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \return 1 if the interrupts are enabled otherwize it returns 0.
+ */
+extern int rtc_interrupt_enabled(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief Check if an interrupt is raised.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \return 1 if an interrupt is currently raised otherwize it returns 0.
+ */
+extern int rtc_is_interrupt(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief This function sets the RTC current top value.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \param top The top value you want to store.
+ */
+extern void rtc_set_top_value(volatile avr32_rtc_t *rtc, unsigned long top);
+
+/*!
+ * \brief This function returns the RTC current top value.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \return The RTC current top value.
+ */
+extern unsigned long rtc_get_top_value(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief This function checks if the RTC is busy or not.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \return 1 if the RTC is busy otherwize it will return 0.
+ */
+extern int rtc_is_busy(volatile avr32_rtc_t *rtc);
+
+/*!
+ * \brief This function sets the RTC current value.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \param val The value you want to store.
+ */
+extern void rtc_set_value(volatile avr32_rtc_t *rtc, unsigned long val);
+
+/*!
+ * \brief This function returns the RTC current value.
+ * \param rtc Base address of the RTC (i.e. &AVR32_RTC).
+ * \return The RTC current value.
+ */
+extern unsigned long rtc_get_value(volatile avr32_rtc_t *rtc);
+
+
+#endif  // _RTC_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.c

@@ -0,0 +1,443 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief SPI driver for AVR32 UC3.
+ *
+ * This file defines a useful set of functions for the SPI interface on AVR32
+ * devices.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include "spi.h"
+
+#ifdef FREERTOS_USED
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+
+#endif
+
+
+/*! \name SPI Writable Bit-Field Registers
+ */
+//! @{
+
+typedef union
+{
+  unsigned long                 cr;
+  avr32_spi_cr_t                CR;
+} u_avr32_spi_cr_t;
+
+typedef union
+{
+  unsigned long                 mr;
+  avr32_spi_mr_t                MR;
+} u_avr32_spi_mr_t;
+
+typedef union
+{
+  unsigned long                 tdr;
+  avr32_spi_tdr_t               TDR;
+} u_avr32_spi_tdr_t;
+
+typedef union
+{
+  unsigned long                 ier;
+  avr32_spi_ier_t               IER;
+} u_avr32_spi_ier_t;
+
+typedef union
+{
+  unsigned long                 idr;
+  avr32_spi_idr_t               IDR;
+} u_avr32_spi_idr_t;
+
+typedef union
+{
+  unsigned long                 csr;
+  avr32_spi_csr0_t              CSR;
+} u_avr32_spi_csr_t;
+
+//! @}
+
+
+#ifdef FREERTOS_USED
+
+//! The SPI mutex.
+static xSemaphoreHandle xSPIMutex;
+
+#endif
+
+
+/*! \brief Calculates the baudrate divider.
+ *
+ * \param options Pointer to a structure containing initialization options for
+ *                an SPI channel.
+ * \param pba_hz  SPI module input clock frequency (PBA clock, Hz).
+ *
+ * \return Divider or error code.
+ *   \retval >=0  Success.
+ *   \retval  <0  Error.
+ */
+static int getBaudDiv(const spi_options_t *options, unsigned int pba_hz)
+{
+  int baudDiv = (pba_hz + options->baudrate / 2) / options->baudrate;
+
+  if (baudDiv <= 0 || baudDiv > 255) {
+    return -1;
+  }
+
+  return baudDiv;
+}
+
+
+void spi_reset(volatile avr32_spi_t *spi)
+{
+  spi->cr = AVR32_SPI_CR_SWRST_MASK;
+}
+
+
+spi_status_t spi_initSlave(volatile avr32_spi_t *spi,
+                           unsigned char bits,
+                           unsigned char spi_mode)
+{
+  if (spi_mode > 3 ||
+      bits < 8 || bits > 16) {
+    return SPI_ERROR_ARGUMENT;
+  }
+
+  // Reset.
+  spi->cr = AVR32_SPI_CR_SWRST_MASK;
+
+  // Will use CSR0 offsets; these are the same for CSR0 to CSR3.
+  spi->csr0 = ((spi_mode >> 1) << AVR32_SPI_CSR0_CPOL_OFFSET) |
+              (((spi_mode & 0x1) ^ 0x1) << AVR32_SPI_CSR0_NCPHA_OFFSET) |
+              ((bits - 8) << AVR32_SPI_CSR0_BITS_OFFSET);
+
+  return SPI_OK;
+}
+
+
+spi_status_t spi_initTest(volatile avr32_spi_t *spi)
+{
+  // Reset.
+  spi->cr = AVR32_SPI_CR_SWRST_MASK;
+  spi->mr |= AVR32_SPI_MR_MSTR_MASK | // Master Mode.
+             AVR32_SPI_MR_LLB_MASK;   // Local Loopback.
+
+  return SPI_OK;
+}
+
+
+spi_status_t spi_initMaster(volatile avr32_spi_t *spi, const spi_options_t *options)
+{
+  u_avr32_spi_mr_t u_avr32_spi_mr;
+
+  if (options->modfdis > 1) {
+    return SPI_ERROR_ARGUMENT;
+  }
+
+  // Reset.
+  spi->cr = AVR32_SPI_CR_SWRST_MASK;
+
+  // Master Mode.
+  u_avr32_spi_mr.mr = spi->mr;
+  u_avr32_spi_mr.MR.mstr = 1;
+  u_avr32_spi_mr.MR.modfdis = options->modfdis;
+  u_avr32_spi_mr.MR.llb = 0;
+  u_avr32_spi_mr.MR.pcs = (1 << AVR32_SPI_MR_PCS_SIZE) - 1;
+  spi->mr = u_avr32_spi_mr.mr;
+
+  return SPI_OK;
+}
+
+
+spi_status_t spi_selectionMode(volatile avr32_spi_t *spi,
+                               unsigned char variable_ps,
+                               unsigned char pcs_decode,
+                               unsigned char delay)
+{
+  u_avr32_spi_mr_t u_avr32_spi_mr;
+
+  if (variable_ps > 1 ||
+      pcs_decode > 1) {
+    return SPI_ERROR_ARGUMENT;
+  }
+
+  u_avr32_spi_mr.mr = spi->mr;
+  u_avr32_spi_mr.MR.ps = variable_ps;
+  u_avr32_spi_mr.MR.pcsdec = pcs_decode;
+  u_avr32_spi_mr.MR.dlybcs = delay;
+  spi->mr = u_avr32_spi_mr.mr;
+
+  return SPI_OK;
+}
+
+
+spi_status_t spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip)
+{
+#ifdef FREERTOS_USED
+  while (pdFALSE == xSemaphoreTake(xSPIMutex, 20));
+#endif
+
+  // Assert all lines; no peripheral is selected.
+  spi->mr |= AVR32_SPI_MR_PCS_MASK;
+
+  if (spi->mr & AVR32_SPI_MR_PCSDEC_MASK) {
+    // The signal is decoded; allow up to 15 chips.
+    if (chip > 14) {
+      return SPI_ERROR_ARGUMENT;
+    }
+
+    spi->mr &= ~AVR32_SPI_MR_PCS_MASK | (chip << AVR32_SPI_MR_PCS_OFFSET);
+  } else {
+    if (chip > 3) {
+      return SPI_ERROR_ARGUMENT;
+    }
+
+    spi->mr &= ~(1 << (AVR32_SPI_MR_PCS_OFFSET + chip));
+  }
+
+  return SPI_OK;
+}
+
+
+spi_status_t spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip)
+{
+  unsigned int timeout = SPI_TIMEOUT;
+
+  while (!(spi->sr & AVR32_SPI_SR_TXEMPTY_MASK)) {
+    if (!timeout--) {
+      return SPI_ERROR_TIMEOUT;
+    }
+  }
+
+  // Assert all lines; no peripheral is selected.
+  spi->mr |= AVR32_SPI_MR_PCS_MASK;
+
+  // Last transfer, so deassert the current NPCS if CSAAT is set.
+  spi->cr = AVR32_SPI_CR_LASTXFER_MASK;
+
+#ifdef FREERTOS_USED
+  xSemaphoreGive(xSPIMutex);
+#endif
+
+  return SPI_OK;
+}
+
+
+spi_status_t spi_setupChipReg(volatile avr32_spi_t *spi,
+                              const spi_options_t *options,
+                              unsigned int pba_hz)
+{
+  u_avr32_spi_csr_t u_avr32_spi_csr;
+
+  if (options->spi_mode > 3 ||
+      options->stay_act > 1 ||
+      options->bits < 8 || options->bits > 16) {
+    return SPI_ERROR_ARGUMENT;
+  }
+
+  int baudDiv = getBaudDiv(options, pba_hz);
+
+  if (baudDiv < 0) {
+    return SPI_ERROR_ARGUMENT;
+  }
+
+  // Will use CSR0 offsets; these are the same for CSR0 to CSR3.
+  u_avr32_spi_csr.csr = 0;
+  u_avr32_spi_csr.CSR.cpol = options->spi_mode >> 1;
+  u_avr32_spi_csr.CSR.ncpha = (options->spi_mode & 0x1) ^ 0x1;
+  u_avr32_spi_csr.CSR.csaat = options->stay_act;
+  u_avr32_spi_csr.CSR.bits = options->bits - 8;
+  u_avr32_spi_csr.CSR.scbr = baudDiv;
+  u_avr32_spi_csr.CSR.dlybs = options->spck_delay;
+  u_avr32_spi_csr.CSR.dlybct = options->trans_delay;
+
+  switch(options->reg) {
+    case 0:
+      spi->csr0 = u_avr32_spi_csr.csr;
+      break;
+    case 1:
+      spi->csr1 = u_avr32_spi_csr.csr;
+      break;
+    case 2:
+      spi->csr2 = u_avr32_spi_csr.csr;
+      break;
+    case 3:
+      spi->csr3 = u_avr32_spi_csr.csr;
+      break;
+    default:
+      return SPI_ERROR_ARGUMENT;
+  }
+
+#ifdef FREERTOS_USED
+  if (!xSPIMutex)
+  {
+    // Create the SPI mutex.
+    vSemaphoreCreateBinary(xSPIMutex);
+    if (!xSPIMutex)
+    {
+      while(1);
+    }
+  }
+#endif
+
+  return SPI_OK;
+}
+
+
+void spi_enable(volatile avr32_spi_t *spi)
+{
+  spi->cr = AVR32_SPI_CR_SPIEN_MASK;
+}
+
+
+void spi_disable(volatile avr32_spi_t *spi)
+{
+  spi->cr = AVR32_SPI_CR_SPIDIS_MASK;
+}
+
+
+int spi_is_enabled(volatile avr32_spi_t *spi)
+{
+  return (spi->sr & AVR32_SPI_SR_SPIENS_MASK) != 0;
+}
+
+
+inline unsigned char spi_writeRegisterEmptyCheck(volatile avr32_spi_t *spi)
+{
+  return ((spi->sr & AVR32_SPI_SR_TDRE_MASK) != 0);
+}
+
+
+inline spi_status_t spi_write(volatile avr32_spi_t *spi, unsigned short data)
+{
+  unsigned int timeout = SPI_TIMEOUT;
+
+  while (!(spi->sr & AVR32_SPI_SR_TDRE_MASK)) {
+    if (!timeout--) {
+      return SPI_ERROR_TIMEOUT;
+    }
+  }
+
+  spi->tdr = data << AVR32_SPI_TDR_TD_OFFSET;
+
+  return SPI_OK;
+}
+
+
+spi_status_t spi_variableSlaveWrite(volatile avr32_spi_t *spi, unsigned short data,
+                                    unsigned char pcs, unsigned char lastxfer)
+{
+  unsigned int timeout = SPI_TIMEOUT;
+
+  if (pcs > 14 || lastxfer > 1) {
+    return SPI_ERROR_ARGUMENT;
+  }
+
+  while (!(spi->sr & AVR32_SPI_SR_TDRE_MASK)) {
+    if (!timeout--) {
+      return SPI_ERROR_TIMEOUT;
+    }
+  }
+
+  spi->tdr = (data << AVR32_SPI_TDR_TD_OFFSET) |
+             (pcs << AVR32_SPI_TDR_PCS_OFFSET) |
+             (lastxfer << AVR32_SPI_TDR_LASTXFER_OFFSET);
+
+  return SPI_OK;
+}
+
+
+inline unsigned char spi_writeEndCheck(volatile avr32_spi_t *spi)
+{
+  return ((spi->sr & AVR32_SPI_SR_TXEMPTY_MASK) != 0);
+}
+
+
+unsigned char spi_readRegisterFullCheck(volatile avr32_spi_t *spi)
+{
+  return ((spi->sr & AVR32_SPI_SR_RDRF_MASK) != 0);
+}
+
+
+inline spi_status_t spi_read(volatile avr32_spi_t *spi, unsigned short *data)
+{
+  unsigned int timeout = SPI_TIMEOUT;
+
+  while ((spi->sr & (AVR32_SPI_SR_RDRF_MASK | AVR32_SPI_SR_TXEMPTY_MASK)) !=
+         (AVR32_SPI_SR_RDRF_MASK | AVR32_SPI_SR_TXEMPTY_MASK)) {
+    if (!timeout--) {
+      return SPI_ERROR_TIMEOUT;
+    }
+  }
+
+  *data = spi->rdr >> AVR32_SPI_RDR_RD_OFFSET;
+
+  return SPI_OK;
+}
+
+
+unsigned char spi_getStatus(volatile avr32_spi_t *spi)
+{
+  spi_status_t ret = SPI_OK;
+  unsigned long sr = spi->sr;
+
+  if (sr & AVR32_SPI_SR_OVRES_MASK) {
+    ret = SPI_ERROR_OVERRUN;
+  }
+
+  if (sr & AVR32_SPI_SR_MODF_MASK) {
+    ret += SPI_ERROR_MODE_FAULT;
+  }
+
+  if (ret == (SPI_ERROR_OVERRUN + SPI_ERROR_MODE_FAULT)) {
+    return SPI_ERROR_OVERRUN_AND_MODE_FAULT;
+  }
+  else if (ret > 0) {
+    return ret;
+  } else {
+    return SPI_OK;
+  }
+}

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/SPI/spi.h

@@ -0,0 +1,342 @@
+/* This header file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief SPI driver for AVR32 UC3.
+ *
+ * This file defines a useful set of functions for the SPI interface on AVR32
+ * devices.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with an SPI module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#ifndef _SPI_H_
+#define _SPI_H_
+
+#include <avr32/io.h>
+
+
+//! Time-out value (number of attempts).
+#define SPI_TIMEOUT       10000
+
+
+//! Status codes used by the SPI driver.
+typedef enum
+{
+  SPI_ERROR = -1,
+  SPI_OK = 0,
+  SPI_ERROR_TIMEOUT = 1,
+  SPI_ERROR_ARGUMENT,
+  SPI_ERROR_OVERRUN,
+  SPI_ERROR_MODE_FAULT,
+  SPI_ERROR_OVERRUN_AND_MODE_FAULT
+} spi_status_t;
+
+//! Option structure for SPI channels.
+typedef struct
+{
+  //! The SPI channel to set up.
+  unsigned char reg;
+
+  //! Preferred baudrate for the SPI.
+  unsigned int baudrate;
+
+  //! Number of bits in each character (8 to 16).
+  unsigned char bits;
+
+  //! Delay before first clock pulse after selecting slave (in PBA clock periods).
+  unsigned char spck_delay;
+
+  //! Delay between each transfer/character (in PBA clock periods).
+  unsigned char trans_delay;
+
+  //! Sets this chip to stay active after last transfer to it.
+  unsigned char stay_act;
+
+  //! Which SPI mode to use when transmitting.
+  unsigned char spi_mode;
+
+  //! Disables the mode fault detection.
+  //! With this bit cleared, the SPI master mode will disable itself if another
+  //! master tries to address it.
+  unsigned char modfdis;
+} spi_options_t;
+
+
+/*! \brief Resets the SPI controller.
+ *
+ * \param spi Base address of the SPI instance.
+ */
+extern void spi_reset(volatile avr32_spi_t *spi);
+
+/*! \brief Initializes the SPI in slave mode.
+ *
+ * \param spi       Base address of the SPI instance.
+ * \param bits      Number of bits in each transmitted character (8 to 16).
+ * \param spi_mode  Clock polarity and phase.
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed.
+ */
+extern spi_status_t spi_initSlave(volatile avr32_spi_t *spi,
+                                  unsigned char bits,
+                                  unsigned char spi_mode);
+
+/*! \brief Sets up the SPI in a test mode where the transmitter is connected to
+ *         the receiver (local loopback).
+ *
+ * \param spi Base address of the SPI instance.
+ *
+ * \return Status.
+ *   \retval SPI_OK Success.
+ */
+extern spi_status_t spi_initTest(volatile avr32_spi_t *spi);
+
+/*! \brief Initializes the SPI in master mode.
+ *
+ * \param spi     Base address of the SPI instance.
+ * \param options Pointer to a structure containing initialization options.
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed.
+ */
+extern spi_status_t spi_initMaster(volatile avr32_spi_t *spi, const spi_options_t *options);
+
+/*! \brief Sets up how and when the slave chips are selected (master mode only).
+ *
+ * \param spi         Base address of the SPI instance.
+ * \param variable_ps Target slave is selected in transfer register for every
+ *                    character to transmit.
+ * \param pcs_decode  The four chip select lines are decoded externally. Values
+ *                    0 to 14 can be given to \ref spi_selectChip.
+ * \param delay       Delay in PBA periods between chip selects.
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed.
+ */
+extern spi_status_t spi_selectionMode(volatile avr32_spi_t *spi,
+                                      unsigned char variable_ps,
+                                      unsigned char pcs_decode,
+                                      unsigned char delay);
+
+/*! \brief Selects slave chip.
+ *
+ * \param spi   Base address of the SPI instance.
+ * \param chip  Slave chip number (normal: 0 to 3, extarnally decoded signal: 0
+ *              to 14).
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed.
+ */
+extern spi_status_t spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip);
+
+/*! \brief Unselects slave chip.
+ *
+ * \param spi   Base address of the SPI instance.
+ * \param chip  Slave chip number (normal: 0 to 3, extarnally decoded signal: 0
+ *              to 14).
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_TIMEOUT  Time-out.
+ *
+ * \note Will block program execution until time-out occurs if last transmission
+ *       is not complete. Invoke \ref spi_writeEndCheck beforehand if needed.
+ */
+extern spi_status_t spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip);
+
+/*! \brief Sets options for a specific slave chip.
+ *
+ * The baudrate field has to be written before transfer in master mode. Four
+ * similar registers exist, one for each slave. When using encoded slave
+ * addressing, reg=0 sets options for slaves 0 to 3, reg=1 for slaves 4 to 7 and
+ * so on.
+ *
+ * \param spi     Base address of the SPI instance.
+ * \param options Pointer to a structure containing initialization options for
+ *                an SPI channel.
+ * \param pba_hz  SPI module input clock frequency (PBA clock, Hz).
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed.
+ */
+extern spi_status_t spi_setupChipReg(volatile avr32_spi_t *spi,
+                                     const spi_options_t *options,
+                                     unsigned int pba_hz);
+
+/*! \brief Enables the SPI.
+ *
+ * \param spi Base address of the SPI instance.
+ */
+extern void spi_enable(volatile avr32_spi_t *spi);
+
+/*! \brief Disables the SPI.
+ *
+ * Ensures that nothing is transferred while setting up buffers.
+ *
+ * \param spi Base address of the SPI instance.
+ *
+ * \warning This may cause data loss if used on a slave SPI.
+ */
+extern void spi_disable(volatile avr32_spi_t *spi);
+
+/*! \brief Tests if the SPI is enabled.
+ *
+ * \param spi Base address of the SPI instance.
+ *
+ * \return \c 1 if the SPI is enabled, otherwise \c 0.
+ */
+extern int spi_is_enabled(volatile avr32_spi_t *spi);
+
+/*! \brief Checks if there is no data in the transmit register.
+ *
+ * \param spi Base address of the SPI instance.
+ *
+ * \return Status.
+ *   \retval 1  No data in TDR.
+ *   \retval 0  Some data in TDR.
+ */
+extern unsigned char spi_writeRegisterEmptyCheck(volatile avr32_spi_t *spi);
+
+/*! \brief Writes one data word in master fixed peripheral select mode or in
+ *         slave mode.
+ *
+ * \param spi   Base address of the SPI instance.
+ * \param data  The data word to write.
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_TIMEOUT  Time-out.
+ *
+ * \note Will block program execution until time-out occurs if transmitter is
+ *       busy and transmit buffer is full. Invoke
+ *       \ref spi_writeRegisterEmptyCheck beforehand if needed.
+ *
+ * \note Once the data has been written to the transmit buffer, the end of
+ *       transmission is not waited for. Invoke \ref spi_writeEndCheck if
+ *       needed.
+ */
+extern spi_status_t spi_write(volatile avr32_spi_t *spi, unsigned short data);
+
+/*! \brief Selects a slave in master variable peripheral select mode and writes
+ *         one data word to it.
+ *
+ * \param spi       Base address of the SPI instance.
+ * \param data      The data word to write.
+ * \param pcs       Slave selector (bit 0 -> nCS line 0, bit 1 -> nCS line 1,
+ *                  etc.).
+ * \param lastxfer  Boolean indicating whether this is the last data word
+ *                  transfer.
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_TIMEOUT  Time-out.
+ *   \retval SPI_ERROR_ARGUMENT Invalid argument(s) passed.
+ *
+ * \note Will block program execution until time-out occurs if transmitter is
+ *       busy and transmit buffer is full. Invoke
+ *       \ref spi_writeRegisterEmptyCheck beforehand if needed.
+ *
+ * \note Once the data has been written to the transmit buffer, the end of
+ *       transmission is not waited for. Invoke \ref spi_writeEndCheck if
+ *       needed.
+ */
+extern spi_status_t spi_variableSlaveWrite(volatile avr32_spi_t *spi,
+                                           unsigned short data,
+                                           unsigned char pcs,
+                                           unsigned char lastxfer);
+
+/*! \brief Checks if all transmissions are complete.
+ *
+ * \param spi Base address of the SPI instance.
+ *
+ * \return Status.
+ *   \retval 1  All transmissions complete.
+ *   \retval 0  Transmissions not complete.
+ */
+extern unsigned char spi_writeEndCheck(volatile avr32_spi_t *spi);
+
+/*! \brief Checks if there is data in the receive register.
+ *
+ * \param spi Base address of the SPI instance.
+ *
+ * \return Status.
+ *   \retval 1  Some data in RDR.
+ *   \retval 0  No data in RDR.
+ */
+extern unsigned char spi_readRegisterFullCheck(volatile avr32_spi_t *spi);
+
+/*! \brief Reads one data word in master mode or in slave mode.
+ *
+ * \param spi   Base address of the SPI instance.
+ * \param data  Pointer to the location where to store the received data word.
+ *
+ * \return Status.
+ *   \retval SPI_OK             Success.
+ *   \retval SPI_ERROR_TIMEOUT  Time-out.
+ *
+ * \note Will block program execution until time-out occurs if no data is
+ *       received or last transmission is not complete. Invoke
+ *       \ref spi_writeEndCheck or \ref spi_readRegisterFullCheck beforehand if
+ *       needed.
+ */
+extern spi_status_t spi_read(volatile avr32_spi_t *spi, unsigned short *data);
+
+/*! \brief Gets status information from the SPI.
+ *
+ * \param spi Base address of the SPI instance.
+ *
+ * \return Status.
+ *   \retval SPI_OK                           Success.
+ *   \retval SPI_ERROR_OVERRUN                Overrun error.
+ *   \retval SPI_ERROR_MODE_FAULT             Mode fault (SPI addressed as slave
+ *                                            while in master mode).
+ *   \retval SPI_ERROR_OVERRUN_AND_MODE_FAULT Overrun error and mode fault.
+ */
+extern unsigned char spi_getStatus(volatile avr32_spi_t *spi);
+
+
+#endif  // _SPI_H_

hardware/arduino/firmwares/wifishield/wifiHD/src/SOFTWARE_FRAMEWORK/DRIVERS/TC/tc.c

@@ -0,0 +1,314 @@
+/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief TC driver for AVR32 UC3.
+ *
+ * AVR32 Timer/Counter driver module.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a TC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support and FAQ: http://support.atmel.no/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an Atmel
+ * AVR product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+ *
+ */
+
+#include <avr32/io.h>
+#include "compiler.h"
+#include "tc.h"
+
+
+int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  return tc->channel[channel].imr;
+}
+
+
+int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield)
+{
+  Bool global_interrupt_enabled = Is_global_interrupt_enabled();
+
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // Enable the appropriate interrupts.
+  tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET |
+                             bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET |
+                             bitfield->ldras << AVR32_TC_LDRAS_OFFSET |
+                             bitfield->cpcs << AVR32_TC_CPCS_OFFSET |
+                             bitfield->cpbs << AVR32_TC_CPBS_OFFSET |
+                             bitfield->cpas << AVR32_TC_CPAS_OFFSET |
+                             bitfield->lovrs << AVR32_TC_LOVRS_OFFSET |
+                             bitfield->covfs << AVR32_TC_COVFS_OFFSET;
+
+  // Disable the appropriate interrupts.
+  if (global_interrupt_enabled) Disable_global_interrupt();
+  tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET |
+                             (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET |
+                             (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET |
+                             (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET |
+                             (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET |
+                             (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET |
+                             (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET |
+                             (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET;
+  tc->channel[channel].sr;
+  if (global_interrupt_enabled) Enable_global_interrupt();
+
+  return 0;
+}
+
+
+int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE)
+    return TC_INVALID_ARGUMENT;
+
+  // Clear bit-field and set the correct behavior.
+  tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) |
+            (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE));
+
+  return 0;
+}
+
+
+int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt)
+{
+  // Check for valid input.
+  if (opt->channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // MEASURE SIGNALS: Capture operating mode.
+  tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET |
+                                  opt->ldra << AVR32_TC_LDRA_OFFSET |
+                                  0 << AVR32_TC_WAVE_OFFSET |
+                                  opt->cpctrg << AVR32_TC_CPCTRG_OFFSET |
+                                  opt->abetrg << AVR32_TC_ABETRG_OFFSET |
+                                  opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET|
+                                  opt->ldbdis << AVR32_TC_LDBDIS_OFFSET |
+                                  opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET |
+                                  opt->burst << AVR32_TC_BURST_OFFSET |
+                                  opt->clki << AVR32_TC_CLKI_OFFSET |
+                                  opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
+
+  return 0;
+}
+
+
+int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt)
+{
+  // Check for valid input.
+  if (opt->channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // GENERATE SIGNALS: Waveform operating mode.
+  tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET |
+                                  opt->beevt << AVR32_TC_BEEVT_OFFSET |
+                                  opt->bcpc << AVR32_TC_BCPC_OFFSET |
+                                  opt->bcpb << AVR32_TC_BCPB_OFFSET |
+                                  opt->aswtrg << AVR32_TC_ASWTRG_OFFSET |
+                                  opt->aeevt << AVR32_TC_AEEVT_OFFSET |
+                                  opt->acpc << AVR32_TC_ACPC_OFFSET |
+                                  opt->acpa << AVR32_TC_ACPA_OFFSET |
+                                  1 << AVR32_TC_WAVE_OFFSET |
+                                  opt->wavsel << AVR32_TC_WAVSEL_OFFSET |
+                                  opt->enetrg << AVR32_TC_ENETRG_OFFSET |
+                                  opt->eevt << AVR32_TC_EEVT_OFFSET |
+                                  opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET |
+                                  opt->cpcdis << AVR32_TC_CPCDIS_OFFSET |
+                                  opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET |
+                                  opt->burst << AVR32_TC_BURST_OFFSET |
+                                  opt->clki << AVR32_TC_CLKI_OFFSET |
+                                  opt->tcclks << AVR32_TC_TCCLKS_OFFSET;
+
+  return 0;
+}
+
+
+int tc_start(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // Enable, reset and start the selected timer/counter channel.
+  tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK;
+
+  return 0;
+}
+
+
+int tc_stop(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // Disable the selected timer/counter channel.
+  tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK;
+
+  return 0;
+}
+
+
+int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // Reset the selected timer/counter channel.
+  tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK;
+
+  return 0;
+}
+
+
+void tc_sync_trigger(volatile avr32_tc_t *tc)
+{
+  // Reset all channels of the selected timer/counter.
+  tc->bcr = AVR32_TC_BCR_SYNC_MASK;
+}
+
+
+void tc_sync_start(volatile avr32_tc_t *tc)
+{
+  unsigned int i;
+  // Enable the clock for each channel.
+  for(i=0; i<TC_NUMBER_OF_CHANNELS;i++)
+    tc->channel[i].ccr = AVR32_TC_CLKEN_MASK;
+    
+  // Reset all channels of the selected timer/counter.
+  tc->bcr = AVR32_TC_BCR_SYNC_MASK;
+}
+
+
+int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  return tc->channel[channel].sr;
+}
+
+
+int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK);
+}
+
+
+int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK);
+}
+
+
+int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK);
+}
+
+
+int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK);
+}
+
+
+int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // This function is only available in WAVEFORM mode.
+  if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
+    Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value);
+
+  return value;
+}
+
+
+int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // This function is only available in WAVEFORM mode.
+  if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
+    Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value);
+
+  return value;
+}
+
+
+int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value)
+{
+  // Check for valid input.
+  if (channel >= TC_NUMBER_OF_CHANNELS)
+    return TC_INVALID_ARGUMENT;
+
+  // This function is only available in WAVEFORM mode.
+  if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK))
+    Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value);
+
+  return value;
+}