mirror of
https://github.com/esp8266/Arduino.git
synced 2025-07-30 16:24:09 +03:00
[sam] fixing last stupid commit
This commit is contained in:
Thibaut VIARD
@ -6,21 +6,21 @@ SUBMAKE_OPTIONS=--no-builtin-rules --no-builtin-variables
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# Rules
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#-------------------------------------------------------------------------------
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# libchip_sam3s4_gcc_rel.a
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all: libchip_sam3s4_gcc_dbg.a
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# libchip_sam3s4c_gcc_rel.a
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all: libchip_sam3s4c_gcc_dbg.a
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libchip_sam3s4_gcc_dbg.a:
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libchip_sam3s4c_gcc_dbg.a:
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@echo --- Making $@
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@$(MAKE) CHIP=sam3s4 DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
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@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk
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libchip_sam3s4_gcc_rel.a:
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libchip_sam3s4c_gcc_rel.a:
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@echo --- Making $@
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@$(MAKE) CHIP=sam3s4 $(SUBMAKE_OPTIONS) -f sam3.mk
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@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk
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.PHONY: clean
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clean:
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@echo --- Cleaning sam3s4 release and debug
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@$(MAKE) CHIP=sam3s4 $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@$(MAKE) CHIP=sam3s4 DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@echo --- Cleaning sam3s4c release and debug
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@$(MAKE) CHIP=__SAM3S4C__ $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@$(MAKE) CHIP=__SAM3S4C__ DEBUG=1 $(SUBMAKE_OPTIONS) -f sam3.mk $@
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@ -9,6 +9,9 @@ ifeq ($(CHIP),)
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$(error CHIP not defined)
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endif
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#CHIP_NAME=$(subst __,,$(CHIP))
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#CHIP_NAME=$(subst __,,$(call lc,$(CHIP)))
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#-------------------------------------------------------------------------------
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# Path
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#-------------------------------------------------------------------------------
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@ -18,22 +21,43 @@ OUTPUT_BIN = ../lib
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# Libraries
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PROJECT_BASE_PATH = ..
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CMSIS_BASE_PATH = $(PROJECT_BASE_PATH)/../CMSIS/CM3/CoreSupport
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CMSIS_BASE_PATH = $(PROJECT_BASE_PATH)/../CMSIS/Include
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ifeq ($(CHIP), __SAM3S4C__)
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CHIP_NAME=sam3s4c
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CHIP_SERIE=sam3s
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else ifeq ($(CHIP), __SAM3U4E__)
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CHIP_NAME=sam3u4e
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CHIP_SERIE=sam3u
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else ifeq ($(CHIP), __SAM3N4C__)
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CHIP_NAME=sam3n4c
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CHIP_SERIE=sam3n
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else ifeq ($(CHIP), __SAM3X8H__)
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CHIP_NAME=sam3x8h
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CHIP_SERIE=sam3xa
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else
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endif
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CMSIS_CHIP_PATH=$(PROJECT_BASE_PATH)/../cmsis/$(CHIP_SERIE)
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#-------------------------------------------------------------------------------
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# Files
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#-------------------------------------------------------------------------------
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vpath %.h $(PROJECT_BASE_PATH)/include
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vpath %.c $(PROJECT_BASE_PATH)/source $(CMSIS_BASE_PATH)
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vpath %.s $(PROJECT_BASE_PATH)/source $(CMSIS_BASE_PATH)
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vpath %.h $(PROJECT_BASE_PATH)/include $(PROJECT_BASE_PATH)/../cmsis/$(CHIP_SERIE)/include
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vpath %.c $(PROJECT_BASE_PATH)/source $(CMSIS_BASE_PATH) $(CMSIS_CHIP_PATH)/source/templates $(CMSIS_CHIP_PATH)/source/templates
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VPATH+=$(PROJECT_BASE_PATH)/source
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VPATH+=$(CMSIS_BASE_PATH)
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VPATH+=$(CMSIS_CHIP_PATH)/include
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VPATH+=$(CMSIS_CHIP_PATH)/source/templates
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VPATH+=$(CMSIS_CHIP_PATH)/source/templates/gcc
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INCLUDES = -I$(PROJECT_BASE_PATH)
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INCLUDES += -I$(PROJECT_BASE_PATH)/include
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INCLUDES += -I$(CMSIS_BASE_PATH)
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INCLUDES += -I$(CMSIS_CHIP_PATH)/include
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INCLUDES += -I$(CMSIS_CHIP_PATH)/source/templates
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#-------------------------------------------------------------------------------
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ifdef DEBUG
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@ -51,19 +75,20 @@ include $(TOOLCHAIN).mk
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#-------------------------------------------------------------------------------
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ifdef DEBUG
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OUTPUT_OBJ=debug
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OUTPUT_LIB=$(LIBNAME)_$(CHIP)_$(TOOLCHAIN)_dbg.a
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OUTPUT_LIB=$(LIBNAME)_$(CHIP_NAME)_$(TOOLCHAIN)_dbg.a
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else
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OUTPUT_OBJ=release
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OUTPUT_LIB=$(LIBNAME)_$(CHIP)_$(TOOLCHAIN)_rel.a
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OUTPUT_LIB=$(LIBNAME)_$(CHIP_NAME)_$(TOOLCHAIN)_rel.a
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endif
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OUTPUT_PATH=$(OUTPUT_OBJ)_$(CHIP)
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OUTPUT_PATH=$(OUTPUT_OBJ)_$(CHIP_NAME)
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#-------------------------------------------------------------------------------
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# C source files and objects
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#-------------------------------------------------------------------------------
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C_SRC=$(wildcard $(PROJECT_BASE_PATH)/source/*.c)
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C_SRC+=$(wildcard $(CMSIS_BASE_PATH)/*.c)
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C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/*.c)
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C_SRC+=$(wildcard $(CMSIS_CHIP_PATH)/gcc*.c)
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C_OBJ_TEMP=$(patsubst %.c, %.o, $(notdir $(C_SRC)))
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@ -103,7 +103,7 @@
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</option>
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<option>
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<name>GenLowLevelInterface</name>
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<state>1</state>
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<state>0</state>
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</option>
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<option>
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<name>GEndianModeBE</name>
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@ -164,7 +164,7 @@
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<debug>1</debug>
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<option>
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<name>CCDefines</name>
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<state>__sam3s4c__</state>
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<state>__SAM3S4C__</state>
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</option>
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<option>
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<name>CCPreprocFile</name>
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@ -295,6 +295,7 @@
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<name>CCIncludePath2</name>
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<state>$PROJ_DIR$\..</state>
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<state>$PROJ_DIR$\..\include</state>
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<state>$PROJ_DIR$\..\source\templates</state>
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</option>
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<option>
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<name>CCStdIncCheck</name>
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@ -3822,9 +3823,6 @@
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<file>
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<name>$PROJ_DIR$\..\cmsis\sam3s\include\sam3s4c.h</name>
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</file>
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<file>
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<name>$PROJ_DIR$\..\cmsis\sam3s\include\system_sam3s.h</name>
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</file>
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</group>
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<group>
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<name>source</name>
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@ -3832,12 +3830,6 @@
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<name>templates</name>
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<group>
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<name>iar</name>
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<file>
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<name>$PROJ_DIR$\..\cmsis\sam3s\source\templates\iar\exceptions.c</name>
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<excluded>
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<configuration>Debug</configuration>
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</excluded>
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</file>
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<file>
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<name>$PROJ_DIR$\..\cmsis\sam3s\source\templates\iar\startup_sam3s.c</name>
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</file>
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@ -3851,6 +3843,9 @@
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<file>
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<name>$PROJ_DIR$\..\cmsis\sam3s\source\templates\system_sam3s.c</name>
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</file>
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<file>
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<name>$PROJ_DIR$\..\cmsis\sam3s\source\templates\system_sam3s.h</name>
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</file>
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</group>
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</group>
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</group>
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@ -10,7 +10,23 @@
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<project>
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<path>$WS_DIR$\..\..\..\cores\sam\validation\build_iar\test.ewp</path>
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</project>
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<batchBuild/>
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<batchBuild>
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<batchDefinition>
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<name>all_debug_sam3s</name>
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<member>
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<project>libsam</project>
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<configuration>Debug</configuration>
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</member>
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<member>
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<project>libarduino</project>
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<configuration>Debug</configuration>
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</member>
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<member>
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<project>test</project>
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<configuration>Debug</configuration>
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</member>
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</batchDefinition>
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</batchBuild>
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</workspace>
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@ -1,17 +1,14 @@
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/*
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%atmel_license%
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*/
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#ifndef _LIB_SAM3S_
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#define _LIB_SAM3S_
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/*
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* Peripherals registers definitions
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* Core and peripherals registers definitions
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*/
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#if defined sam3s4
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#elif defined sam3s2
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#elif defined sam3s1
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#else
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#warning Library does not support the specified chip, specifying sam3s4.
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#define sam3s4
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#endif
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#include "include/SAM3S.h"
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#include "include/sam3.h"
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/** Define MAX number of Interrupts: (IRQn_Type+1) + 8 for CM3 core */
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#define EXTERNAL_NUM_INTERRUPTS (UDP_IRQn+1+8)
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@ -19,43 +16,29 @@
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/* Define attribute */
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#if defined ( __GNUC__ ) /* GCC CS3 */
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#define WEAK __attribute__ ((weak))
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#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */
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#define WEAK __weak
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#endif
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/* Define NO_INIT attribute */
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#if defined ( __GNUC__ )
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#define NO_INIT
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#elif defined ( __ICCARM__ )
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#define NO_INIT __no_init
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#endif
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/*
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* Core
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*/
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#include "include/exceptions.h"
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/*
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* Peripherals
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*/
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#include "include/acc.h"
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#include "include/adc.h"
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#include "include/async.h"
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#include "include/crccu.h"
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#include "include/dacc.h"
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#include "include/efc.h"
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#include "include/flashd.h"
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#include "include/pio.h"
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//#include "include/pio_it.h"
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#include "include/pio_capture.h"
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#include "include/pmc.h"
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#include "include/pwmc.h"
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#include "include/rtc.h"
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#include "include/rtt.h"
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#include "include/spi.h"
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#include "include/spi_pdc.h"
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#include "include/ssc.h"
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#include "include/tc.h"
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#include "include/twi.h"
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#include "include/twid.h"
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#include "include/usart.h"
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#include "include/wdt.h"
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@ -1,75 +1,95 @@
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/*
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||||
%atmel_license%
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||||
*/
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||||
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||||
/** \file cmsis example */
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||||
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#include <stdlib.h>
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#include <compiler.h>
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#include <board.h>
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#include "conf_board.h"
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volatile uint32_t msTicks = 0; /* counts 1ms timeTicks */
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//! counts 1ms timeTicks
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volatile uint32_t dw_ms_ticks = 0;
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|
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/*----------------------------------------------------------------------------
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SysTick_Handler
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*----------------------------------------------------------------------------*/
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||||
/**
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||||
* \brief SysTick_Handler.
|
||||
*/
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||||
void SysTick_Handler(void)
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||||
{
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msTicks++; /* increment counter necessary in Delay() */
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// increment counter necessary in delay()
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dw_ms_ticks++;
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}
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|
||||
/*----------------------------------------------------------------------------
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delays number of tick Systicks (happens every 1 ms)
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*----------------------------------------------------------------------------*/
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__INLINE static void Delay(uint32_t dlyTicks)
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/**
|
||||
* \brief delays number of tick Systicks (happens every 1 ms)
|
||||
*/
|
||||
__INLINE static void delay_ms(uint32_t dw_dly_ticks)
|
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{
|
||||
uint32_t curTicks;
|
||||
uint32_t dw_cur_ticks;
|
||||
|
||||
curTicks = msTicks;
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while ((msTicks - curTicks) < dlyTicks);
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||||
dw_cur_ticks = dw_ms_ticks;
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while ((dw_ms_ticks - dw_cur_ticks) < dw_dly_ticks);
|
||||
}
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||||
|
||||
/*----------------------------------------------------------------------------
|
||||
configer LED pins
|
||||
*----------------------------------------------------------------------------*/
|
||||
__INLINE static void LED_Config(void)
|
||||
/**
|
||||
* \brief configer LED pins
|
||||
*/
|
||||
__INLINE static void led_config(void)
|
||||
{
|
||||
LED0_PIO->PIO_PER = LED0_MASK; /* Setup Pin PA19 for LED */
|
||||
// Setup LED Pin
|
||||
LED0_PIO->PIO_PER = LED0_MASK;
|
||||
LED0_PIO->PIO_OER = LED0_MASK;
|
||||
LED0_PIO->PIO_PUDR = LED0_MASK;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Switch on LEDs
|
||||
*----------------------------------------------------------------------------*/
|
||||
__INLINE static void LED_On(uint32_t led)
|
||||
/**
|
||||
* \brief Switch on LED
|
||||
*/
|
||||
__INLINE static void led_on(uint32_t dw_led)
|
||||
{
|
||||
LED0_PIO->PIO_CODR = led; /* Turn On LED */
|
||||
// Turn On LED
|
||||
LED0_PIO->PIO_CODR = dw_led;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Switch off LEDs
|
||||
*----------------------------------------------------------------------------*/
|
||||
__INLINE static void LED_Off(uint32_t led)
|
||||
/**
|
||||
* \brief Switch off LED
|
||||
*/
|
||||
__INLINE static void led_off(uint32_t dw_led)
|
||||
{
|
||||
LED0_PIO->PIO_SODR = led; /* Turn Off LED */
|
||||
// Turn Off LED
|
||||
LED0_PIO->PIO_SODR = dw_led;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
MAIN function
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* \brief Application entry point.
|
||||
*
|
||||
* \return Unused (ANSI-C compatibility).
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
SystemInit();
|
||||
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
|
||||
if (SysTick_Config(SystemCoreClock / 1000)) { /* Setup SysTick Timer for 1 msec interrupts */
|
||||
while (1); /* Capture error */
|
||||
}
|
||||
|
||||
LED_Config();
|
||||
|
||||
SystemInit();
|
||||
|
||||
WDT->WDT_MR = WDT_MR_WDDIS;
|
||||
|
||||
// Setup SysTick Timer for 1 msec interrupts
|
||||
if (SysTick_Config(SystemCoreClock / 1000)) {
|
||||
// Capture error
|
||||
while (1);
|
||||
}
|
||||
|
||||
led_config();
|
||||
|
||||
// Flash the LED
|
||||
while(1) {
|
||||
LED_On (LED0_MASK); /* Turn on the LED. */
|
||||
Delay (1000); /* delay 100 Msec */
|
||||
LED_Off (LED0_MASK); /* Turn off the LED. */
|
||||
Delay (1000); /* delay 100 Msec */
|
||||
// Turn on the LED.
|
||||
led_on (LED0_MASK);
|
||||
// delay 1000 Msec.
|
||||
delay_ms (1000);
|
||||
|
||||
// Turn off the LED.
|
||||
led_off(LED0_MASK);
|
||||
// delay 1000 Msec.
|
||||
delay_ms (1000);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_ADC_COMPONENT_
|
||||
#define _SAM3N_ADC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_CHIPID_COMPONENT_
|
||||
#define _SAM3N_CHIPID_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_DACC_COMPONENT_
|
||||
#define _SAM3N_DACC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_EFC_COMPONENT_
|
||||
#define _SAM3N_EFC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_GPBR_COMPONENT_
|
||||
#define _SAM3N_GPBR_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_MATRIX_COMPONENT_
|
||||
#define _SAM3N_MATRIX_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PDC_COMPONENT_
|
||||
#define _SAM3N_PDC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PIO_COMPONENT_
|
||||
#define _SAM3N_PIO_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PMC_COMPONENT_
|
||||
#define _SAM3N_PMC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PWM_COMPONENT_
|
||||
#define _SAM3N_PWM_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_RSTC_COMPONENT_
|
||||
#define _SAM3N_RSTC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_RTC_COMPONENT_
|
||||
#define _SAM3N_RTC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_RTT_COMPONENT_
|
||||
#define _SAM3N_RTT_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_SPI_COMPONENT_
|
||||
#define _SAM3N_SPI_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_SUPC_COMPONENT_
|
||||
#define _SAM3N_SUPC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_TC_COMPONENT_
|
||||
#define _SAM3N_TC_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_TWI_COMPONENT_
|
||||
#define _SAM3N_TWI_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_UART_COMPONENT_
|
||||
#define _SAM3N_UART_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_USART_COMPONENT_
|
||||
#define _SAM3N_USART_COMPONENT_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_WDT_COMPONENT_
|
||||
#define _SAM3N_WDT_COMPONENT_
|
||||
|
||||
@ -1,37 +1,69 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_ADC_INSTANCE_
|
||||
#define _SAM3N_ADC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC peripheral ========== */
|
||||
#define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /**< \brief (ADC) Control Register */
|
||||
#define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /**< \brief (ADC) Mode Register */
|
||||
#define REG_ADC_SEQR1 REG_ACCESS(RwReg, 0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
|
||||
#define REG_ADC_SEQR2 REG_ACCESS(RwReg, 0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
|
||||
#define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /**< \brief (ADC) Channel Enable Register */
|
||||
#define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /**< \brief (ADC) Channel Disable Register */
|
||||
#define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /**< \brief (ADC) Channel Status Register */
|
||||
#define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /**< \brief (ADC) Last Converted Data Register */
|
||||
#define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
|
||||
#define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
|
||||
#define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
|
||||
#define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /**< \brief (ADC) Interrupt Status Register */
|
||||
#define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /**< \brief (ADC) Overrun Status Register */
|
||||
#define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /**< \brief (ADC) Extended Mode Register */
|
||||
#define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /**< \brief (ADC) Compare Window Register */
|
||||
#define REG_ADC_CDR REG_ACCESS(RoReg, 0x40038050U) /**< \brief (ADC) Channel Data Register */
|
||||
#define REG_ADC_TRGR REG_ACCESS(RwReg, 0x400380C0U) /**< \brief (ADC) Trigger Register */
|
||||
#define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
|
||||
#define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
|
||||
#define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /**< \brief (ADC) Receive Pointer Register */
|
||||
#define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /**< \brief (ADC) Receive Counter Register */
|
||||
#define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
|
||||
#define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
|
||||
#define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
|
||||
#define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
|
||||
#define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
|
||||
#define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
|
||||
#define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /**< \brief (ADC) Transfer Control Register */
|
||||
#define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /**< \brief (ADC) Transfer Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_ADC_CR (0x40038000U) /**< \brief (ADC) Control Register */
|
||||
#define REG_ADC_MR (0x40038004U) /**< \brief (ADC) Mode Register */
|
||||
#define REG_ADC_SEQR1 (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
|
||||
#define REG_ADC_SEQR2 (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
|
||||
#define REG_ADC_CHER (0x40038010U) /**< \brief (ADC) Channel Enable Register */
|
||||
#define REG_ADC_CHDR (0x40038014U) /**< \brief (ADC) Channel Disable Register */
|
||||
#define REG_ADC_CHSR (0x40038018U) /**< \brief (ADC) Channel Status Register */
|
||||
#define REG_ADC_LCDR (0x40038020U) /**< \brief (ADC) Last Converted Data Register */
|
||||
#define REG_ADC_IER (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
|
||||
#define REG_ADC_IDR (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
|
||||
#define REG_ADC_IMR (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
|
||||
#define REG_ADC_ISR (0x40038030U) /**< \brief (ADC) Interrupt Status Register */
|
||||
#define REG_ADC_OVER (0x4003803CU) /**< \brief (ADC) Overrun Status Register */
|
||||
#define REG_ADC_EMR (0x40038040U) /**< \brief (ADC) Extended Mode Register */
|
||||
#define REG_ADC_CWR (0x40038044U) /**< \brief (ADC) Compare Window Register */
|
||||
#define REG_ADC_CDR (0x40038050U) /**< \brief (ADC) Channel Data Register */
|
||||
#define REG_ADC_TRGR (0x400380C0U) /**< \brief (ADC) Trigger Register */
|
||||
#define REG_ADC_WPMR (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
|
||||
#define REG_ADC_WPSR (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
|
||||
#define REG_ADC_RPR (0x40038100U) /**< \brief (ADC) Receive Pointer Register */
|
||||
#define REG_ADC_RCR (0x40038104U) /**< \brief (ADC) Receive Counter Register */
|
||||
#define REG_ADC_TPR (0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
|
||||
#define REG_ADC_TCR (0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
|
||||
#define REG_ADC_RNPR (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
|
||||
#define REG_ADC_RNCR (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
|
||||
#define REG_ADC_TNPR (0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
|
||||
#define REG_ADC_TNCR (0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
|
||||
#define REG_ADC_PTCR (0x40038120U) /**< \brief (ADC) Transfer Control Register */
|
||||
#define REG_ADC_PTSR (0x40038124U) /**< \brief (ADC) Transfer Status Register */
|
||||
#else
|
||||
#define REG_ADC_CR (*(WoReg*)0x40038000U) /**< \brief (ADC) Control Register */
|
||||
#define REG_ADC_MR (*(RwReg*)0x40038004U) /**< \brief (ADC) Mode Register */
|
||||
#define REG_ADC_SEQR1 (*(RwReg*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */
|
||||
#define REG_ADC_SEQR2 (*(RwReg*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */
|
||||
#define REG_ADC_CHER (*(WoReg*)0x40038010U) /**< \brief (ADC) Channel Enable Register */
|
||||
#define REG_ADC_CHDR (*(WoReg*)0x40038014U) /**< \brief (ADC) Channel Disable Register */
|
||||
#define REG_ADC_CHSR (*(RoReg*)0x40038018U) /**< \brief (ADC) Channel Status Register */
|
||||
#define REG_ADC_LCDR (*(RoReg*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */
|
||||
#define REG_ADC_IER (*(WoReg*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */
|
||||
#define REG_ADC_IDR (*(WoReg*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */
|
||||
#define REG_ADC_IMR (*(RoReg*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */
|
||||
#define REG_ADC_ISR (*(RoReg*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */
|
||||
#define REG_ADC_OVER (*(RoReg*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */
|
||||
#define REG_ADC_EMR (*(RwReg*)0x40038040U) /**< \brief (ADC) Extended Mode Register */
|
||||
#define REG_ADC_CWR (*(RwReg*)0x40038044U) /**< \brief (ADC) Compare Window Register */
|
||||
#define REG_ADC_CDR (*(RoReg*)0x40038050U) /**< \brief (ADC) Channel Data Register */
|
||||
#define REG_ADC_TRGR (*(RwReg*)0x400380C0U) /**< \brief (ADC) Trigger Register */
|
||||
#define REG_ADC_WPMR (*(RwReg*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */
|
||||
#define REG_ADC_WPSR (*(RoReg*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */
|
||||
#define REG_ADC_RPR (*(RwReg*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */
|
||||
#define REG_ADC_RCR (*(RwReg*)0x40038104U) /**< \brief (ADC) Receive Counter Register */
|
||||
#define REG_ADC_TPR (*(RwReg*)0x40038108U) /**< \brief (ADC) Transmit Pointer Register */
|
||||
#define REG_ADC_TCR (*(RwReg*)0x4003810CU) /**< \brief (ADC) Transmit Counter Register */
|
||||
#define REG_ADC_RNPR (*(RwReg*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */
|
||||
#define REG_ADC_RNCR (*(RwReg*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */
|
||||
#define REG_ADC_TNPR (*(RwReg*)0x40038118U) /**< \brief (ADC) Transmit Next Pointer Register */
|
||||
#define REG_ADC_TNCR (*(RwReg*)0x4003811CU) /**< \brief (ADC) Transmit Next Counter Register */
|
||||
#define REG_ADC_PTCR (*(WoReg*)0x40038120U) /**< \brief (ADC) Transfer Control Register */
|
||||
#define REG_ADC_PTSR (*(RoReg*)0x40038124U) /**< \brief (ADC) Transfer Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_ADC_INSTANCE_ */
|
||||
|
||||
@ -1,10 +1,15 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_CHIPID_INSTANCE_
|
||||
#define _SAM3N_CHIPID_INSTANCE_
|
||||
|
||||
/* ========== Register definition for CHIPID peripheral ========== */
|
||||
#define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
|
||||
#define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
|
||||
#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
|
||||
#else
|
||||
#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
|
||||
#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_CHIPID_INSTANCE_ */
|
||||
|
||||
@ -1,27 +1,49 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_DACC_INSTANCE_
|
||||
#define _SAM3N_DACC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DACC peripheral ========== */
|
||||
#define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /**< \brief (DACC) Control Register */
|
||||
#define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /**< \brief (DACC) Mode Register */
|
||||
#define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C008U) /**< \brief (DACC) Conversion Data Register */
|
||||
#define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
|
||||
#define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
|
||||
#define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
|
||||
#define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
|
||||
#define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
|
||||
#define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
|
||||
#define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
|
||||
#define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /**< \brief (DACC) Receive Counter Register */
|
||||
#define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
|
||||
#define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
|
||||
#define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
|
||||
#define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
|
||||
#define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
|
||||
#define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
|
||||
#define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /**< \brief (DACC) Transfer Control Register */
|
||||
#define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /**< \brief (DACC) Transfer Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_DACC_CR (0x4003C000U) /**< \brief (DACC) Control Register */
|
||||
#define REG_DACC_MR (0x4003C004U) /**< \brief (DACC) Mode Register */
|
||||
#define REG_DACC_CDR (0x4003C008U) /**< \brief (DACC) Conversion Data Register */
|
||||
#define REG_DACC_IER (0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
|
||||
#define REG_DACC_IDR (0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
|
||||
#define REG_DACC_IMR (0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
|
||||
#define REG_DACC_ISR (0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
|
||||
#define REG_DACC_WPMR (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
|
||||
#define REG_DACC_WPSR (0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
|
||||
#define REG_DACC_RPR (0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
|
||||
#define REG_DACC_RCR (0x4003C104U) /**< \brief (DACC) Receive Counter Register */
|
||||
#define REG_DACC_TPR (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
|
||||
#define REG_DACC_TCR (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
|
||||
#define REG_DACC_RNPR (0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
|
||||
#define REG_DACC_RNCR (0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
|
||||
#define REG_DACC_TNPR (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
|
||||
#define REG_DACC_TNCR (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
|
||||
#define REG_DACC_PTCR (0x4003C120U) /**< \brief (DACC) Transfer Control Register */
|
||||
#define REG_DACC_PTSR (0x4003C124U) /**< \brief (DACC) Transfer Status Register */
|
||||
#else
|
||||
#define REG_DACC_CR (*(WoReg*)0x4003C000U) /**< \brief (DACC) Control Register */
|
||||
#define REG_DACC_MR (*(RwReg*)0x4003C004U) /**< \brief (DACC) Mode Register */
|
||||
#define REG_DACC_CDR (*(WoReg*)0x4003C008U) /**< \brief (DACC) Conversion Data Register */
|
||||
#define REG_DACC_IER (*(WoReg*)0x4003C00CU) /**< \brief (DACC) Interrupt Enable Register */
|
||||
#define REG_DACC_IDR (*(WoReg*)0x4003C010U) /**< \brief (DACC) Interrupt Disable Register */
|
||||
#define REG_DACC_IMR (*(RoReg*)0x4003C014U) /**< \brief (DACC) Interrupt Mask Register */
|
||||
#define REG_DACC_ISR (*(RoReg*)0x4003C018U) /**< \brief (DACC) Interrupt Status Register */
|
||||
#define REG_DACC_WPMR (*(RwReg*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode Register */
|
||||
#define REG_DACC_WPSR (*(RoReg*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status Register */
|
||||
#define REG_DACC_RPR (*(RwReg*)0x4003C100U) /**< \brief (DACC) Receive Pointer Register */
|
||||
#define REG_DACC_RCR (*(RwReg*)0x4003C104U) /**< \brief (DACC) Receive Counter Register */
|
||||
#define REG_DACC_TPR (*(RwReg*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */
|
||||
#define REG_DACC_TCR (*(RwReg*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */
|
||||
#define REG_DACC_RNPR (*(RwReg*)0x4003C110U) /**< \brief (DACC) Receive Next Pointer Register */
|
||||
#define REG_DACC_RNCR (*(RwReg*)0x4003C114U) /**< \brief (DACC) Receive Next Counter Register */
|
||||
#define REG_DACC_TNPR (*(RwReg*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */
|
||||
#define REG_DACC_TNCR (*(RwReg*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */
|
||||
#define REG_DACC_PTCR (*(WoReg*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */
|
||||
#define REG_DACC_PTSR (*(RoReg*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_DACC_INSTANCE_ */
|
||||
|
||||
@ -1,12 +1,19 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_EFC_INSTANCE_
|
||||
#define _SAM3N_EFC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EFC peripheral ========== */
|
||||
#define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
|
||||
#define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
|
||||
#define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
|
||||
#define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
|
||||
#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
|
||||
#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
|
||||
#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
|
||||
#else
|
||||
#define REG_EFC_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
|
||||
#define REG_EFC_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
|
||||
#define REG_EFC_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
|
||||
#define REG_EFC_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_EFC_INSTANCE_ */
|
||||
|
||||
@ -1,9 +1,13 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_GPBR_INSTANCE_
|
||||
#define _SAM3N_GPBR_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GPBR peripheral ========== */
|
||||
#define REG_GPBR_GPBR REG_ACCESS(RwReg, 0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_GPBR_GPBR (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
|
||||
#else
|
||||
#define REG_GPBR_GPBR (*(RwReg*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_GPBR_INSTANCE_ */
|
||||
|
||||
@ -1,17 +1,29 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_MATRIX_INSTANCE_
|
||||
#define _SAM3N_MATRIX_INSTANCE_
|
||||
|
||||
/* ========== Register definition for MATRIX peripheral ========== */
|
||||
#define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
|
||||
#define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
|
||||
#define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
|
||||
#define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
|
||||
#define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
|
||||
#define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
|
||||
#define REG_CCFG_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
|
||||
#define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
|
||||
#define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
|
||||
#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
|
||||
#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
|
||||
#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
|
||||
#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
|
||||
#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
|
||||
#define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
|
||||
#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
|
||||
#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
|
||||
#else
|
||||
#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
|
||||
#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
|
||||
#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
|
||||
#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
|
||||
#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
|
||||
#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
|
||||
#define REG_CCFG_SYSIO (*(RwReg*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */
|
||||
#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
|
||||
#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_MATRIX_INSTANCE_ */
|
||||
|
||||
@ -1,55 +1,105 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PIOA_INSTANCE_
|
||||
#define _SAM3N_PIOA_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOA peripheral ========== */
|
||||
#define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
|
||||
#define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
|
||||
#define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
|
||||
#define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
|
||||
#define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
|
||||
#define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /**< \brief (PIOA) Output Status Register */
|
||||
#define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
|
||||
#define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
|
||||
#define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
|
||||
#define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
|
||||
#define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
|
||||
#define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
|
||||
#define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
|
||||
#define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
|
||||
#define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
|
||||
#define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
|
||||
#define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
|
||||
#define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
|
||||
#define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
|
||||
#define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
|
||||
#define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
|
||||
#define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
|
||||
#define REG_PIOA_IFSCDR REG_ACCESS(WoReg, 0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOA_IFSCER REG_ACCESS(WoReg, 0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOA_IFSCSR REG_ACCESS(RoReg, 0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
|
||||
#define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
|
||||
#define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
|
||||
#define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
|
||||
#define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
|
||||
#define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
|
||||
#define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
|
||||
#define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
|
||||
#define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
|
||||
#define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /**< \brief (PIOA) Lock Status */
|
||||
#define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
|
||||
#define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
|
||||
#define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
|
||||
#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
|
||||
#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
|
||||
#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
|
||||
#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
|
||||
#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
|
||||
#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
|
||||
#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
|
||||
#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
|
||||
#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
|
||||
#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
|
||||
#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
|
||||
#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
|
||||
#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
|
||||
#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
|
||||
#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
|
||||
#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
|
||||
#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
|
||||
#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
|
||||
#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
|
||||
#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
|
||||
#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
|
||||
#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
|
||||
#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
|
||||
#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
|
||||
#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
|
||||
#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
|
||||
#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
|
||||
#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
|
||||
#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
|
||||
#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
|
||||
#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
|
||||
#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
|
||||
#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
|
||||
#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
|
||||
#else
|
||||
#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
|
||||
#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
|
||||
#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
|
||||
#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
|
||||
#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
|
||||
#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
|
||||
#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
|
||||
#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
|
||||
#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
|
||||
#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
|
||||
#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
|
||||
#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
|
||||
#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
|
||||
#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
|
||||
#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
|
||||
#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
|
||||
#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
|
||||
#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
|
||||
#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
|
||||
#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
|
||||
#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
|
||||
#define REG_PIOA_ABCDSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
|
||||
#define REG_PIOA_IFSCDR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOA_IFSCER (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOA_IFSCSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOA_PPDDR (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
|
||||
#define REG_PIOA_PPDER (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
|
||||
#define REG_PIOA_PPDSR (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
|
||||
#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
|
||||
#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
|
||||
#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
|
||||
#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
|
||||
#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
|
||||
#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
|
||||
#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
|
||||
#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
|
||||
#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
|
||||
#define REG_PIOA_SCHMITT (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_PIOA_INSTANCE_ */
|
||||
|
||||
@ -1,55 +1,105 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PIOB_INSTANCE_
|
||||
#define _SAM3N_PIOB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOB peripheral ========== */
|
||||
#define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
|
||||
#define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
|
||||
#define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /**< \brief (PIOB) PIO Status Register */
|
||||
#define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /**< \brief (PIOB) Output Enable Register */
|
||||
#define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /**< \brief (PIOB) Output Disable Register */
|
||||
#define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /**< \brief (PIOB) Output Status Register */
|
||||
#define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
|
||||
#define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
|
||||
#define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
|
||||
#define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
|
||||
#define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
|
||||
#define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
|
||||
#define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
|
||||
#define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
|
||||
#define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
|
||||
#define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
|
||||
#define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
|
||||
#define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
|
||||
#define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
|
||||
#define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
|
||||
#define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
|
||||
#define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
|
||||
#define REG_PIOB_IFSCDR REG_ACCESS(WoReg, 0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOB_IFSCER REG_ACCESS(WoReg, 0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOB_IFSCSR REG_ACCESS(RoReg, 0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
|
||||
#define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
|
||||
#define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
|
||||
#define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
|
||||
#define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
|
||||
#define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
|
||||
#define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
|
||||
#define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /**< \brief (PIOB) Level Select Register */
|
||||
#define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
|
||||
#define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /**< \brief (PIOB) Lock Status */
|
||||
#define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
|
||||
#define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
|
||||
#define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
|
||||
#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
|
||||
#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
|
||||
#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
|
||||
#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
|
||||
#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */
|
||||
#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
|
||||
#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
|
||||
#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
|
||||
#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
|
||||
#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
|
||||
#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
|
||||
#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
|
||||
#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
|
||||
#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
|
||||
#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
|
||||
#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
|
||||
#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
|
||||
#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
|
||||
#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
|
||||
#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
|
||||
#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
|
||||
#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
|
||||
#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
|
||||
#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
|
||||
#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
|
||||
#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
|
||||
#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
|
||||
#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
|
||||
#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
|
||||
#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
|
||||
#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */
|
||||
#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
|
||||
#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
|
||||
#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
|
||||
#else
|
||||
#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
|
||||
#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
|
||||
#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
|
||||
#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
|
||||
#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
|
||||
#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
|
||||
#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
|
||||
#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
|
||||
#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
|
||||
#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
|
||||
#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
|
||||
#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
|
||||
#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
|
||||
#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
|
||||
#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
|
||||
#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
|
||||
#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
|
||||
#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
|
||||
#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
|
||||
#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
|
||||
#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
|
||||
#define REG_PIOB_ABCDSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
|
||||
#define REG_PIOB_IFSCDR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOB_IFSCER (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOB_IFSCSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOB_PPDDR (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
|
||||
#define REG_PIOB_PPDER (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
|
||||
#define REG_PIOB_PPDSR (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
|
||||
#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
|
||||
#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
|
||||
#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
|
||||
#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
|
||||
#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
|
||||
#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
|
||||
#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
|
||||
#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
|
||||
#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
|
||||
#define REG_PIOB_SCHMITT (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_PIOB_INSTANCE_ */
|
||||
|
||||
@ -1,55 +1,105 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PIOC_INSTANCE_
|
||||
#define _SAM3N_PIOC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PIOC peripheral ========== */
|
||||
#define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
|
||||
#define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
|
||||
#define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /**< \brief (PIOC) PIO Status Register */
|
||||
#define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /**< \brief (PIOC) Output Enable Register */
|
||||
#define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /**< \brief (PIOC) Output Disable Register */
|
||||
#define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /**< \brief (PIOC) Output Status Register */
|
||||
#define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
|
||||
#define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
|
||||
#define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
|
||||
#define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
|
||||
#define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
|
||||
#define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
|
||||
#define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
|
||||
#define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
|
||||
#define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
|
||||
#define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
|
||||
#define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
|
||||
#define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
|
||||
#define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
|
||||
#define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
|
||||
#define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
|
||||
#define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
|
||||
#define REG_PIOC_IFSCDR REG_ACCESS(WoReg, 0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOC_IFSCER REG_ACCESS(WoReg, 0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOC_IFSCSR REG_ACCESS(RoReg, 0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
|
||||
#define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
|
||||
#define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
|
||||
#define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
|
||||
#define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
|
||||
#define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
|
||||
#define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
|
||||
#define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /**< \brief (PIOC) Level Select Register */
|
||||
#define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
|
||||
#define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /**< \brief (PIOC) Lock Status */
|
||||
#define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
|
||||
#define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
|
||||
#define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
|
||||
#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
|
||||
#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
|
||||
#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
|
||||
#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
|
||||
#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */
|
||||
#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
|
||||
#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
|
||||
#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
|
||||
#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
|
||||
#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
|
||||
#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
|
||||
#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
|
||||
#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
|
||||
#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
|
||||
#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
|
||||
#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
|
||||
#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
|
||||
#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
|
||||
#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
|
||||
#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
|
||||
#define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
|
||||
#define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
|
||||
#define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
|
||||
#define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
|
||||
#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
|
||||
#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
|
||||
#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
|
||||
#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
|
||||
#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
|
||||
#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
|
||||
#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */
|
||||
#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
|
||||
#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
|
||||
#define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
|
||||
#else
|
||||
#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
|
||||
#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
|
||||
#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
|
||||
#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
|
||||
#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
|
||||
#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
|
||||
#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
|
||||
#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
|
||||
#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
|
||||
#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
|
||||
#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
|
||||
#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
|
||||
#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
|
||||
#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
|
||||
#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
|
||||
#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
|
||||
#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
|
||||
#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
|
||||
#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
|
||||
#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
|
||||
#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
|
||||
#define REG_PIOC_ABCDSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
|
||||
#define REG_PIOC_IFSCDR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOC_IFSCER (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOC_IFSCSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOC_PPDDR (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
|
||||
#define REG_PIOC_PPDER (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
|
||||
#define REG_PIOC_PPDSR (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
|
||||
#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
|
||||
#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
|
||||
#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
|
||||
#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
|
||||
#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
|
||||
#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
|
||||
#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
|
||||
#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
|
||||
#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
|
||||
#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
|
||||
#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
|
||||
#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
|
||||
#define REG_PIOC_SCHMITT (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_PIOC_INSTANCE_ */
|
||||
|
||||
@ -1,29 +1,53 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PMC_INSTANCE_
|
||||
#define _SAM3N_PMC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PMC peripheral ========== */
|
||||
#define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
|
||||
#define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
|
||||
#define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /**< \brief (PMC) System Clock Status Register */
|
||||
#define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
|
||||
#define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
|
||||
#define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
|
||||
#define REG_CKGR_MOR REG_ACCESS(RwReg, 0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
|
||||
#define REG_CKGR_MCFR REG_ACCESS(RoReg, 0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
|
||||
#define REG_CKGR_PLLR REG_ACCESS(RwReg, 0x400E0428U) /**< \brief (PMC) PLL Register */
|
||||
#define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /**< \brief (PMC) Master Clock Register */
|
||||
#define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
|
||||
#define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
|
||||
#define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
|
||||
#define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /**< \brief (PMC) Status Register */
|
||||
#define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
|
||||
#define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
|
||||
#define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
|
||||
#define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
|
||||
#define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
|
||||
#define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
|
||||
#define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
|
||||
#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
|
||||
#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
|
||||
#define REG_PMC_PCER (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
|
||||
#define REG_PMC_PCDR (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
|
||||
#define REG_PMC_PCSR (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
|
||||
#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
|
||||
#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
|
||||
#define REG_CKGR_PLLR (0x400E0428U) /**< \brief (PMC) PLL Register */
|
||||
#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */
|
||||
#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
|
||||
#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
|
||||
#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
|
||||
#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */
|
||||
#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
|
||||
#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
|
||||
#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
|
||||
#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
|
||||
#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
|
||||
#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
|
||||
#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
|
||||
#else
|
||||
#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
|
||||
#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
|
||||
#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
|
||||
#define REG_PMC_PCER (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register */
|
||||
#define REG_PMC_PCDR (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register */
|
||||
#define REG_PMC_PCSR (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register */
|
||||
#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
|
||||
#define REG_CKGR_MCFR (*(RoReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
|
||||
#define REG_CKGR_PLLR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLL Register */
|
||||
#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
|
||||
#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
|
||||
#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
|
||||
#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
|
||||
#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
|
||||
#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
|
||||
#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
|
||||
#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
|
||||
#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
|
||||
#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
|
||||
#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
|
||||
#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_PMC_INSTANCE_ */
|
||||
|
||||
@ -1,36 +1,67 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_PWM_INSTANCE_
|
||||
#define _SAM3N_PWM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PWM peripheral ========== */
|
||||
#define REG_PWM_MR REG_ACCESS(RwReg, 0x40020000U) /**< \brief (PWM) PWM Mode Register */
|
||||
#define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /**< \brief (PWM) PWM Enable Register */
|
||||
#define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /**< \brief (PWM) PWM Disable Register */
|
||||
#define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /**< \brief (PWM) PWM Status Register */
|
||||
#define REG_PWM_IER REG_ACCESS(WoReg, 0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
|
||||
#define REG_PWM_IDR REG_ACCESS(WoReg, 0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
|
||||
#define REG_PWM_IMR REG_ACCESS(RoReg, 0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
|
||||
#define REG_PWM_ISR REG_ACCESS(RoReg, 0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
|
||||
#define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
|
||||
#define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
|
||||
#define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
|
||||
#define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
|
||||
#define REG_PWM_CUPD0 REG_ACCESS(WoReg, 0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
|
||||
#define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
|
||||
#define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
|
||||
#define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
|
||||
#define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
|
||||
#define REG_PWM_CUPD1 REG_ACCESS(WoReg, 0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
|
||||
#define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
|
||||
#define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
|
||||
#define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
|
||||
#define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
|
||||
#define REG_PWM_CUPD2 REG_ACCESS(WoReg, 0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
|
||||
#define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
|
||||
#define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
|
||||
#define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
|
||||
#define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
|
||||
#define REG_PWM_CUPD3 REG_ACCESS(WoReg, 0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_PWM_MR (0x40020000U) /**< \brief (PWM) PWM Mode Register */
|
||||
#define REG_PWM_ENA (0x40020004U) /**< \brief (PWM) PWM Enable Register */
|
||||
#define REG_PWM_DIS (0x40020008U) /**< \brief (PWM) PWM Disable Register */
|
||||
#define REG_PWM_SR (0x4002000CU) /**< \brief (PWM) PWM Status Register */
|
||||
#define REG_PWM_IER (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
|
||||
#define REG_PWM_IDR (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
|
||||
#define REG_PWM_IMR (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
|
||||
#define REG_PWM_ISR (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
|
||||
#define REG_PWM_CMR0 (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
|
||||
#define REG_PWM_CDTY0 (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
|
||||
#define REG_PWM_CPRD0 (0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
|
||||
#define REG_PWM_CCNT0 (0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
|
||||
#define REG_PWM_CUPD0 (0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
|
||||
#define REG_PWM_CMR1 (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
|
||||
#define REG_PWM_CDTY1 (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
|
||||
#define REG_PWM_CPRD1 (0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
|
||||
#define REG_PWM_CCNT1 (0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
|
||||
#define REG_PWM_CUPD1 (0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
|
||||
#define REG_PWM_CMR2 (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
|
||||
#define REG_PWM_CDTY2 (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
|
||||
#define REG_PWM_CPRD2 (0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
|
||||
#define REG_PWM_CCNT2 (0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
|
||||
#define REG_PWM_CUPD2 (0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
|
||||
#define REG_PWM_CMR3 (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
|
||||
#define REG_PWM_CDTY3 (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
|
||||
#define REG_PWM_CPRD3 (0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
|
||||
#define REG_PWM_CCNT3 (0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
|
||||
#define REG_PWM_CUPD3 (0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
|
||||
#else
|
||||
#define REG_PWM_MR (*(RwReg*)0x40020000U) /**< \brief (PWM) PWM Mode Register */
|
||||
#define REG_PWM_ENA (*(WoReg*)0x40020004U) /**< \brief (PWM) PWM Enable Register */
|
||||
#define REG_PWM_DIS (*(WoReg*)0x40020008U) /**< \brief (PWM) PWM Disable Register */
|
||||
#define REG_PWM_SR (*(RoReg*)0x4002000CU) /**< \brief (PWM) PWM Status Register */
|
||||
#define REG_PWM_IER (*(WoReg*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register */
|
||||
#define REG_PWM_IDR (*(WoReg*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register */
|
||||
#define REG_PWM_IMR (*(RoReg*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register */
|
||||
#define REG_PWM_ISR (*(RoReg*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register */
|
||||
#define REG_PWM_CMR0 (*(RwReg*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
|
||||
#define REG_PWM_CDTY0 (*(RwReg*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
|
||||
#define REG_PWM_CPRD0 (*(RwReg*)0x40020208U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
|
||||
#define REG_PWM_CCNT0 (*(RoReg*)0x4002020CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
|
||||
#define REG_PWM_CUPD0 (*(WoReg*)0x40020210U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 0) */
|
||||
#define REG_PWM_CMR1 (*(RwReg*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
|
||||
#define REG_PWM_CDTY1 (*(RwReg*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
|
||||
#define REG_PWM_CPRD1 (*(RwReg*)0x40020228U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
|
||||
#define REG_PWM_CCNT1 (*(RoReg*)0x4002022CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
|
||||
#define REG_PWM_CUPD1 (*(WoReg*)0x40020230U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 1) */
|
||||
#define REG_PWM_CMR2 (*(RwReg*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
|
||||
#define REG_PWM_CDTY2 (*(RwReg*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
|
||||
#define REG_PWM_CPRD2 (*(RwReg*)0x40020248U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
|
||||
#define REG_PWM_CCNT2 (*(RoReg*)0x4002024CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
|
||||
#define REG_PWM_CUPD2 (*(WoReg*)0x40020250U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 2) */
|
||||
#define REG_PWM_CMR3 (*(RwReg*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
|
||||
#define REG_PWM_CDTY3 (*(RwReg*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
|
||||
#define REG_PWM_CPRD3 (*(RwReg*)0x40020268U) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
|
||||
#define REG_PWM_CCNT3 (*(RoReg*)0x4002026CU) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
|
||||
#define REG_PWM_CUPD3 (*(WoReg*)0x40020270U) /**< \brief (PWM) PWM Channel Update Register (ch_num = 3) */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_PWM_INSTANCE_ */
|
||||
|
||||
@ -1,11 +1,17 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_RSTC_INSTANCE_
|
||||
#define _SAM3N_RSTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RSTC peripheral ========== */
|
||||
#define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /**< \brief (RSTC) Control Register */
|
||||
#define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /**< \brief (RSTC) Status Register */
|
||||
#define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /**< \brief (RSTC) Mode Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_RSTC_CR (0x400E1400U) /**< \brief (RSTC) Control Register */
|
||||
#define REG_RSTC_SR (0x400E1404U) /**< \brief (RSTC) Status Register */
|
||||
#define REG_RSTC_MR (0x400E1408U) /**< \brief (RSTC) Mode Register */
|
||||
#else
|
||||
#define REG_RSTC_CR (*(WoReg*)0x400E1400U) /**< \brief (RSTC) Control Register */
|
||||
#define REG_RSTC_SR (*(RoReg*)0x400E1404U) /**< \brief (RSTC) Status Register */
|
||||
#define REG_RSTC_MR (*(RwReg*)0x400E1408U) /**< \brief (RSTC) Mode Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_RSTC_INSTANCE_ */
|
||||
|
||||
@ -1,21 +1,37 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_RTC_INSTANCE_
|
||||
#define _SAM3N_RTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /**< \brief (RTC) Control Register */
|
||||
#define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /**< \brief (RTC) Mode Register */
|
||||
#define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /**< \brief (RTC) Time Register */
|
||||
#define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /**< \brief (RTC) Calendar Register */
|
||||
#define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /**< \brief (RTC) Time Alarm Register */
|
||||
#define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
|
||||
#define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /**< \brief (RTC) Status Register */
|
||||
#define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
|
||||
#define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
|
||||
#define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
|
||||
#define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
|
||||
#define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /**< \brief (RTC) Valid Entry Register */
|
||||
#define REG_RTC_WPMR REG_ACCESS(RwReg, 0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_RTC_CR (0x400E1460U) /**< \brief (RTC) Control Register */
|
||||
#define REG_RTC_MR (0x400E1464U) /**< \brief (RTC) Mode Register */
|
||||
#define REG_RTC_TIMR (0x400E1468U) /**< \brief (RTC) Time Register */
|
||||
#define REG_RTC_CALR (0x400E146CU) /**< \brief (RTC) Calendar Register */
|
||||
#define REG_RTC_TIMALR (0x400E1470U) /**< \brief (RTC) Time Alarm Register */
|
||||
#define REG_RTC_CALALR (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
|
||||
#define REG_RTC_SR (0x400E1478U) /**< \brief (RTC) Status Register */
|
||||
#define REG_RTC_SCCR (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
|
||||
#define REG_RTC_IER (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
|
||||
#define REG_RTC_IDR (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
|
||||
#define REG_RTC_IMR (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
|
||||
#define REG_RTC_VER (0x400E148CU) /**< \brief (RTC) Valid Entry Register */
|
||||
#define REG_RTC_WPMR (0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
|
||||
#else
|
||||
#define REG_RTC_CR (*(RwReg*)0x400E1460U) /**< \brief (RTC) Control Register */
|
||||
#define REG_RTC_MR (*(RwReg*)0x400E1464U) /**< \brief (RTC) Mode Register */
|
||||
#define REG_RTC_TIMR (*(RwReg*)0x400E1468U) /**< \brief (RTC) Time Register */
|
||||
#define REG_RTC_CALR (*(RwReg*)0x400E146CU) /**< \brief (RTC) Calendar Register */
|
||||
#define REG_RTC_TIMALR (*(RwReg*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */
|
||||
#define REG_RTC_CALALR (*(RwReg*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */
|
||||
#define REG_RTC_SR (*(RoReg*)0x400E1478U) /**< \brief (RTC) Status Register */
|
||||
#define REG_RTC_SCCR (*(WoReg*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */
|
||||
#define REG_RTC_IER (*(WoReg*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */
|
||||
#define REG_RTC_IDR (*(WoReg*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */
|
||||
#define REG_RTC_IMR (*(RoReg*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */
|
||||
#define REG_RTC_VER (*(RoReg*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */
|
||||
#define REG_RTC_WPMR (*(RwReg*)0x400E1544U) /**< \brief (RTC) Write Protect Mode Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_RTC_INSTANCE_ */
|
||||
|
||||
@ -1,12 +1,19 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_RTT_INSTANCE_
|
||||
#define _SAM3N_RTT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTT peripheral ========== */
|
||||
#define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /**< \brief (RTT) Mode Register */
|
||||
#define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /**< \brief (RTT) Alarm Register */
|
||||
#define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /**< \brief (RTT) Value Register */
|
||||
#define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /**< \brief (RTT) Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_RTT_MR (0x400E1430U) /**< \brief (RTT) Mode Register */
|
||||
#define REG_RTT_AR (0x400E1434U) /**< \brief (RTT) Alarm Register */
|
||||
#define REG_RTT_VR (0x400E1438U) /**< \brief (RTT) Value Register */
|
||||
#define REG_RTT_SR (0x400E143CU) /**< \brief (RTT) Status Register */
|
||||
#else
|
||||
#define REG_RTT_MR (*(RwReg*)0x400E1430U) /**< \brief (RTT) Mode Register */
|
||||
#define REG_RTT_AR (*(RwReg*)0x400E1434U) /**< \brief (RTT) Alarm Register */
|
||||
#define REG_RTT_VR (*(RoReg*)0x400E1438U) /**< \brief (RTT) Value Register */
|
||||
#define REG_RTT_SR (*(RoReg*)0x400E143CU) /**< \brief (RTT) Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_RTT_INSTANCE_ */
|
||||
|
||||
@ -1,29 +1,53 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_SPI_INSTANCE_
|
||||
#define _SAM3N_SPI_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SPI peripheral ========== */
|
||||
#define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /**< \brief (SPI) Control Register */
|
||||
#define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /**< \brief (SPI) Mode Register */
|
||||
#define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /**< \brief (SPI) Receive Data Register */
|
||||
#define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /**< \brief (SPI) Transmit Data Register */
|
||||
#define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /**< \brief (SPI) Status Register */
|
||||
#define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
|
||||
#define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
|
||||
#define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
|
||||
#define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /**< \brief (SPI) Chip Select Register */
|
||||
#define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
|
||||
#define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
|
||||
#define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /**< \brief (SPI) Receive Pointer Register */
|
||||
#define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /**< \brief (SPI) Receive Counter Register */
|
||||
#define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
|
||||
#define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
|
||||
#define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
|
||||
#define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
|
||||
#define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
|
||||
#define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
|
||||
#define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /**< \brief (SPI) Transfer Control Register */
|
||||
#define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /**< \brief (SPI) Transfer Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */
|
||||
#define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */
|
||||
#define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */
|
||||
#define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */
|
||||
#define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */
|
||||
#define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
|
||||
#define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
|
||||
#define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
|
||||
#define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */
|
||||
#define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
|
||||
#define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
|
||||
#define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */
|
||||
#define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */
|
||||
#define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
|
||||
#define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
|
||||
#define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
|
||||
#define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
|
||||
#define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
|
||||
#define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
|
||||
#define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */
|
||||
#define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */
|
||||
#else
|
||||
#define REG_SPI_CR (*(WoReg*)0x40008000U) /**< \brief (SPI) Control Register */
|
||||
#define REG_SPI_MR (*(RwReg*)0x40008004U) /**< \brief (SPI) Mode Register */
|
||||
#define REG_SPI_RDR (*(RoReg*)0x40008008U) /**< \brief (SPI) Receive Data Register */
|
||||
#define REG_SPI_TDR (*(WoReg*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */
|
||||
#define REG_SPI_SR (*(RoReg*)0x40008010U) /**< \brief (SPI) Status Register */
|
||||
#define REG_SPI_IER (*(WoReg*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */
|
||||
#define REG_SPI_IDR (*(WoReg*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */
|
||||
#define REG_SPI_IMR (*(RoReg*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */
|
||||
#define REG_SPI_CSR (*(RwReg*)0x40008030U) /**< \brief (SPI) Chip Select Register */
|
||||
#define REG_SPI_WPMR (*(RwReg*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */
|
||||
#define REG_SPI_WPSR (*(RoReg*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */
|
||||
#define REG_SPI_RPR (*(RwReg*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */
|
||||
#define REG_SPI_RCR (*(RwReg*)0x40008104U) /**< \brief (SPI) Receive Counter Register */
|
||||
#define REG_SPI_TPR (*(RwReg*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */
|
||||
#define REG_SPI_TCR (*(RwReg*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */
|
||||
#define REG_SPI_RNPR (*(RwReg*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */
|
||||
#define REG_SPI_RNCR (*(RwReg*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */
|
||||
#define REG_SPI_TNPR (*(RwReg*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */
|
||||
#define REG_SPI_TNCR (*(RwReg*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */
|
||||
#define REG_SPI_PTCR (*(WoReg*)0x40008120U) /**< \brief (SPI) Transfer Control Register */
|
||||
#define REG_SPI_PTSR (*(RoReg*)0x40008124U) /**< \brief (SPI) Transfer Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_SPI_INSTANCE_ */
|
||||
|
||||
@ -1,14 +1,23 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_SUPC_INSTANCE_
|
||||
#define _SAM3N_SUPC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SUPC peripheral ========== */
|
||||
#define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
|
||||
#define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
|
||||
#define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
|
||||
#define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
|
||||
#define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
|
||||
#define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_SUPC_CR (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
|
||||
#define REG_SUPC_SMMR (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
|
||||
#define REG_SUPC_MR (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
|
||||
#define REG_SUPC_WUMR (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
|
||||
#define REG_SUPC_WUIR (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
|
||||
#define REG_SUPC_SR (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
|
||||
#else
|
||||
#define REG_SUPC_CR (*(WoReg*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */
|
||||
#define REG_SUPC_SMMR (*(RwReg*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
|
||||
#define REG_SUPC_MR (*(RwReg*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */
|
||||
#define REG_SUPC_WUMR (*(RwReg*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
|
||||
#define REG_SUPC_WUIR (*(RwReg*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
|
||||
#define REG_SUPC_SR (*(RoReg*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_SUPC_INSTANCE_ */
|
||||
|
||||
@ -1,48 +1,91 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_TC0_INSTANCE_
|
||||
#define _SAM3N_TC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC0 peripheral ========== */
|
||||
#define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
|
||||
#define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC0_SMMR0 REG_ACCESS(RwReg, 0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
|
||||
#define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
|
||||
#define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
|
||||
#define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
|
||||
#define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
|
||||
#define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
|
||||
#define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC0_SMMR1 REG_ACCESS(RwReg, 0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
|
||||
#define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
|
||||
#define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
|
||||
#define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
|
||||
#define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
|
||||
#define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
|
||||
#define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC0_SMMR2 REG_ACCESS(RwReg, 0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
|
||||
#define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
|
||||
#define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
|
||||
#define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
|
||||
#define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
|
||||
#define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /**< \brief (TC0) Block Control Register */
|
||||
#define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /**< \brief (TC0) Block Mode Register */
|
||||
#define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
|
||||
#define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
|
||||
#define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
|
||||
#define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
|
||||
#define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_TC0_CCR0 (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
|
||||
#define REG_TC0_CMR0 (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC0_SMMR0 (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC0_CV0 (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
|
||||
#define REG_TC0_RA0 (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
|
||||
#define REG_TC0_RB0 (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
|
||||
#define REG_TC0_RC0 (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
|
||||
#define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
|
||||
#define REG_TC0_IER0 (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC0_IDR0 (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC0_IMR0 (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC0_CCR1 (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
|
||||
#define REG_TC0_CMR1 (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC0_SMMR1 (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC0_CV1 (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
|
||||
#define REG_TC0_RA1 (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
|
||||
#define REG_TC0_RB1 (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
|
||||
#define REG_TC0_RC1 (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
|
||||
#define REG_TC0_SR1 (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
|
||||
#define REG_TC0_IER1 (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC0_IDR1 (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC0_CCR2 (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
|
||||
#define REG_TC0_CMR2 (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC0_SMMR2 (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC0_CV2 (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
|
||||
#define REG_TC0_RA2 (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
|
||||
#define REG_TC0_RB2 (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
|
||||
#define REG_TC0_RC2 (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
|
||||
#define REG_TC0_SR2 (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
|
||||
#define REG_TC0_IER2 (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC0_IDR2 (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC0_IMR2 (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC0_BCR (0x400100C0U) /**< \brief (TC0) Block Control Register */
|
||||
#define REG_TC0_BMR (0x400100C4U) /**< \brief (TC0) Block Mode Register */
|
||||
#define REG_TC0_QIER (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
|
||||
#define REG_TC0_QIDR (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
|
||||
#define REG_TC0_QIMR (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
|
||||
#define REG_TC0_QISR (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
|
||||
#define REG_TC0_WPMR (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
|
||||
#else
|
||||
#define REG_TC0_CCR0 (*(WoReg*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
|
||||
#define REG_TC0_CMR0 (*(RwReg*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC0_SMMR0 (*(RwReg*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC0_CV0 (*(RoReg*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */
|
||||
#define REG_TC0_RA0 (*(RwReg*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */
|
||||
#define REG_TC0_RB0 (*(RwReg*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */
|
||||
#define REG_TC0_RC0 (*(RwReg*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */
|
||||
#define REG_TC0_SR0 (*(RoReg*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */
|
||||
#define REG_TC0_IER0 (*(WoReg*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC0_IDR0 (*(WoReg*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC0_IMR0 (*(RoReg*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC0_CCR1 (*(WoReg*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
|
||||
#define REG_TC0_CMR1 (*(RwReg*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC0_SMMR1 (*(RwReg*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC0_CV1 (*(RoReg*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */
|
||||
#define REG_TC0_RA1 (*(RwReg*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */
|
||||
#define REG_TC0_RB1 (*(RwReg*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */
|
||||
#define REG_TC0_RC1 (*(RwReg*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */
|
||||
#define REG_TC0_SR1 (*(RoReg*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */
|
||||
#define REG_TC0_IER1 (*(WoReg*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC0_IDR1 (*(WoReg*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC0_IMR1 (*(RoReg*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC0_CCR2 (*(WoReg*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
|
||||
#define REG_TC0_CMR2 (*(RwReg*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC0_SMMR2 (*(RwReg*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC0_CV2 (*(RoReg*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */
|
||||
#define REG_TC0_RA2 (*(RwReg*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */
|
||||
#define REG_TC0_RB2 (*(RwReg*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */
|
||||
#define REG_TC0_RC2 (*(RwReg*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */
|
||||
#define REG_TC0_SR2 (*(RoReg*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */
|
||||
#define REG_TC0_IER2 (*(WoReg*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC0_IDR2 (*(WoReg*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC0_IMR2 (*(RoReg*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC0_BCR (*(WoReg*)0x400100C0U) /**< \brief (TC0) Block Control Register */
|
||||
#define REG_TC0_BMR (*(RwReg*)0x400100C4U) /**< \brief (TC0) Block Mode Register */
|
||||
#define REG_TC0_QIER (*(WoReg*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
|
||||
#define REG_TC0_QIDR (*(WoReg*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
|
||||
#define REG_TC0_QIMR (*(RoReg*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
|
||||
#define REG_TC0_QISR (*(RoReg*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
|
||||
#define REG_TC0_WPMR (*(RwReg*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_TC0_INSTANCE_ */
|
||||
|
||||
@ -1,48 +1,91 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_TC1_INSTANCE_
|
||||
#define _SAM3N_TC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC1 peripheral ========== */
|
||||
#define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
|
||||
#define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC1_SMMR0 REG_ACCESS(RwReg, 0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
|
||||
#define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
|
||||
#define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
|
||||
#define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
|
||||
#define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
|
||||
#define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
|
||||
#define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC1_SMMR1 REG_ACCESS(RwReg, 0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
|
||||
#define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
|
||||
#define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
|
||||
#define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
|
||||
#define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
|
||||
#define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
|
||||
#define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC1_SMMR2 REG_ACCESS(RwReg, 0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
|
||||
#define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
|
||||
#define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
|
||||
#define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
|
||||
#define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
|
||||
#define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /**< \brief (TC1) Block Control Register */
|
||||
#define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /**< \brief (TC1) Block Mode Register */
|
||||
#define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
|
||||
#define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
|
||||
#define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
|
||||
#define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
|
||||
#define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_TC1_CCR0 (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
|
||||
#define REG_TC1_CMR0 (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC1_SMMR0 (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC1_CV0 (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
|
||||
#define REG_TC1_RA0 (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
|
||||
#define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
|
||||
#define REG_TC1_RC0 (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
|
||||
#define REG_TC1_SR0 (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
|
||||
#define REG_TC1_IER0 (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC1_IDR0 (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC1_IMR0 (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC1_CCR1 (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
|
||||
#define REG_TC1_CMR1 (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC1_SMMR1 (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC1_CV1 (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
|
||||
#define REG_TC1_RA1 (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
|
||||
#define REG_TC1_RB1 (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
|
||||
#define REG_TC1_RC1 (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
|
||||
#define REG_TC1_SR1 (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
|
||||
#define REG_TC1_IER1 (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC1_IDR1 (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC1_IMR1 (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC1_CCR2 (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
|
||||
#define REG_TC1_CMR2 (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC1_SMMR2 (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC1_CV2 (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
|
||||
#define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
|
||||
#define REG_TC1_RB2 (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
|
||||
#define REG_TC1_RC2 (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
|
||||
#define REG_TC1_SR2 (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
|
||||
#define REG_TC1_IER2 (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC1_IDR2 (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC1_IMR2 (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC1_BCR (0x400140C0U) /**< \brief (TC1) Block Control Register */
|
||||
#define REG_TC1_BMR (0x400140C4U) /**< \brief (TC1) Block Mode Register */
|
||||
#define REG_TC1_QIER (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
|
||||
#define REG_TC1_QIDR (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
|
||||
#define REG_TC1_QIMR (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
|
||||
#define REG_TC1_QISR (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
|
||||
#define REG_TC1_WPMR (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
|
||||
#else
|
||||
#define REG_TC1_CCR0 (*(WoReg*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
|
||||
#define REG_TC1_CMR0 (*(RwReg*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
|
||||
#define REG_TC1_SMMR0 (*(RwReg*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
|
||||
#define REG_TC1_CV0 (*(RoReg*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */
|
||||
#define REG_TC1_RA0 (*(RwReg*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */
|
||||
#define REG_TC1_RB0 (*(RwReg*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */
|
||||
#define REG_TC1_RC0 (*(RwReg*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */
|
||||
#define REG_TC1_SR0 (*(RoReg*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */
|
||||
#define REG_TC1_IER0 (*(WoReg*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
|
||||
#define REG_TC1_IDR0 (*(WoReg*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
|
||||
#define REG_TC1_IMR0 (*(RoReg*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
|
||||
#define REG_TC1_CCR1 (*(WoReg*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
|
||||
#define REG_TC1_CMR1 (*(RwReg*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
|
||||
#define REG_TC1_SMMR1 (*(RwReg*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
|
||||
#define REG_TC1_CV1 (*(RoReg*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */
|
||||
#define REG_TC1_RA1 (*(RwReg*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */
|
||||
#define REG_TC1_RB1 (*(RwReg*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */
|
||||
#define REG_TC1_RC1 (*(RwReg*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */
|
||||
#define REG_TC1_SR1 (*(RoReg*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */
|
||||
#define REG_TC1_IER1 (*(WoReg*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
|
||||
#define REG_TC1_IDR1 (*(WoReg*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
|
||||
#define REG_TC1_IMR1 (*(RoReg*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
|
||||
#define REG_TC1_CCR2 (*(WoReg*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
|
||||
#define REG_TC1_CMR2 (*(RwReg*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
|
||||
#define REG_TC1_SMMR2 (*(RwReg*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
|
||||
#define REG_TC1_CV2 (*(RoReg*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */
|
||||
#define REG_TC1_RA2 (*(RwReg*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */
|
||||
#define REG_TC1_RB2 (*(RwReg*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */
|
||||
#define REG_TC1_RC2 (*(RwReg*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */
|
||||
#define REG_TC1_SR2 (*(RoReg*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */
|
||||
#define REG_TC1_IER2 (*(WoReg*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
|
||||
#define REG_TC1_IDR2 (*(WoReg*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
|
||||
#define REG_TC1_IMR2 (*(RoReg*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
|
||||
#define REG_TC1_BCR (*(WoReg*)0x400140C0U) /**< \brief (TC1) Block Control Register */
|
||||
#define REG_TC1_BMR (*(RwReg*)0x400140C4U) /**< \brief (TC1) Block Mode Register */
|
||||
#define REG_TC1_QIER (*(WoReg*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
|
||||
#define REG_TC1_QIDR (*(WoReg*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
|
||||
#define REG_TC1_QIMR (*(RoReg*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
|
||||
#define REG_TC1_QISR (*(RoReg*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
|
||||
#define REG_TC1_WPMR (*(RwReg*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_TC1_INSTANCE_ */
|
||||
|
||||
@ -1,29 +1,53 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_TWI0_INSTANCE_
|
||||
#define _SAM3N_TWI0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TWI0 peripheral ========== */
|
||||
#define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /**< \brief (TWI0) Control Register */
|
||||
#define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /**< \brief (TWI0) Master Mode Register */
|
||||
#define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /**< \brief (TWI0) Slave Mode Register */
|
||||
#define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /**< \brief (TWI0) Internal Address Register */
|
||||
#define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
|
||||
#define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /**< \brief (TWI0) Status Register */
|
||||
#define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
|
||||
#define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
|
||||
#define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
|
||||
#define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /**< \brief (TWI0) Receive Holding Register */
|
||||
#define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
|
||||
#define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
|
||||
#define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /**< \brief (TWI0) Receive Counter Register */
|
||||
#define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
|
||||
#define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
|
||||
#define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
|
||||
#define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
|
||||
#define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
|
||||
#define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
|
||||
#define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /**< \brief (TWI0) Transfer Control Register */
|
||||
#define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /**< \brief (TWI0) Transfer Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_TWI0_CR (0x40018000U) /**< \brief (TWI0) Control Register */
|
||||
#define REG_TWI0_MMR (0x40018004U) /**< \brief (TWI0) Master Mode Register */
|
||||
#define REG_TWI0_SMR (0x40018008U) /**< \brief (TWI0) Slave Mode Register */
|
||||
#define REG_TWI0_IADR (0x4001800CU) /**< \brief (TWI0) Internal Address Register */
|
||||
#define REG_TWI0_CWGR (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
|
||||
#define REG_TWI0_SR (0x40018020U) /**< \brief (TWI0) Status Register */
|
||||
#define REG_TWI0_IER (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
|
||||
#define REG_TWI0_IDR (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
|
||||
#define REG_TWI0_IMR (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
|
||||
#define REG_TWI0_RHR (0x40018030U) /**< \brief (TWI0) Receive Holding Register */
|
||||
#define REG_TWI0_THR (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
|
||||
#define REG_TWI0_RPR (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
|
||||
#define REG_TWI0_RCR (0x40018104U) /**< \brief (TWI0) Receive Counter Register */
|
||||
#define REG_TWI0_TPR (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
|
||||
#define REG_TWI0_TCR (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
|
||||
#define REG_TWI0_RNPR (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
|
||||
#define REG_TWI0_RNCR (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
|
||||
#define REG_TWI0_TNPR (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
|
||||
#define REG_TWI0_TNCR (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
|
||||
#define REG_TWI0_PTCR (0x40018120U) /**< \brief (TWI0) Transfer Control Register */
|
||||
#define REG_TWI0_PTSR (0x40018124U) /**< \brief (TWI0) Transfer Status Register */
|
||||
#else
|
||||
#define REG_TWI0_CR (*(WoReg*)0x40018000U) /**< \brief (TWI0) Control Register */
|
||||
#define REG_TWI0_MMR (*(RwReg*)0x40018004U) /**< \brief (TWI0) Master Mode Register */
|
||||
#define REG_TWI0_SMR (*(RwReg*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */
|
||||
#define REG_TWI0_IADR (*(RwReg*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */
|
||||
#define REG_TWI0_CWGR (*(RwReg*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */
|
||||
#define REG_TWI0_SR (*(RoReg*)0x40018020U) /**< \brief (TWI0) Status Register */
|
||||
#define REG_TWI0_IER (*(WoReg*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */
|
||||
#define REG_TWI0_IDR (*(WoReg*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */
|
||||
#define REG_TWI0_IMR (*(RoReg*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */
|
||||
#define REG_TWI0_RHR (*(RoReg*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */
|
||||
#define REG_TWI0_THR (*(WoReg*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */
|
||||
#define REG_TWI0_RPR (*(RwReg*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */
|
||||
#define REG_TWI0_RCR (*(RwReg*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */
|
||||
#define REG_TWI0_TPR (*(RwReg*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */
|
||||
#define REG_TWI0_TCR (*(RwReg*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */
|
||||
#define REG_TWI0_RNPR (*(RwReg*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */
|
||||
#define REG_TWI0_RNCR (*(RwReg*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */
|
||||
#define REG_TWI0_TNPR (*(RwReg*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */
|
||||
#define REG_TWI0_TNCR (*(RwReg*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */
|
||||
#define REG_TWI0_PTCR (*(WoReg*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */
|
||||
#define REG_TWI0_PTSR (*(RoReg*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_TWI0_INSTANCE_ */
|
||||
|
||||
@ -1,19 +1,33 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_TWI1_INSTANCE_
|
||||
#define _SAM3N_TWI1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TWI1 peripheral ========== */
|
||||
#define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /**< \brief (TWI1) Control Register */
|
||||
#define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /**< \brief (TWI1) Master Mode Register */
|
||||
#define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
|
||||
#define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
|
||||
#define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
|
||||
#define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /**< \brief (TWI1) Status Register */
|
||||
#define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
|
||||
#define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
|
||||
#define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
|
||||
#define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
|
||||
#define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_TWI1_CR (0x4001C000U) /**< \brief (TWI1) Control Register */
|
||||
#define REG_TWI1_MMR (0x4001C004U) /**< \brief (TWI1) Master Mode Register */
|
||||
#define REG_TWI1_SMR (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
|
||||
#define REG_TWI1_IADR (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
|
||||
#define REG_TWI1_CWGR (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
|
||||
#define REG_TWI1_SR (0x4001C020U) /**< \brief (TWI1) Status Register */
|
||||
#define REG_TWI1_IER (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
|
||||
#define REG_TWI1_IDR (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
|
||||
#define REG_TWI1_IMR (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
|
||||
#define REG_TWI1_RHR (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
|
||||
#define REG_TWI1_THR (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
|
||||
#else
|
||||
#define REG_TWI1_CR (*(WoReg*)0x4001C000U) /**< \brief (TWI1) Control Register */
|
||||
#define REG_TWI1_MMR (*(RwReg*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */
|
||||
#define REG_TWI1_SMR (*(RwReg*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */
|
||||
#define REG_TWI1_IADR (*(RwReg*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */
|
||||
#define REG_TWI1_CWGR (*(RwReg*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */
|
||||
#define REG_TWI1_SR (*(RoReg*)0x4001C020U) /**< \brief (TWI1) Status Register */
|
||||
#define REG_TWI1_IER (*(WoReg*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */
|
||||
#define REG_TWI1_IDR (*(WoReg*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */
|
||||
#define REG_TWI1_IMR (*(RoReg*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */
|
||||
#define REG_TWI1_RHR (*(RoReg*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */
|
||||
#define REG_TWI1_THR (*(WoReg*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_TWI1_INSTANCE_ */
|
||||
|
||||
@ -1,27 +1,49 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_UART0_INSTANCE_
|
||||
#define _SAM3N_UART0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for UART0 peripheral ========== */
|
||||
#define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /**< \brief (UART0) Control Register */
|
||||
#define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /**< \brief (UART0) Mode Register */
|
||||
#define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
|
||||
#define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
|
||||
#define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
|
||||
#define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /**< \brief (UART0) Status Register */
|
||||
#define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /**< \brief (UART0) Receive Holding Register */
|
||||
#define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
|
||||
#define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
|
||||
#define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
|
||||
#define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /**< \brief (UART0) Receive Counter Register */
|
||||
#define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
|
||||
#define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
|
||||
#define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
|
||||
#define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
|
||||
#define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
|
||||
#define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
|
||||
#define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /**< \brief (UART0) Transfer Control Register */
|
||||
#define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /**< \brief (UART0) Transfer Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */
|
||||
#define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */
|
||||
#define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
|
||||
#define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
|
||||
#define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
|
||||
#define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */
|
||||
#define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
|
||||
#define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
|
||||
#define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
|
||||
#define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
|
||||
#define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
|
||||
#define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
|
||||
#define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
|
||||
#define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
|
||||
#define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
|
||||
#define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
|
||||
#define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
|
||||
#define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
|
||||
#define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
|
||||
#else
|
||||
#define REG_UART0_CR (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
|
||||
#define REG_UART0_MR (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
|
||||
#define REG_UART0_IER (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
|
||||
#define REG_UART0_IDR (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
|
||||
#define REG_UART0_IMR (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
|
||||
#define REG_UART0_SR (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
|
||||
#define REG_UART0_RHR (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
|
||||
#define REG_UART0_THR (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
|
||||
#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
|
||||
#define REG_UART0_RPR (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
|
||||
#define REG_UART0_RCR (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
|
||||
#define REG_UART0_TPR (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
|
||||
#define REG_UART0_TCR (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
|
||||
#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
|
||||
#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
|
||||
#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
|
||||
#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
|
||||
#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
|
||||
#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_UART0_INSTANCE_ */
|
||||
|
||||
@ -1,17 +1,29 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_UART1_INSTANCE_
|
||||
#define _SAM3N_UART1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for UART1 peripheral ========== */
|
||||
#define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /**< \brief (UART1) Control Register */
|
||||
#define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /**< \brief (UART1) Mode Register */
|
||||
#define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
|
||||
#define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
|
||||
#define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
|
||||
#define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /**< \brief (UART1) Status Register */
|
||||
#define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /**< \brief (UART1) Receive Holding Register */
|
||||
#define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
|
||||
#define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_UART1_CR (0x400E0800U) /**< \brief (UART1) Control Register */
|
||||
#define REG_UART1_MR (0x400E0804U) /**< \brief (UART1) Mode Register */
|
||||
#define REG_UART1_IER (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
|
||||
#define REG_UART1_IDR (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
|
||||
#define REG_UART1_IMR (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
|
||||
#define REG_UART1_SR (0x400E0814U) /**< \brief (UART1) Status Register */
|
||||
#define REG_UART1_RHR (0x400E0818U) /**< \brief (UART1) Receive Holding Register */
|
||||
#define REG_UART1_THR (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
|
||||
#define REG_UART1_BRGR (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
|
||||
#else
|
||||
#define REG_UART1_CR (*(WoReg*)0x400E0800U) /**< \brief (UART1) Control Register */
|
||||
#define REG_UART1_MR (*(RwReg*)0x400E0804U) /**< \brief (UART1) Mode Register */
|
||||
#define REG_UART1_IER (*(WoReg*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */
|
||||
#define REG_UART1_IDR (*(WoReg*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */
|
||||
#define REG_UART1_IMR (*(RoReg*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */
|
||||
#define REG_UART1_SR (*(RoReg*)0x400E0814U) /**< \brief (UART1) Status Register */
|
||||
#define REG_UART1_RHR (*(RoReg*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */
|
||||
#define REG_UART1_THR (*(WoReg*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */
|
||||
#define REG_UART1_BRGR (*(RwReg*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_UART1_INSTANCE_ */
|
||||
|
||||
@ -1,34 +1,63 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_USART0_INSTANCE_
|
||||
#define _SAM3N_USART0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART0 peripheral ========== */
|
||||
#define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /**< \brief (USART0) Control Register */
|
||||
#define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /**< \brief (USART0) Mode Register */
|
||||
#define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
|
||||
#define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
|
||||
#define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
|
||||
#define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /**< \brief (USART0) Channel Status Register */
|
||||
#define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /**< \brief (USART0) Receiver Holding Register */
|
||||
#define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
|
||||
#define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
|
||||
#define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
|
||||
#define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
|
||||
#define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
|
||||
#define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /**< \brief (USART0) Number of Errors Register */
|
||||
#define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
|
||||
#define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
|
||||
#define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
|
||||
#define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /**< \brief (USART0) Receive Pointer Register */
|
||||
#define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /**< \brief (USART0) Receive Counter Register */
|
||||
#define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
|
||||
#define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
|
||||
#define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
|
||||
#define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
|
||||
#define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
|
||||
#define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
|
||||
#define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /**< \brief (USART0) Transfer Control Register */
|
||||
#define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /**< \brief (USART0) Transfer Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */
|
||||
#define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */
|
||||
#define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
|
||||
#define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
|
||||
#define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
|
||||
#define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */
|
||||
#define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receiver Holding Register */
|
||||
#define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
|
||||
#define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
|
||||
#define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
|
||||
#define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
|
||||
#define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
|
||||
#define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */
|
||||
#define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
|
||||
#define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
|
||||
#define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
|
||||
#define REG_USART0_RPR (0x40024100U) /**< \brief (USART0) Receive Pointer Register */
|
||||
#define REG_USART0_RCR (0x40024104U) /**< \brief (USART0) Receive Counter Register */
|
||||
#define REG_USART0_TPR (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
|
||||
#define REG_USART0_TCR (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
|
||||
#define REG_USART0_RNPR (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
|
||||
#define REG_USART0_RNCR (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
|
||||
#define REG_USART0_TNPR (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
|
||||
#define REG_USART0_TNCR (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
|
||||
#define REG_USART0_PTCR (0x40024120U) /**< \brief (USART0) Transfer Control Register */
|
||||
#define REG_USART0_PTSR (0x40024124U) /**< \brief (USART0) Transfer Status Register */
|
||||
#else
|
||||
#define REG_USART0_CR (*(WoReg*)0x40024000U) /**< \brief (USART0) Control Register */
|
||||
#define REG_USART0_MR (*(RwReg*)0x40024004U) /**< \brief (USART0) Mode Register */
|
||||
#define REG_USART0_IER (*(WoReg*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
|
||||
#define REG_USART0_IDR (*(WoReg*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
|
||||
#define REG_USART0_IMR (*(RoReg*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
|
||||
#define REG_USART0_CSR (*(RoReg*)0x40024014U) /**< \brief (USART0) Channel Status Register */
|
||||
#define REG_USART0_RHR (*(RoReg*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */
|
||||
#define REG_USART0_THR (*(WoReg*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */
|
||||
#define REG_USART0_BRGR (*(RwReg*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
|
||||
#define REG_USART0_RTOR (*(RwReg*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
|
||||
#define REG_USART0_TTGR (*(RwReg*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
|
||||
#define REG_USART0_FIDI (*(RwReg*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */
|
||||
#define REG_USART0_NER (*(RoReg*)0x40024044U) /**< \brief (USART0) Number of Errors Register */
|
||||
#define REG_USART0_IF (*(RwReg*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */
|
||||
#define REG_USART0_WPMR (*(RwReg*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */
|
||||
#define REG_USART0_WPSR (*(RoReg*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */
|
||||
#define REG_USART0_RPR (*(RwReg*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */
|
||||
#define REG_USART0_RCR (*(RwReg*)0x40024104U) /**< \brief (USART0) Receive Counter Register */
|
||||
#define REG_USART0_TPR (*(RwReg*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */
|
||||
#define REG_USART0_TCR (*(RwReg*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */
|
||||
#define REG_USART0_RNPR (*(RwReg*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */
|
||||
#define REG_USART0_RNCR (*(RwReg*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */
|
||||
#define REG_USART0_TNPR (*(RwReg*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */
|
||||
#define REG_USART0_TNCR (*(RwReg*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */
|
||||
#define REG_USART0_PTCR (*(WoReg*)0x40024120U) /**< \brief (USART0) Transfer Control Register */
|
||||
#define REG_USART0_PTSR (*(RoReg*)0x40024124U) /**< \brief (USART0) Transfer Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_USART0_INSTANCE_ */
|
||||
|
||||
@ -1,24 +1,43 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_USART1_INSTANCE_
|
||||
#define _SAM3N_USART1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USART1 peripheral ========== */
|
||||
#define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /**< \brief (USART1) Control Register */
|
||||
#define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /**< \brief (USART1) Mode Register */
|
||||
#define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
|
||||
#define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
|
||||
#define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
|
||||
#define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /**< \brief (USART1) Channel Status Register */
|
||||
#define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /**< \brief (USART1) Receiver Holding Register */
|
||||
#define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
|
||||
#define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
|
||||
#define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
|
||||
#define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
|
||||
#define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
|
||||
#define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /**< \brief (USART1) Number of Errors Register */
|
||||
#define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
|
||||
#define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
|
||||
#define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */
|
||||
#define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */
|
||||
#define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
|
||||
#define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
|
||||
#define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
|
||||
#define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */
|
||||
#define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receiver Holding Register */
|
||||
#define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
|
||||
#define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
|
||||
#define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
|
||||
#define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
|
||||
#define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
|
||||
#define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */
|
||||
#define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
|
||||
#define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
|
||||
#define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
|
||||
#else
|
||||
#define REG_USART1_CR (*(WoReg*)0x40028000U) /**< \brief (USART1) Control Register */
|
||||
#define REG_USART1_MR (*(RwReg*)0x40028004U) /**< \brief (USART1) Mode Register */
|
||||
#define REG_USART1_IER (*(WoReg*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
|
||||
#define REG_USART1_IDR (*(WoReg*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
|
||||
#define REG_USART1_IMR (*(RoReg*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
|
||||
#define REG_USART1_CSR (*(RoReg*)0x40028014U) /**< \brief (USART1) Channel Status Register */
|
||||
#define REG_USART1_RHR (*(RoReg*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */
|
||||
#define REG_USART1_THR (*(WoReg*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */
|
||||
#define REG_USART1_BRGR (*(RwReg*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
|
||||
#define REG_USART1_RTOR (*(RwReg*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
|
||||
#define REG_USART1_TTGR (*(RwReg*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
|
||||
#define REG_USART1_FIDI (*(RwReg*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
|
||||
#define REG_USART1_NER (*(RoReg*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
|
||||
#define REG_USART1_IF (*(RwReg*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
|
||||
#define REG_USART1_WPMR (*(RwReg*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */
|
||||
#define REG_USART1_WPSR (*(RoReg*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_USART1_INSTANCE_ */
|
||||
|
||||
@ -1,11 +1,17 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_WDT_INSTANCE_
|
||||
#define _SAM3N_WDT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for WDT peripheral ========== */
|
||||
#define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /**< \brief (WDT) Control Register */
|
||||
#define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /**< \brief (WDT) Mode Register */
|
||||
#define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /**< \brief (WDT) Status Register */
|
||||
#ifdef __ASSEMBLY__
|
||||
#define REG_WDT_CR (0x400E1450U) /**< \brief (WDT) Control Register */
|
||||
#define REG_WDT_MR (0x400E1454U) /**< \brief (WDT) Mode Register */
|
||||
#define REG_WDT_SR (0x400E1458U) /**< \brief (WDT) Status Register */
|
||||
#else
|
||||
#define REG_WDT_CR (*(WoReg*)0x400E1450U) /**< \brief (WDT) Control Register */
|
||||
#define REG_WDT_MR (*(RwReg*)0x400E1454U) /**< \brief (WDT) Mode Register */
|
||||
#define REG_WDT_SR (*(RoReg*)0x400E1458U) /**< \brief (WDT) Status Register */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* _SAM3N_WDT_INSTANCE_ */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N1A_PIO_
|
||||
#define _SAM3N1A_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N1B_PIO_
|
||||
#define _SAM3N1B_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N1C_PIO_
|
||||
#define _SAM3N1C_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N2A_PIO_
|
||||
#define _SAM3N2A_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N2B_PIO_
|
||||
#define _SAM3N2B_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N2C_PIO_
|
||||
#define _SAM3N2C_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N4A_PIO_
|
||||
#define _SAM3N4A_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N4B_PIO_
|
||||
#define _SAM3N4B_PIO_
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N4C_PIO_
|
||||
#define _SAM3N4C_PIO_
|
||||
|
||||
@ -1,26 +1,26 @@
|
||||
/* %ATMEL_LICENCE% */
|
||||
/* $asf_license$ */
|
||||
|
||||
#ifndef _SAM3N_
|
||||
#define _SAM3N_
|
||||
|
||||
#if defined __sam3n1a__
|
||||
#include "SAM3N1A.h"
|
||||
#elif defined __sam3n1b__
|
||||
#include "SAM3N1B.h"
|
||||
#elif defined __sam3n1c__
|
||||
#include "SAM3N1C.h"
|
||||
#elif defined __sam3n2a__
|
||||
#include "SAM3N2A.h"
|
||||
#elif defined __sam3n2b__
|
||||
#include "SAM3N2B.h"
|
||||
#elif defined __sam3n2c__
|
||||
#include "SAM3N2C.h"
|
||||
#elif defined __sam3n4a__
|
||||
#include "SAM3N4A.h"
|
||||
#elif defined __sam3n4b__
|
||||
#include "SAM3N4B.h"
|
||||
#elif defined __sam3n4c__
|
||||
#include "SAM3N4C.h"
|
||||
#if defined __SAM3N1A__
|
||||
#include "sam3n1a.h"
|
||||
#elif defined __SAM3N1B__
|
||||
#include "sam3n1b.h"
|
||||
#elif defined __SAM3N1C__
|
||||
#include "sam3n1c.h"
|
||||
#elif defined __SAM3N2A__
|
||||
#include "sam3n2a.h"
|
||||
#elif defined __SAM3N2B__
|
||||
#include "sam3n2b.h"
|
||||
#elif defined __SAM3N2C__
|
||||
#include "sam3n2c.h"
|
||||
#elif defined __SAM3N4A__
|
||||
#include "sam3n4a.h"
|
||||
#elif defined __SAM3N4B__
|
||||
#include "sam3n4b.h"
|
||||
#elif defined __SAM3N4C__
|
||||
#include "sam3n4c.h"
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user