mirror of
https://github.com/esp8266/Arduino.git
synced 2025-06-12 01:53:07 +03:00
Allman now (#6080)
* switch restyle script for CI * remove confirmation * restyle with allman
This commit is contained in:
Allman-astyler
committed by
david gauchard
david gauchard
parent
625c3a62c4
commit
98125f8860
@ -2,66 +2,66 @@
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#define GDBSTUB_CFG_H
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/*
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Enable this define if you're using the RTOS SDK. It will use a custom exception handler instead of the HAL
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and do some other magic to make everything work and compile under FreeRTOS.
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Enable this define if you're using the RTOS SDK. It will use a custom exception handler instead of the HAL
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and do some other magic to make everything work and compile under FreeRTOS.
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*/
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#ifndef GDBSTUB_FREERTOS
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#define GDBSTUB_FREERTOS 0
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#endif
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/*
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Enable this to make the exception and debugging handlers switch to a private stack. This will use
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up 1K of RAM, but may be useful if you're debugging stack or stack pointer corruption problems. It's
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normally disabled because not many situations need it. If for some reason the GDB communication
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stops when you run into an error in your code, try enabling this.
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Enable this to make the exception and debugging handlers switch to a private stack. This will use
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up 1K of RAM, but may be useful if you're debugging stack or stack pointer corruption problems. It's
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normally disabled because not many situations need it. If for some reason the GDB communication
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stops when you run into an error in your code, try enabling this.
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*/
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#ifndef GDBSTUB_USE_OWN_STACK
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#define GDBSTUB_USE_OWN_STACK 0
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#endif
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/*
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Enable this to cause the program to pause and wait for gdb to be connected when an exception is
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encountered.
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Enable this to cause the program to pause and wait for gdb to be connected when an exception is
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encountered.
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*/
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#ifndef GDBSTUB_BREAK_ON_EXCEPTION
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#define GDBSTUB_BREAK_ON_EXCEPTION 1
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#endif
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/*
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If this is defined, gdbstub will break the program when you press Ctrl-C in gdb. it does this by
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hooking the UART interrupt. Unfortunately, this means receiving stuff over the serial port won't
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work for your program anymore. This will fail if your program sets an UART interrupt handler after
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the gdbstub_init call.
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If this is defined, gdbstub will break the program when you press Ctrl-C in gdb. it does this by
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hooking the UART interrupt. Unfortunately, this means receiving stuff over the serial port won't
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work for your program anymore. This will fail if your program sets an UART interrupt handler after
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the gdbstub_init call.
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*/
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#ifndef GDBSTUB_CTRLC_BREAK
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#define GDBSTUB_CTRLC_BREAK 1
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#endif
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/*
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Enabling this will redirect console output to GDB. This basically means that printf/os_printf output
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will show up in your gdb session, which is useful if you use gdb to do stuff. It also means that if
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you use a normal terminal, you can't read the printfs anymore.
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Enabling this will redirect console output to GDB. This basically means that printf/os_printf output
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will show up in your gdb session, which is useful if you use gdb to do stuff. It also means that if
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you use a normal terminal, you can't read the printfs anymore.
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*/
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#ifndef GDBSTUB_REDIRECT_CONSOLE_OUTPUT
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#define GDBSTUB_REDIRECT_CONSOLE_OUTPUT 1
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#endif
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/*
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Enable this if you want the GDB stub to wait for you to attach GDB before running. It does this by
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breaking in the init routine; use the gdb 'c' command (continue) to start the program.
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Enable this if you want the GDB stub to wait for you to attach GDB before running. It does this by
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breaking in the init routine; use the gdb 'c' command (continue) to start the program.
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*/
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#ifndef GDBSTUB_BREAK_ON_INIT
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#define GDBSTUB_BREAK_ON_INIT 0
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#endif
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/*
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Function attributes for function types.
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Gdbstub functions are placed in flash or IRAM using attributes, as defined here. The gdbinit function
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(and related) can always be in flash, because it's called in the normal code flow. The rest of the
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gdbstub functions can be in flash too, but only if there's no chance of them being called when the
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flash somehow is disabled (eg during SPI operations or flash write/erase operations). If the routines
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are called when the flash is disabled (eg due to a Ctrl-C at the wrong time), the ESP8266 will most
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likely crash.
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Function attributes for function types.
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Gdbstub functions are placed in flash or IRAM using attributes, as defined here. The gdbinit function
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(and related) can always be in flash, because it's called in the normal code flow. The rest of the
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gdbstub functions can be in flash too, but only if there's no chance of them being called when the
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flash somehow is disabled (eg during SPI operations or flash write/erase operations). If the routines
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are called when the flash is disabled (eg due to a Ctrl-C at the wrong time), the ESP8266 will most
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likely crash.
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*/
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#ifndef ATTR_GDBINIT
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#define ATTR_GDBINIT ICACHE_FLASH_ATTR
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File diff suppressed because it is too large
Load Diff
@ -1,32 +1,32 @@
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/*
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* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
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* processor CORE configuration
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*
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* See <xtensa/config/core.h>, which includes this file, for more details.
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*/
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/*
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xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
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processor CORE configuration
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/* Xtensa processor core configuration information.
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See <xtensa/config/core.h>, which includes this file, for more details.
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*/
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Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
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/* Xtensa processor core configuration information.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
|
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"Software"), to deal in the Software without restriction, including
|
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without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
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Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
|
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|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef _XTENSA_CORE_CONFIGURATION_H
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#define _XTENSA_CORE_CONFIGURATION_H
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@ -37,14 +37,14 @@
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****************************************************************************/
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/*
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* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
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configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
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#define XCHAL_HAVE_WINDOWED 0 /* windowed registers option */
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@ -99,9 +99,9 @@
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#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
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/*----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_WRITEBUFFER_ENTRIES 1 /* size of write buffer */
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#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
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@ -121,8 +121,8 @@
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#define XCHAL_BUILD_UNIQUE_ID 0x0002B6F6 /* 22-bit sw build ID */
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/*
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* These definitions describe the hardware targeted by this software.
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*/
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These definitions describe the hardware targeted by this software.
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*/
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#define XCHAL_HW_CONFIGID0 0xC28CDAFA /* ConfigID hi 32 bits*/
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#define XCHAL_HW_CONFIGID1 0x1082B6F6 /* ConfigID lo 32 bits*/
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#define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */
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@ -142,9 +142,9 @@
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#define XCHAL_HW_MAX_VERSION 230001 /* latest targeted hw */
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/*----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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----------------------------------------------------------------------*/
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#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
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#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
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@ -169,9 +169,9 @@
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#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
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@ -199,9 +199,9 @@
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#define XCHAL_CA_BITS 4
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/*----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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INTERNAL I/D RAM/ROMs and XLMI
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----------------------------------------------------------------------*/
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
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#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
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@ -253,9 +253,9 @@
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#define XCHAL_XLMI0_ECC_PARITY 0
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/*----------------------------------------------------------------------
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/* ----------------------------------------------------------------------
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INTERRUPTS and TIMERS
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----------------------------------------------------------------------*/
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
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#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
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@ -268,7 +268,7 @@
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#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
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(not including level zero) */
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#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
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/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
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/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
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/* Masks of interrupts at each interrupt level: */
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#define XCHAL_INTLEVEL1_MASK 0x00003FFF
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@ -348,13 +348,13 @@
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/*
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* External interrupt vectors/levels.
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* These macros describe how Xtensa processor interrupt numbers
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||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
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* map to external BInterrupt<n> pins, for those interrupts
|
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* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
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External interrupt vectors/levels.
|
||||
These macros describe how Xtensa processor interrupt numbers
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(as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
map to external BInterrupt<n> pins, for those interrupts
|
||||
configured as external (level-triggered, edge-triggered, or NMI).
|
||||
See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
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#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
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@ -372,9 +372,9 @@
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#define XCHAL_EXTINT12_NUM 14 /* (intlevel 3) */
|
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|
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|
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/*----------------------------------------------------------------------
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||||
/* ----------------------------------------------------------------------
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EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
----------------------------------------------------------------------*/
|
||||
|
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#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
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@ -420,9 +420,9 @@
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#define XCHAL_INTLEVEL3_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
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|
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|
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/*----------------------------------------------------------------------
|
||||
/* ----------------------------------------------------------------------
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||||
DEBUG
|
||||
----------------------------------------------------------------------*/
|
||||
----------------------------------------------------------------------*/
|
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|
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#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
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#define XCHAL_NUM_IBREAK 1 /* number of IBREAKn regs */
|
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@ -430,9 +430,9 @@
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#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
|
||||
|
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|
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/*----------------------------------------------------------------------
|
||||
/* ----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
|
||||
@ -1,29 +1,29 @@
|
||||
/*
|
||||
* Xtensa Special Register symbolic names
|
||||
*/
|
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Xtensa Special Register symbolic names
|
||||
*/
|
||||
|
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/* $Id: //depot/rel/Boreal/Xtensa/SWConfig/hal/specreg.h.tpp#2 $ */
|
||||
|
||||
/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef XTENSA_SPECREG_H
|
||||
#define XTENSA_SPECREG_H
|
||||
|
||||
@ -1,34 +1,34 @@
|
||||
/*
|
||||
* xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
|
||||
*
|
||||
* (In previous releases, these were defined in specreg.h, a generated file.
|
||||
* This file is not generated, ie. it is processor configuration independent.)
|
||||
*/
|
||||
xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
|
||||
|
||||
(In previous releases, these were defined in specreg.h, a generated file.
|
||||
This file is not generated, ie. it is processor configuration independent.)
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Boreal/Xtensa/OS/include/xtensa/corebits.h#2 $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005-2007 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
Copyright (c) 2005-2007 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_COREBITS_H
|
||||
#define XTENSA_COREBITS_H
|
||||
@ -38,10 +38,10 @@
|
||||
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
|
||||
/* EXCCAUSE register values: */
|
||||
/*
|
||||
* General Exception Causes
|
||||
* (values of EXCCAUSE special register set by general exceptions,
|
||||
* which vector to the user, kernel, or double-exception vectors).
|
||||
*/
|
||||
General Exception Causes
|
||||
(values of EXCCAUSE special register set by general exceptions,
|
||||
which vector to the user, kernel, or double-exception vectors).
|
||||
*/
|
||||
#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
|
||||
#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
|
||||
#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
|
||||
@ -143,7 +143,7 @@
|
||||
#define MESR_DME_SHIFT 1
|
||||
#define MESR_RCE 0x00000010 /* recorded memory error */
|
||||
#define MESR_RCE_SHIFT 4
|
||||
#define MESR_LCE
|
||||
#define MESR_LCE
|
||||
#define MESR_LCE_SHIFT ?
|
||||
#define MESR_LCE_L
|
||||
#define MESR_ERRENAB 0x00000100
|
||||
|
||||
Reference in New Issue
Block a user