mirror of
https://github.com/esp8266/Arduino.git
synced 2025-06-19 09:42:11 +03:00
Merge branch 'master' into esp8266
* master: (148 commits)
Update revision log
Cherry picked fix from 87865ac19d
Updated revision log
Added dependencies for AStylej.dll
Updated translations
Update revision log
Temporary fix for pulseIn() regression.
Added README.adoc for the library manager project
Fixed some libraries metadata.
Temporary disabled DefaultTargetTest under certain conditions
Updated translation from transifex
Updated some translation strings
Fixed test
sam: Fixed initialization of UART/USART mode register
update revision log
Fixed NPE when import menu are empty
Fixed NPE when currently selected platform is no more installed.
Optimized FileUtils.recursiveDelete(File) function
Fixed a bunch of simple warnings in java code
Removed unused classes Commander.java and Webserver.java
...
This commit is contained in:
Ivan Grokhotkov
@ -114,7 +114,7 @@ typedef unsigned int word;
|
||||
|
||||
#define bit(b) (1UL << (b))
|
||||
|
||||
typedef uint8_t boolean;
|
||||
typedef bool boolean;
|
||||
typedef uint8_t byte;
|
||||
|
||||
void init(void);
|
||||
|
||||
@ -61,9 +61,25 @@ unsigned long pulseIn(uint8_t pin, uint8_t state, unsigned long timeout)
|
||||
width++;
|
||||
}
|
||||
|
||||
// convert the reading to microseconds. The loop has been determined
|
||||
// to be 20 clock cycles long and have about 16 clocks between the edge
|
||||
// and the start of the loop. There will be some error introduced by
|
||||
// convert the reading to microseconds. There will be some error introduced by
|
||||
// the interrupt handlers.
|
||||
return clockCyclesToMicroseconds(width * 21 + 16);
|
||||
|
||||
// Conversion constants are compiler-dependent, different compiler versions
|
||||
// have different levels of optimization.
|
||||
#if __GNUC__==4 && __GNUC_MINOR__==3 && __GNUC_PATCHLEVEL__==2
|
||||
// avr-gcc 4.3.2
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||||
return clockCyclesToMicroseconds(width * 21 + 16);
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||||
#elif __GNUC__==4 && __GNUC_MINOR__==8 && __GNUC_PATCHLEVEL__==1
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||||
// avr-gcc 4.8.1
|
||||
return clockCyclesToMicroseconds(width * 24 + 16);
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||||
#elif __GNUC__<=4 && __GNUC_MINOR__<=3
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||||
// avr-gcc <=4.3.x
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||||
#warning "pulseIn() results may not be accurate"
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||||
return clockCyclesToMicroseconds(width * 21 + 16);
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||||
#else
|
||||
// avr-gcc >4.3.x
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||||
#warning "pulseIn() results may not be accurate"
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||||
return clockCyclesToMicroseconds(width * 24 + 16);
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||||
#endif
|
||||
|
||||
}
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>
|
||||
* Copyright (c) 2014 by Paul Stoffregen <paul@pjrc.com> (Transaction API)
|
||||
* Copyright (c) 2014 by Matthijs Kooijman <matthijs@stdin.nl> (SPISettings AVR)
|
||||
* Copyright (c) 2014 by Andrew J. Kroll <xxxajk@gmail.com> (atomicity fixes)
|
||||
* SPI Master library for arduino.
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
@ -14,6 +15,7 @@
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||||
|
||||
SPIClass SPI;
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||||
|
||||
uint8_t SPIClass::initialized = 0;
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||||
uint8_t SPIClass::interruptMode = 0;
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||||
uint8_t SPIClass::interruptMask = 0;
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||||
uint8_t SPIClass::interruptSave = 0;
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||||
@ -23,32 +25,51 @@ uint8_t SPIClass::inTransactionFlag = 0;
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||||
|
||||
void SPIClass::begin()
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||||
{
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||||
// Set SS to high so a connected chip will be "deselected" by default
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||||
digitalWrite(SS, HIGH);
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||||
uint8_t sreg = SREG;
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||||
noInterrupts(); // Protect from a scheduler and prevent transactionBegin
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||||
if (!initialized) {
|
||||
// Set SS to high so a connected chip will be "deselected" by default
|
||||
digitalWrite(SS, HIGH);
|
||||
|
||||
// When the SS pin is set as OUTPUT, it can be used as
|
||||
// a general purpose output port (it doesn't influence
|
||||
// SPI operations).
|
||||
pinMode(SS, OUTPUT);
|
||||
// When the SS pin is set as OUTPUT, it can be used as
|
||||
// a general purpose output port (it doesn't influence
|
||||
// SPI operations).
|
||||
pinMode(SS, OUTPUT);
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||||
|
||||
// Warning: if the SS pin ever becomes a LOW INPUT then SPI
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||||
// automatically switches to Slave, so the data direction of
|
||||
// the SS pin MUST be kept as OUTPUT.
|
||||
SPCR |= _BV(MSTR);
|
||||
SPCR |= _BV(SPE);
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||||
// Warning: if the SS pin ever becomes a LOW INPUT then SPI
|
||||
// automatically switches to Slave, so the data direction of
|
||||
// the SS pin MUST be kept as OUTPUT.
|
||||
SPCR |= _BV(MSTR);
|
||||
SPCR |= _BV(SPE);
|
||||
|
||||
// Set direction register for SCK and MOSI pin.
|
||||
// MISO pin automatically overrides to INPUT.
|
||||
// By doing this AFTER enabling SPI, we avoid accidentally
|
||||
// clocking in a single bit since the lines go directly
|
||||
// from "input" to SPI control.
|
||||
// http://code.google.com/p/arduino/issues/detail?id=888
|
||||
pinMode(SCK, OUTPUT);
|
||||
pinMode(MOSI, OUTPUT);
|
||||
// Set direction register for SCK and MOSI pin.
|
||||
// MISO pin automatically overrides to INPUT.
|
||||
// By doing this AFTER enabling SPI, we avoid accidentally
|
||||
// clocking in a single bit since the lines go directly
|
||||
// from "input" to SPI control.
|
||||
// http://code.google.com/p/arduino/issues/detail?id=888
|
||||
pinMode(SCK, OUTPUT);
|
||||
pinMode(MOSI, OUTPUT);
|
||||
}
|
||||
initialized++; // reference count
|
||||
SREG = sreg;
|
||||
}
|
||||
|
||||
void SPIClass::end() {
|
||||
SPCR &= ~_BV(SPE);
|
||||
uint8_t sreg = SREG;
|
||||
noInterrupts(); // Protect from a scheduler and prevent transactionBegin
|
||||
// Decrease the reference counter
|
||||
if (initialized)
|
||||
initialized--;
|
||||
// If there are no more references disable SPI
|
||||
if (!initialized) {
|
||||
SPCR &= ~_BV(SPE);
|
||||
interruptMode = 0;
|
||||
#ifdef SPI_TRANSACTION_MISMATCH_LED
|
||||
inTransactionFlag = 0;
|
||||
#endif
|
||||
}
|
||||
SREG = sreg;
|
||||
}
|
||||
|
||||
// mapping of interrupt numbers to bits within SPI_AVR_EIMSK
|
||||
@ -90,11 +111,9 @@ void SPIClass::end() {
|
||||
|
||||
void SPIClass::usingInterrupt(uint8_t interruptNumber)
|
||||
{
|
||||
uint8_t mask;
|
||||
|
||||
if (interruptMode > 1) return;
|
||||
|
||||
noInterrupts();
|
||||
uint8_t mask = 0;
|
||||
uint8_t sreg = SREG;
|
||||
noInterrupts(); // Protect from a scheduler and prevent transactionBegin
|
||||
switch (interruptNumber) {
|
||||
#ifdef SPI_INT0_MASK
|
||||
case 0: mask = SPI_INT0_MASK; break;
|
||||
@ -122,11 +141,53 @@ void SPIClass::usingInterrupt(uint8_t interruptNumber)
|
||||
#endif
|
||||
default:
|
||||
interruptMode = 2;
|
||||
interrupts();
|
||||
return;
|
||||
break;
|
||||
}
|
||||
interruptMode = 1;
|
||||
interruptMask |= mask;
|
||||
interrupts();
|
||||
if (!interruptMode)
|
||||
interruptMode = 1;
|
||||
SREG = sreg;
|
||||
}
|
||||
|
||||
void SPIClass::notUsingInterrupt(uint8_t interruptNumber)
|
||||
{
|
||||
// Once in mode 2 we can't go back to 0 without a proper reference count
|
||||
if (interruptMode == 2)
|
||||
return;
|
||||
uint8_t mask = 0;
|
||||
uint8_t sreg = SREG;
|
||||
noInterrupts(); // Protect from a scheduler and prevent transactionBegin
|
||||
switch (interruptNumber) {
|
||||
#ifdef SPI_INT0_MASK
|
||||
case 0: mask = SPI_INT0_MASK; break;
|
||||
#endif
|
||||
#ifdef SPI_INT1_MASK
|
||||
case 1: mask = SPI_INT1_MASK; break;
|
||||
#endif
|
||||
#ifdef SPI_INT2_MASK
|
||||
case 2: mask = SPI_INT2_MASK; break;
|
||||
#endif
|
||||
#ifdef SPI_INT3_MASK
|
||||
case 3: mask = SPI_INT3_MASK; break;
|
||||
#endif
|
||||
#ifdef SPI_INT4_MASK
|
||||
case 4: mask = SPI_INT4_MASK; break;
|
||||
#endif
|
||||
#ifdef SPI_INT5_MASK
|
||||
case 5: mask = SPI_INT5_MASK; break;
|
||||
#endif
|
||||
#ifdef SPI_INT6_MASK
|
||||
case 6: mask = SPI_INT6_MASK; break;
|
||||
#endif
|
||||
#ifdef SPI_INT7_MASK
|
||||
case 7: mask = SPI_INT7_MASK; break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
// this case can't be reached
|
||||
}
|
||||
interruptMask &= ~mask;
|
||||
if (!interruptMask)
|
||||
interruptMode = 0;
|
||||
SREG = sreg;
|
||||
}
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
* Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st>
|
||||
* Copyright (c) 2014 by Paul Stoffregen <paul@pjrc.com> (Transaction API)
|
||||
* Copyright (c) 2014 by Matthijs Kooijman <matthijs@stdin.nl> (SPISettings AVR)
|
||||
* Copyright (c) 2014 by Andrew J. Kroll <xxxajk@gmail.com> (atomicity fixes)
|
||||
* SPI Master library for arduino.
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
@ -19,6 +20,16 @@
|
||||
// usingInterrupt(), and SPISetting(clock, bitOrder, dataMode)
|
||||
#define SPI_HAS_TRANSACTION 1
|
||||
|
||||
// SPI_HAS_NOTUSINGINTERRUPT means that SPI has notUsingInterrupt() method
|
||||
#define SPI_HAS_NOTUSINGINTERRUPT 1
|
||||
|
||||
// SPI_ATOMIC_VERSION means that SPI has atomicity fixes and what version.
|
||||
// This way when there is a bug fix you can check this define to alert users
|
||||
// of your code if it uses better version of this library.
|
||||
// This also implies everything that SPI_HAS_TRANSACTION as documented above is
|
||||
// available too.
|
||||
#define SPI_ATOMIC_VERSION 1
|
||||
|
||||
// Uncomment this line to add detection of mismatched begin/end transactions.
|
||||
// A mismatch occurs if other libraries fail to use SPI.endTransaction() for
|
||||
// each SPI.beginTransaction(). Connect an LED to this pin. The LED will turn
|
||||
@ -153,23 +164,34 @@ public:
|
||||
// with attachInterrupt. If SPI is used from a different interrupt
|
||||
// (eg, a timer), interruptNumber should be 255.
|
||||
static void usingInterrupt(uint8_t interruptNumber);
|
||||
// And this does the opposite.
|
||||
static void notUsingInterrupt(uint8_t interruptNumber);
|
||||
// Note: the usingInterrupt and notUsingInterrupt functions should
|
||||
// not to be called from ISR context or inside a transaction.
|
||||
// For details see:
|
||||
// https://github.com/arduino/Arduino/pull/2381
|
||||
// https://github.com/arduino/Arduino/pull/2449
|
||||
|
||||
// Before using SPI.transfer() or asserting chip select pins,
|
||||
// this function is used to gain exclusive access to the SPI bus
|
||||
// and configure the correct settings.
|
||||
inline static void beginTransaction(SPISettings settings) {
|
||||
if (interruptMode > 0) {
|
||||
uint8_t sreg = SREG;
|
||||
noInterrupts();
|
||||
|
||||
#ifdef SPI_AVR_EIMSK
|
||||
if (interruptMode == 1) {
|
||||
interruptSave = SPI_AVR_EIMSK;
|
||||
SPI_AVR_EIMSK &= ~interruptMask;
|
||||
SREG = sreg;
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
interruptSave = SREG;
|
||||
cli();
|
||||
interruptSave = sreg;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef SPI_TRANSACTION_MISMATCH_LED
|
||||
if (inTransactionFlag) {
|
||||
pinMode(SPI_TRANSACTION_MISMATCH_LED, OUTPUT);
|
||||
@ -177,6 +199,7 @@ public:
|
||||
}
|
||||
inTransactionFlag = 1;
|
||||
#endif
|
||||
|
||||
SPCR = settings.spcr;
|
||||
SPSR = settings.spsr;
|
||||
}
|
||||
@ -184,6 +207,12 @@ public:
|
||||
// Write to the SPI bus (MOSI pin) and also receive (MISO pin)
|
||||
inline static uint8_t transfer(uint8_t data) {
|
||||
SPDR = data;
|
||||
/*
|
||||
* The following NOP introduces a small delay that can prevent the wait
|
||||
* loop form iterating when running at the maximum speed. This gives
|
||||
* about 10% more speed, even if it seems counter-intuitive. At lower
|
||||
* speeds it is unnoticed.
|
||||
*/
|
||||
asm volatile("nop");
|
||||
while (!(SPSR & _BV(SPIF))) ; // wait
|
||||
return SPDR;
|
||||
@ -193,16 +222,20 @@ public:
|
||||
in.val = data;
|
||||
if (!(SPCR & _BV(DORD))) {
|
||||
SPDR = in.msb;
|
||||
asm volatile("nop"); // See transfer(uint8_t) function
|
||||
while (!(SPSR & _BV(SPIF))) ;
|
||||
out.msb = SPDR;
|
||||
SPDR = in.lsb;
|
||||
asm volatile("nop");
|
||||
while (!(SPSR & _BV(SPIF))) ;
|
||||
out.lsb = SPDR;
|
||||
} else {
|
||||
SPDR = in.lsb;
|
||||
asm volatile("nop");
|
||||
while (!(SPSR & _BV(SPIF))) ;
|
||||
out.lsb = SPDR;
|
||||
SPDR = in.msb;
|
||||
asm volatile("nop");
|
||||
while (!(SPSR & _BV(SPIF))) ;
|
||||
out.msb = SPDR;
|
||||
}
|
||||
@ -232,10 +265,16 @@ public:
|
||||
}
|
||||
inTransactionFlag = 0;
|
||||
#endif
|
||||
|
||||
if (interruptMode > 0) {
|
||||
#ifdef SPI_AVR_EIMSK
|
||||
uint8_t sreg = SREG;
|
||||
#endif
|
||||
noInterrupts();
|
||||
#ifdef SPI_AVR_EIMSK
|
||||
if (interruptMode == 1) {
|
||||
SPI_AVR_EIMSK = interruptSave;
|
||||
SREG = sreg;
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
@ -271,6 +310,7 @@ public:
|
||||
inline static void detachInterrupt() { SPCR &= ~_BV(SPIE); }
|
||||
|
||||
private:
|
||||
static uint8_t initialized;
|
||||
static uint8_t interruptMode; // 0=none, 1=mask, 2=global
|
||||
static uint8_t interruptMask; // which interrupts to mask
|
||||
static uint8_t interruptSave; // temp storage, to restore state
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
# https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification
|
||||
|
||||
name=Arduino AVR Boards
|
||||
version=1.5.8
|
||||
version=1.6.0
|
||||
|
||||
# AVR compile variables
|
||||
# ---------------------
|
||||
|
||||
@ -4,5 +4,6 @@ author=Arduino
|
||||
maintainer=Arduino <info@arduino.cc>
|
||||
sentence=Enables network connection (local and Internet) using the Arduino WiFi shield. For all Arduino boards.
|
||||
paragraph=With this library you can instantiate Servers, Clients and send/receive UDP packets through WiFi. The shield can connect either to open or encrypted networks (WEP, WPA). The IP address can be assigned statically or through a DHCP. The library can also manage DNS.
|
||||
category=Communication
|
||||
url=http://arduino.cc/en/Reference/WiFi
|
||||
architectures=*
|
||||
|
||||
@ -21,7 +21,7 @@
|
||||
|
||||
RingBuffer::RingBuffer( void )
|
||||
{
|
||||
memset( _aucBuffer, 0, SERIAL_BUFFER_SIZE ) ;
|
||||
memset( (void *)_aucBuffer, 0, SERIAL_BUFFER_SIZE ) ;
|
||||
_iHead=0 ;
|
||||
_iTail=0 ;
|
||||
}
|
||||
|
||||
@ -25,14 +25,14 @@
|
||||
// using a ring buffer (I think), in which head is the index of the location
|
||||
// to which to write the next incoming character and tail is the index of the
|
||||
// location from which to read.
|
||||
#define SERIAL_BUFFER_SIZE 64
|
||||
#define SERIAL_BUFFER_SIZE 128
|
||||
|
||||
class RingBuffer
|
||||
{
|
||||
public:
|
||||
uint8_t _aucBuffer[SERIAL_BUFFER_SIZE] ;
|
||||
int _iHead ;
|
||||
int _iTail ;
|
||||
volatile uint8_t _aucBuffer[SERIAL_BUFFER_SIZE] ;
|
||||
volatile int _iHead ;
|
||||
volatile int _iTail ;
|
||||
|
||||
public:
|
||||
RingBuffer( void ) ;
|
||||
|
||||
@ -23,33 +23,45 @@
|
||||
|
||||
// Constructors ////////////////////////////////////////////////////////////////
|
||||
|
||||
UARTClass::UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer )
|
||||
UARTClass::UARTClass( Uart *pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer *pRx_buffer, RingBuffer *pTx_buffer )
|
||||
{
|
||||
_rx_buffer = pRx_buffer ;
|
||||
_rx_buffer = pRx_buffer;
|
||||
_tx_buffer = pTx_buffer;
|
||||
|
||||
_pUart=pUart ;
|
||||
_dwIrq=dwIrq ;
|
||||
_dwId=dwId ;
|
||||
_pUart=pUart;
|
||||
_dwIrq=dwIrq;
|
||||
_dwId=dwId;
|
||||
}
|
||||
|
||||
// Public Methods //////////////////////////////////////////////////////////////
|
||||
|
||||
void UARTClass::begin( const uint32_t dwBaudRate )
|
||||
void UARTClass::begin(const uint32_t dwBaudRate)
|
||||
{
|
||||
begin(dwBaudRate, Mode_8N1);
|
||||
}
|
||||
|
||||
void UARTClass::begin(const uint32_t dwBaudRate, const UARTModes config)
|
||||
{
|
||||
uint32_t modeReg = static_cast<uint32_t>(config) & 0x00000E00;
|
||||
init(dwBaudRate, modeReg | UART_MR_CHMODE_NORMAL);
|
||||
}
|
||||
|
||||
void UARTClass::init(const uint32_t dwBaudRate, const uint32_t modeReg)
|
||||
{
|
||||
// Configure PMC
|
||||
pmc_enable_periph_clk( _dwId ) ;
|
||||
pmc_enable_periph_clk( _dwId );
|
||||
|
||||
// Disable PDC channel
|
||||
_pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS ;
|
||||
_pUart->UART_PTCR = UART_PTCR_RXTDIS | UART_PTCR_TXTDIS;
|
||||
|
||||
// Reset and disable receiver and transmitter
|
||||
_pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS ;
|
||||
_pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | UART_CR_TXDIS;
|
||||
|
||||
// Configure mode
|
||||
_pUart->UART_MR = UART_MR_PAR_NO | UART_MR_CHMODE_NORMAL ;
|
||||
_pUart->UART_MR = modeReg;
|
||||
|
||||
// Configure baudrate (asynchronous, no oversampling)
|
||||
_pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4 ;
|
||||
_pUart->UART_BRGR = (SystemCoreClock / dwBaudRate) >> 4;
|
||||
|
||||
// Configure interrupts
|
||||
_pUart->UART_IDR = 0xFFFFFFFF;
|
||||
@ -58,63 +70,99 @@ void UARTClass::begin( const uint32_t dwBaudRate )
|
||||
// Enable UART interrupt in NVIC
|
||||
NVIC_EnableIRQ(_dwIrq);
|
||||
|
||||
// Make sure both ring buffers are initialized back to empty.
|
||||
_rx_buffer->_iHead = _rx_buffer->_iTail = 0;
|
||||
_tx_buffer->_iHead = _tx_buffer->_iTail = 0;
|
||||
|
||||
// Enable receiver and transmitter
|
||||
_pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN ;
|
||||
_pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN;
|
||||
}
|
||||
|
||||
void UARTClass::end( void )
|
||||
{
|
||||
// clear any received data
|
||||
_rx_buffer->_iHead = _rx_buffer->_iTail ;
|
||||
|
||||
// Disable UART interrupt in NVIC
|
||||
NVIC_DisableIRQ( _dwIrq ) ;
|
||||
// Clear any received data
|
||||
_rx_buffer->_iHead = _rx_buffer->_iTail;
|
||||
|
||||
// Wait for any outstanding data to be sent
|
||||
flush();
|
||||
|
||||
pmc_disable_periph_clk( _dwId ) ;
|
||||
// Disable UART interrupt in NVIC
|
||||
NVIC_DisableIRQ( _dwIrq );
|
||||
|
||||
pmc_disable_periph_clk( _dwId );
|
||||
}
|
||||
|
||||
void UARTClass::setInterruptPriority(uint32_t priority)
|
||||
{
|
||||
NVIC_SetPriority(_dwIrq, priority & 0x0F);
|
||||
}
|
||||
|
||||
uint32_t UARTClass::getInterruptPriority()
|
||||
{
|
||||
return NVIC_GetPriority(_dwIrq);
|
||||
}
|
||||
|
||||
int UARTClass::available( void )
|
||||
{
|
||||
return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ;
|
||||
return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE;
|
||||
}
|
||||
|
||||
int UARTClass::availableForWrite(void)
|
||||
{
|
||||
int head = _tx_buffer->_iHead;
|
||||
int tail = _tx_buffer->_iTail;
|
||||
if (head >= tail) return SERIAL_BUFFER_SIZE - 1 - head + tail;
|
||||
return tail - head - 1;
|
||||
}
|
||||
|
||||
int UARTClass::peek( void )
|
||||
{
|
||||
if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
|
||||
return -1 ;
|
||||
return -1;
|
||||
|
||||
return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
|
||||
return _rx_buffer->_aucBuffer[_rx_buffer->_iTail];
|
||||
}
|
||||
|
||||
int UARTClass::read( void )
|
||||
{
|
||||
// if the head isn't ahead of the tail, we don't have any characters
|
||||
if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
|
||||
return -1 ;
|
||||
return -1;
|
||||
|
||||
uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
|
||||
_rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ;
|
||||
return uc ;
|
||||
uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail];
|
||||
_rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE;
|
||||
return uc;
|
||||
}
|
||||
|
||||
void UARTClass::flush( void )
|
||||
{
|
||||
while (_tx_buffer->_iHead != _tx_buffer->_iTail); //wait for transmit data to be sent
|
||||
// Wait for transmission to complete
|
||||
while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
|
||||
;
|
||||
;
|
||||
}
|
||||
|
||||
size_t UARTClass::write( const uint8_t uc_data )
|
||||
{
|
||||
// Check if the transmitter is ready
|
||||
while ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY)
|
||||
;
|
||||
// Is the hardware currently busy?
|
||||
if (((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) |
|
||||
(_tx_buffer->_iTail != _tx_buffer->_iHead))
|
||||
{
|
||||
// If busy we buffer
|
||||
unsigned int l = (_tx_buffer->_iHead + 1) % SERIAL_BUFFER_SIZE;
|
||||
while (_tx_buffer->_iTail == l)
|
||||
; // Spin locks if we're about to overwrite the buffer. This continues once the data is sent
|
||||
|
||||
// Send character
|
||||
_pUart->UART_THR = uc_data;
|
||||
_tx_buffer->_aucBuffer[_tx_buffer->_iHead] = uc_data;
|
||||
_tx_buffer->_iHead = l;
|
||||
// Make sure TX interrupt is enabled
|
||||
_pUart->UART_IER = UART_IER_TXRDY;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Bypass buffering and send character directly
|
||||
_pUart->UART_THR = uc_data;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
@ -122,15 +170,28 @@ void UARTClass::IrqHandler( void )
|
||||
{
|
||||
uint32_t status = _pUart->UART_SR;
|
||||
|
||||
// Did we receive data ?
|
||||
// Did we receive data?
|
||||
if ((status & UART_SR_RXRDY) == UART_SR_RXRDY)
|
||||
_rx_buffer->store_char(_pUart->UART_RHR);
|
||||
|
||||
// Acknowledge errors
|
||||
if ((status & UART_SR_OVRE) == UART_SR_OVRE ||
|
||||
(status & UART_SR_FRAME) == UART_SR_FRAME)
|
||||
// Do we need to keep sending data?
|
||||
if ((status & UART_SR_TXRDY) == UART_SR_TXRDY)
|
||||
{
|
||||
// TODO: error reporting outside ISR
|
||||
if (_tx_buffer->_iTail != _tx_buffer->_iHead) {
|
||||
_pUart->UART_THR = _tx_buffer->_aucBuffer[_tx_buffer->_iTail];
|
||||
_tx_buffer->_iTail = (unsigned int)(_tx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Mask off transmit interrupt so we don't get it anymore
|
||||
_pUart->UART_IDR = UART_IDR_TXRDY;
|
||||
}
|
||||
}
|
||||
|
||||
// Acknowledge errors
|
||||
if ((status & UART_SR_OVRE) == UART_SR_OVRE || (status & UART_SR_FRAME) == UART_SR_FRAME)
|
||||
{
|
||||
// TODO: error reporting outside ISR
|
||||
_pUart->UART_CR |= UART_CR_RSTSTA;
|
||||
}
|
||||
}
|
||||
|
||||
@ -25,37 +25,53 @@
|
||||
// Includes Atmel CMSIS
|
||||
#include <chip.h>
|
||||
|
||||
#define SERIAL_8N1 UARTClass::Mode_8N1
|
||||
#define SERIAL_8E1 UARTClass::Mode_8E1
|
||||
#define SERIAL_8O1 UARTClass::Mode_8O1
|
||||
#define SERIAL_8M1 UARTClass::Mode_8M1
|
||||
#define SERIAL_8S1 UARTClass::Mode_8S1
|
||||
|
||||
|
||||
class UARTClass : public HardwareSerial
|
||||
{
|
||||
protected:
|
||||
RingBuffer *_rx_buffer ;
|
||||
|
||||
protected:
|
||||
Uart* _pUart ;
|
||||
IRQn_Type _dwIrq ;
|
||||
uint32_t _dwId ;
|
||||
|
||||
public:
|
||||
UARTClass( Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ;
|
||||
enum UARTModes {
|
||||
Mode_8N1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_NO,
|
||||
Mode_8E1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_EVEN,
|
||||
Mode_8O1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_ODD,
|
||||
Mode_8M1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_MARK,
|
||||
Mode_8S1 = US_MR_CHRL_8_BIT | US_MR_NBSTOP_1_BIT | UART_MR_PAR_SPACE,
|
||||
};
|
||||
UARTClass(Uart* pUart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer);
|
||||
|
||||
void begin( const uint32_t dwBaudRate ) ;
|
||||
void end( void ) ;
|
||||
int available( void ) ;
|
||||
int peek( void ) ;
|
||||
int read( void ) ;
|
||||
void flush( void ) ;
|
||||
size_t write( const uint8_t c ) ;
|
||||
void begin(const uint32_t dwBaudRate);
|
||||
void begin(const uint32_t dwBaudRate, const UARTModes config);
|
||||
void end(void);
|
||||
int available(void);
|
||||
int availableForWrite(void);
|
||||
int peek(void);
|
||||
int read(void);
|
||||
void flush(void);
|
||||
size_t write(const uint8_t c);
|
||||
using Print::write; // pull in write(str) and write(buf, size) from Print
|
||||
|
||||
void IrqHandler( void ) ;
|
||||
void setInterruptPriority(uint32_t priority);
|
||||
uint32_t getInterruptPriority();
|
||||
|
||||
#if defined __GNUC__ /* GCC CS3 */
|
||||
using Print::write ; // pull in write(str) and write(buf, size) from Print
|
||||
#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */
|
||||
// virtual void write( const char *str ) ;
|
||||
// virtual void write( const uint8_t *buffer, size_t size ) ;
|
||||
#endif
|
||||
void IrqHandler(void);
|
||||
|
||||
operator bool() { return true; }; // UART always active
|
||||
|
||||
protected:
|
||||
void init(const uint32_t dwBaudRate, const uint32_t config);
|
||||
|
||||
RingBuffer *_rx_buffer;
|
||||
RingBuffer *_tx_buffer;
|
||||
|
||||
Uart* _pUart;
|
||||
IRQn_Type _dwIrq;
|
||||
uint32_t _dwId;
|
||||
|
||||
};
|
||||
|
||||
#endif // _UART_CLASS_
|
||||
|
||||
@ -23,121 +23,31 @@
|
||||
|
||||
// Constructors ////////////////////////////////////////////////////////////////
|
||||
|
||||
USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer )
|
||||
USARTClass::USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer )
|
||||
: UARTClass((Uart*)pUsart, dwIrq, dwId, pRx_buffer, pTx_buffer)
|
||||
{
|
||||
_rx_buffer = pRx_buffer ;
|
||||
|
||||
_pUsart=pUsart ;
|
||||
_dwIrq=dwIrq ;
|
||||
_dwId=dwId ;
|
||||
// In case anyone needs USART specific functionality in the future
|
||||
_pUsart=pUsart;
|
||||
}
|
||||
|
||||
// Public Methods //////////////////////////////////////////////////////////////
|
||||
|
||||
void USARTClass::begin( const uint32_t dwBaudRate )
|
||||
void USARTClass::begin(const uint32_t dwBaudRate)
|
||||
{
|
||||
begin( dwBaudRate, SERIAL_8N1 );
|
||||
begin(dwBaudRate, Mode_8N1);
|
||||
}
|
||||
|
||||
void USARTClass::begin( const uint32_t dwBaudRate, const uint32_t config )
|
||||
void USARTClass::begin(const uint32_t dwBaudRate, const UARTModes config)
|
||||
{
|
||||
// Configure PMC
|
||||
pmc_enable_periph_clk( _dwId ) ;
|
||||
|
||||
// Disable PDC channel
|
||||
_pUsart->US_PTCR = US_PTCR_RXTDIS | US_PTCR_TXTDIS ;
|
||||
|
||||
// Reset and disable receiver and transmitter
|
||||
_pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RXDIS | US_CR_TXDIS ;
|
||||
|
||||
// Configure mode
|
||||
_pUsart->US_MR = config;
|
||||
|
||||
|
||||
// Configure baudrate, asynchronous no oversampling
|
||||
_pUsart->US_BRGR = (SystemCoreClock / dwBaudRate) / 16 ;
|
||||
|
||||
// Configure interrupts
|
||||
_pUsart->US_IDR = 0xFFFFFFFF;
|
||||
_pUsart->US_IER = US_IER_RXRDY | US_IER_OVRE | US_IER_FRAME;
|
||||
|
||||
// Enable UART interrupt in NVIC
|
||||
NVIC_EnableIRQ( _dwIrq ) ;
|
||||
|
||||
// Enable receiver and transmitter
|
||||
_pUsart->US_CR = US_CR_RXEN | US_CR_TXEN ;
|
||||
uint32_t modeReg = static_cast<uint32_t>(config);
|
||||
modeReg |= US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHMODE_NORMAL;
|
||||
init(dwBaudRate, modeReg);
|
||||
}
|
||||
|
||||
void USARTClass::end( void )
|
||||
void USARTClass::begin(const uint32_t dwBaudRate, const USARTModes config)
|
||||
{
|
||||
// clear any received data
|
||||
_rx_buffer->_iHead = _rx_buffer->_iTail ;
|
||||
|
||||
// Disable UART interrupt in NVIC
|
||||
NVIC_DisableIRQ( _dwIrq ) ;
|
||||
|
||||
// Wait for any outstanding data to be sent
|
||||
flush();
|
||||
|
||||
pmc_disable_periph_clk( _dwId ) ;
|
||||
}
|
||||
|
||||
int USARTClass::available( void )
|
||||
{
|
||||
return (uint32_t)(SERIAL_BUFFER_SIZE + _rx_buffer->_iHead - _rx_buffer->_iTail) % SERIAL_BUFFER_SIZE ;
|
||||
}
|
||||
|
||||
int USARTClass::peek( void )
|
||||
{
|
||||
if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
|
||||
return -1 ;
|
||||
|
||||
return _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
|
||||
}
|
||||
|
||||
int USARTClass::read( void )
|
||||
{
|
||||
// if the head isn't ahead of the tail, we don't have any characters
|
||||
if ( _rx_buffer->_iHead == _rx_buffer->_iTail )
|
||||
return -1 ;
|
||||
|
||||
uint8_t uc = _rx_buffer->_aucBuffer[_rx_buffer->_iTail] ;
|
||||
_rx_buffer->_iTail = (unsigned int)(_rx_buffer->_iTail + 1) % SERIAL_BUFFER_SIZE ;
|
||||
return uc ;
|
||||
}
|
||||
|
||||
void USARTClass::flush( void )
|
||||
{
|
||||
// Wait for transmission to complete
|
||||
while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)
|
||||
;
|
||||
}
|
||||
|
||||
size_t USARTClass::write( const uint8_t uc_data )
|
||||
{
|
||||
// Check if the transmitter is ready
|
||||
while ((_pUsart->US_CSR & US_CSR_TXRDY) != US_CSR_TXRDY)
|
||||
;
|
||||
|
||||
// Send character
|
||||
_pUsart->US_THR = uc_data ;
|
||||
return 1;
|
||||
}
|
||||
|
||||
void USARTClass::IrqHandler( void )
|
||||
{
|
||||
uint32_t status = _pUsart->US_CSR;
|
||||
|
||||
// Did we receive data ?
|
||||
if ((status & US_CSR_RXRDY) == US_CSR_RXRDY)
|
||||
_rx_buffer->store_char( _pUsart->US_RHR ) ;
|
||||
|
||||
// Acknowledge errors
|
||||
if ((status & US_CSR_OVRE) == US_CSR_OVRE ||
|
||||
(status & US_CSR_FRAME) == US_CSR_FRAME)
|
||||
{
|
||||
// TODO: error reporting outside ISR
|
||||
_pUsart->US_CR |= US_CR_RSTSTA;
|
||||
}
|
||||
uint32_t modeReg = static_cast<uint32_t>(config);
|
||||
modeReg |= US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHMODE_NORMAL;
|
||||
init(dwBaudRate, modeReg);
|
||||
}
|
||||
|
||||
|
||||
@ -19,75 +19,100 @@
|
||||
#ifndef _USART_CLASS_
|
||||
#define _USART_CLASS_
|
||||
|
||||
#include "HardwareSerial.h"
|
||||
#include "UARTClass.h"
|
||||
#include "RingBuffer.h"
|
||||
|
||||
// Includes Atmel CMSIS
|
||||
#include <chip.h>
|
||||
|
||||
// Define config for Serial.begin(baud, config);
|
||||
#define SERIAL_5N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_6N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_7N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_8N1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_5N1 USARTClass::Mode_5N1
|
||||
#define SERIAL_6N1 USARTClass::Mode_6N1
|
||||
#define SERIAL_7N1 USARTClass::Mode_7N1
|
||||
#define SERIAL_5N2 USARTClass::Mode_5N2
|
||||
#define SERIAL_6N2 USARTClass::Mode_6N2
|
||||
#define SERIAL_7N2 USARTClass::Mode_7N2
|
||||
#define SERIAL_8N2 USARTClass::Mode_8N2
|
||||
#define SERIAL_5E1 USARTClass::Mode_5E1
|
||||
#define SERIAL_6E1 USARTClass::Mode_6E1
|
||||
#define SERIAL_7E1 USARTClass::Mode_7E1
|
||||
#define SERIAL_5E2 USARTClass::Mode_5E2
|
||||
#define SERIAL_6E2 USARTClass::Mode_6E2
|
||||
#define SERIAL_7E2 USARTClass::Mode_7E2
|
||||
#define SERIAL_8E2 USARTClass::Mode_8E2
|
||||
#define SERIAL_5O1 USARTClass::Mode_5O1
|
||||
#define SERIAL_6O1 USARTClass::Mode_6O1
|
||||
#define SERIAL_7O1 USARTClass::Mode_7O1
|
||||
#define SERIAL_5O2 USARTClass::Mode_5O2
|
||||
#define SERIAL_6O2 USARTClass::Mode_6O2
|
||||
#define SERIAL_7O2 USARTClass::Mode_7O2
|
||||
#define SERIAL_8O2 USARTClass::Mode_8O2
|
||||
#define SERIAL_5M1 USARTClass::Mode_5M1
|
||||
#define SERIAL_6M1 USARTClass::Mode_6M1
|
||||
#define SERIAL_7M1 USARTClass::Mode_7M1
|
||||
#define SERIAL_5M2 USARTClass::Mode_5M2
|
||||
#define SERIAL_6M2 USARTClass::Mode_6M2
|
||||
#define SERIAL_7M2 USARTClass::Mode_7M2
|
||||
#define SERIAL_8M2 USARTClass::Mode_8M2
|
||||
#define SERIAL_5S1 USARTClass::Mode_5S1
|
||||
#define SERIAL_6S1 USARTClass::Mode_6S1
|
||||
#define SERIAL_7S1 USARTClass::Mode_7S1
|
||||
#define SERIAL_5S2 USARTClass::Mode_5S2
|
||||
#define SERIAL_6S2 USARTClass::Mode_6S2
|
||||
#define SERIAL_7S2 USARTClass::Mode_7S2
|
||||
#define SERIAL_8S2 USARTClass::Mode_8S2
|
||||
|
||||
#define SERIAL_5N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_6N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_7N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_8N2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
|
||||
#define SERIAL_5E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_6E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_7E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_8E1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
|
||||
#define SERIAL_5E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_6E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_7E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_8E2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
|
||||
#define SERIAL_5O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_6O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_7O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_8O1 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT | US_MR_CHMODE_NORMAL)
|
||||
|
||||
#define SERIAL_5O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_6O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_7O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
#define SERIAL_8O2 (US_MR_USART_MODE_NORMAL | US_MR_USCLKS_MCK | US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT | US_MR_CHMODE_NORMAL)
|
||||
|
||||
class USARTClass : public HardwareSerial
|
||||
class USARTClass : public UARTClass
|
||||
{
|
||||
protected:
|
||||
RingBuffer *_rx_buffer ;
|
||||
|
||||
protected:
|
||||
Usart* _pUsart ;
|
||||
IRQn_Type _dwIrq ;
|
||||
uint32_t _dwId ;
|
||||
|
||||
public:
|
||||
USARTClass( Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer ) ;
|
||||
// 8x1 bit modes are inherited from UARTClass
|
||||
enum USARTModes {
|
||||
Mode_5N1 = US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
|
||||
Mode_6N1 = US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
|
||||
Mode_7N1 = US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_1_BIT,
|
||||
Mode_5N2 = US_MR_CHRL_5_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
|
||||
Mode_6N2 = US_MR_CHRL_6_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
|
||||
Mode_7N2 = US_MR_CHRL_7_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
|
||||
Mode_8N2 = US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_NBSTOP_2_BIT,
|
||||
Mode_5E1 = US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
|
||||
Mode_6E1 = US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
|
||||
Mode_7E1 = US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_1_BIT,
|
||||
Mode_5E2 = US_MR_CHRL_5_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
|
||||
Mode_6E2 = US_MR_CHRL_6_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
|
||||
Mode_7E2 = US_MR_CHRL_7_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
|
||||
Mode_8E2 = US_MR_CHRL_8_BIT | US_MR_PAR_EVEN | US_MR_NBSTOP_2_BIT,
|
||||
Mode_5O1 = US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
|
||||
Mode_6O1 = US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
|
||||
Mode_7O1 = US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_1_BIT,
|
||||
Mode_5O2 = US_MR_CHRL_5_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
|
||||
Mode_6O2 = US_MR_CHRL_6_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
|
||||
Mode_7O2 = US_MR_CHRL_7_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
|
||||
Mode_8O2 = US_MR_CHRL_8_BIT | US_MR_PAR_ODD | US_MR_NBSTOP_2_BIT,
|
||||
Mode_5M1 = US_MR_CHRL_5_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
|
||||
Mode_6M1 = US_MR_CHRL_6_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
|
||||
Mode_7M1 = US_MR_CHRL_7_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_1_BIT,
|
||||
Mode_5M2 = US_MR_CHRL_5_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
|
||||
Mode_6M2 = US_MR_CHRL_6_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
|
||||
Mode_7M2 = US_MR_CHRL_7_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
|
||||
Mode_8M2 = US_MR_CHRL_8_BIT | US_MR_PAR_MARK | US_MR_NBSTOP_2_BIT,
|
||||
Mode_5S1 = US_MR_CHRL_5_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
|
||||
Mode_6S1 = US_MR_CHRL_6_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
|
||||
Mode_7S1 = US_MR_CHRL_7_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_1_BIT,
|
||||
Mode_5S2 = US_MR_CHRL_5_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
|
||||
Mode_6S2 = US_MR_CHRL_6_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
|
||||
Mode_7S2 = US_MR_CHRL_7_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
|
||||
Mode_8S2 = US_MR_CHRL_8_BIT | US_MR_PAR_SPACE | US_MR_NBSTOP_2_BIT,
|
||||
};
|
||||
|
||||
void begin( const uint32_t dwBaudRate ) ;
|
||||
void begin( const uint32_t dwBaudRate , const uint32_t config ) ;
|
||||
void end( void ) ;
|
||||
int available( void ) ;
|
||||
int peek( void ) ;
|
||||
int read( void ) ;
|
||||
void flush( void ) ;
|
||||
size_t write( const uint8_t c ) ;
|
||||
USARTClass(Usart* pUsart, IRQn_Type dwIrq, uint32_t dwId, RingBuffer* pRx_buffer, RingBuffer* pTx_buffer);
|
||||
|
||||
void IrqHandler( void ) ;
|
||||
void begin(const uint32_t dwBaudRate);
|
||||
void begin(const uint32_t dwBaudRate, const USARTModes config);
|
||||
void begin(const uint32_t dwBaudRate, const UARTModes config);
|
||||
|
||||
#if defined __GNUC__ /* GCC CS3 */
|
||||
using Print::write ; // pull in write(str) and write(buf, size) from Print
|
||||
#elif defined __ICCARM__ /* IAR Ewarm 5.41+ */
|
||||
// virtual void write( const char *str ) ;
|
||||
// virtual void write( const uint8_t *buffer, size_t size ) ;
|
||||
#endif
|
||||
|
||||
operator bool() { return true; }; // USART always active
|
||||
protected:
|
||||
Usart* _pUsart;
|
||||
};
|
||||
|
||||
#endif // _USART_CLASS_
|
||||
|
||||
@ -92,11 +92,9 @@ typedef unsigned int word;
|
||||
|
||||
#define bit(b) (1UL << (b))
|
||||
|
||||
// TODO: to be checked
|
||||
typedef uint8_t boolean ;
|
||||
typedef bool boolean ;
|
||||
typedef uint8_t byte ;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
} // extern "C"
|
||||
#endif // __cplusplus
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
# https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5---3rd-party-Hardware-specification
|
||||
|
||||
name=Arduino ARM (32-bits) Boards
|
||||
version=1.5.8
|
||||
version=1.6.0
|
||||
|
||||
# SAM3 compile variables
|
||||
# ----------------------
|
||||
|
||||
@ -299,8 +299,9 @@ extern const PinDescription g_APinDescription[]=
|
||||
* UART objects
|
||||
*/
|
||||
RingBuffer rx_buffer1;
|
||||
RingBuffer tx_buffer1;
|
||||
|
||||
UARTClass Serial(UART, UART_IRQn, ID_UART, &rx_buffer1);
|
||||
UARTClass Serial(UART, UART_IRQn, ID_UART, &rx_buffer1, &tx_buffer1);
|
||||
void serialEvent() __attribute__((weak));
|
||||
void serialEvent() { }
|
||||
|
||||
@ -317,14 +318,17 @@ void UART_Handler(void)
|
||||
RingBuffer rx_buffer2;
|
||||
RingBuffer rx_buffer3;
|
||||
RingBuffer rx_buffer4;
|
||||
RingBuffer tx_buffer2;
|
||||
RingBuffer tx_buffer3;
|
||||
RingBuffer tx_buffer4;
|
||||
|
||||
USARTClass Serial1(USART0, USART0_IRQn, ID_USART0, &rx_buffer2);
|
||||
USARTClass Serial1(USART0, USART0_IRQn, ID_USART0, &rx_buffer2, &tx_buffer2);
|
||||
void serialEvent1() __attribute__((weak));
|
||||
void serialEvent1() { }
|
||||
USARTClass Serial2(USART1, USART1_IRQn, ID_USART1, &rx_buffer3);
|
||||
USARTClass Serial2(USART1, USART1_IRQn, ID_USART1, &rx_buffer3, &tx_buffer3);
|
||||
void serialEvent2() __attribute__((weak));
|
||||
void serialEvent2() { }
|
||||
USARTClass Serial3(USART3, USART3_IRQn, ID_USART3, &rx_buffer4);
|
||||
USARTClass Serial3(USART3, USART3_IRQn, ID_USART3, &rx_buffer4, &tx_buffer4);
|
||||
void serialEvent3() __attribute__((weak));
|
||||
void serialEvent3() { }
|
||||
|
||||
|
||||
Reference in New Issue
Block a user