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Update GDBStub library with the source of esp-gdbstub
This commit is contained in:
Ivan Grokhotkov
459
libraries/GDBStub/src/xtensa/config/core-isa.h
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459
libraries/GDBStub/src/xtensa/config/core-isa.h
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@ -0,0 +1,459 @@
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/*
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* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
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* processor CORE configuration
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*
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* See <xtensa/config/core.h>, which includes this file, for more details.
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*/
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/* Xtensa processor core configuration information.
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Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
|
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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||||
|
||||
The above copyright notice and this permission notice shall be included
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||||
in all copies or substantial portions of the Software.
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||||
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||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef _XTENSA_CORE_CONFIGURATION_H
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#define _XTENSA_CORE_CONFIGURATION_H
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/****************************************************************************
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Parameters Useful for Any Code, USER or PRIVILEGED
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****************************************************************************/
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/*
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* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
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#define XCHAL_HAVE_WINDOWED 0 /* windowed registers option */
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#define XCHAL_NUM_AREGS 16 /* num of physical addr regs */
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#define XCHAL_NUM_AREGS_LOG2 4 /* log2(XCHAL_NUM_AREGS) */
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#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
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#define XCHAL_HAVE_DEBUG 1 /* debug option */
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#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
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#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
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#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
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#define XCHAL_HAVE_MINMAX 0 /* MIN/MAX instructions */
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#define XCHAL_HAVE_SEXT 0 /* SEXT instruction */
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#define XCHAL_HAVE_CLAMPS 0 /* CLAMPS instruction */
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#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
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#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
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#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
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#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
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#define XCHAL_HAVE_L32R 1 /* L32R instruction */
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#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
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#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
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#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
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#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
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#define XCHAL_HAVE_CALL4AND12 0 /* (obsolete option) */
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#define XCHAL_HAVE_ABS 1 /* ABS instruction */
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/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
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/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
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#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
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#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
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#define XCHAL_HAVE_SPECULATION 0 /* speculation */
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#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
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#define XCHAL_NUM_CONTEXTS 1 /* */
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#define XCHAL_NUM_MISC_REGS 0 /* num of scratch regs (0..4) */
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#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
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#define XCHAL_HAVE_PRID 1 /* processor ID register */
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#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
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#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
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#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
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#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
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#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
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#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */
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#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */
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#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
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#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
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#define XCHAL_HAVE_FP 0 /* floating point pkg */
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#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
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#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */
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#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
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#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
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#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
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#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
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#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_WRITEBUFFER_ENTRIES 1 /* size of write buffer */
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#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
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#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
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/* In T1050, applies to selected core load and store instructions (see ISA): */
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#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
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#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
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#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
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#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
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#define XCHAL_SW_VERSION 800001 /* sw version of this header */
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#define XCHAL_CORE_ID "lx106" /* alphanum core name
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(CoreID) set in the Xtensa
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Processor Generator */
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#define XCHAL_BUILD_UNIQUE_ID 0x0002B6F6 /* 22-bit sw build ID */
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/*
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* These definitions describe the hardware targeted by this software.
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*/
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#define XCHAL_HW_CONFIGID0 0xC28CDAFA /* ConfigID hi 32 bits*/
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#define XCHAL_HW_CONFIGID1 0x1082B6F6 /* ConfigID lo 32 bits*/
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#define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */
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#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
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#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
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#define XCHAL_HW_VERSION 230001 /* major*100+minor */
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#define XCHAL_HW_REL_LX3 1
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#define XCHAL_HW_REL_LX3_0 1
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#define XCHAL_HW_REL_LX3_0_1 1
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#define XCHAL_HW_CONFIGID_RELIABLE 1
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/* If software targets a *range* of hardware versions, these are the bounds: */
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#define XCHAL_HW_MIN_VERSION_MAJOR 2300 /* major v of earliest tgt hw */
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#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */
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#define XCHAL_HW_MIN_VERSION 230001 /* earliest targeted hw */
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#define XCHAL_HW_MAX_VERSION_MAJOR 2300 /* major v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */
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#define XCHAL_HW_MAX_VERSION 230001 /* latest targeted hw */
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
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#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
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#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
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#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
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#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
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#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
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#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
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#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
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#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
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/****************************************************************************
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Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
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****************************************************************************/
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#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
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/*----------------------------------------------------------------------
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CACHE
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
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/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
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/* Number of cache sets in log2(lines per way): */
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#define XCHAL_ICACHE_SETWIDTH 0
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#define XCHAL_DCACHE_SETWIDTH 0
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/* Cache set associativity (number of ways): */
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#define XCHAL_ICACHE_WAYS 1
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#define XCHAL_DCACHE_WAYS 1
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/* Cache features: */
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#define XCHAL_ICACHE_LINE_LOCKABLE 0
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#define XCHAL_DCACHE_LINE_LOCKABLE 0
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#define XCHAL_ICACHE_ECC_PARITY 0
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#define XCHAL_DCACHE_ECC_PARITY 0
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/* Cache access size in bytes (affects operation of SICW instruction): */
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#define XCHAL_ICACHE_ACCESS_SIZE 1
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#define XCHAL_DCACHE_ACCESS_SIZE 1
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/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
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#define XCHAL_CA_BITS 4
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/*----------------------------------------------------------------------
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INTERNAL I/D RAM/ROMs and XLMI
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
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#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
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#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
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#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
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#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
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#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
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/* Instruction ROM 0: */
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#define XCHAL_INSTROM0_VADDR 0x40200000
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#define XCHAL_INSTROM0_PADDR 0x40200000
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#define XCHAL_INSTROM0_SIZE 1048576
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#define XCHAL_INSTROM0_ECC_PARITY 0
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/* Instruction RAM 0: */
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#define XCHAL_INSTRAM0_VADDR 0x40000000
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#define XCHAL_INSTRAM0_PADDR 0x40000000
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#define XCHAL_INSTRAM0_SIZE 1048576
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#define XCHAL_INSTRAM0_ECC_PARITY 0
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/* Instruction RAM 1: */
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#define XCHAL_INSTRAM1_VADDR 0x40100000
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#define XCHAL_INSTRAM1_PADDR 0x40100000
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#define XCHAL_INSTRAM1_SIZE 1048576
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#define XCHAL_INSTRAM1_ECC_PARITY 0
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/* Data ROM 0: */
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#define XCHAL_DATAROM0_VADDR 0x3FF40000
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#define XCHAL_DATAROM0_PADDR 0x3FF40000
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#define XCHAL_DATAROM0_SIZE 262144
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#define XCHAL_DATAROM0_ECC_PARITY 0
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/* Data RAM 0: */
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#define XCHAL_DATARAM0_VADDR 0x3FFC0000
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#define XCHAL_DATARAM0_PADDR 0x3FFC0000
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#define XCHAL_DATARAM0_SIZE 262144
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#define XCHAL_DATARAM0_ECC_PARITY 0
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/* Data RAM 1: */
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#define XCHAL_DATARAM1_VADDR 0x3FF80000
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#define XCHAL_DATARAM1_PADDR 0x3FF80000
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#define XCHAL_DATARAM1_SIZE 262144
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#define XCHAL_DATARAM1_ECC_PARITY 0
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/* XLMI Port 0: */
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#define XCHAL_XLMI0_VADDR 0x3FF00000
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#define XCHAL_XLMI0_PADDR 0x3FF00000
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#define XCHAL_XLMI0_SIZE 262144
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#define XCHAL_XLMI0_ECC_PARITY 0
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/*----------------------------------------------------------------------
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INTERRUPTS and TIMERS
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
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#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
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#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
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#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
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#define XCHAL_NUM_TIMERS 1 /* number of CCOMPAREn regs */
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#define XCHAL_NUM_INTERRUPTS 15 /* number of interrupts */
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#define XCHAL_NUM_INTERRUPTS_LOG2 4 /* ceil(log2(NUM_INTERRUPTS)) */
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#define XCHAL_NUM_EXTINTERRUPTS 13 /* num of external interrupts */
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#define XCHAL_NUM_INTLEVELS 2 /* number of interrupt levels
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(not including level zero) */
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#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
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/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
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/* Masks of interrupts at each interrupt level: */
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#define XCHAL_INTLEVEL1_MASK 0x00003FFF
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#define XCHAL_INTLEVEL2_MASK 0x00000000
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#define XCHAL_INTLEVEL3_MASK 0x00004000
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#define XCHAL_INTLEVEL4_MASK 0x00000000
|
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#define XCHAL_INTLEVEL5_MASK 0x00000000
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#define XCHAL_INTLEVEL6_MASK 0x00000000
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#define XCHAL_INTLEVEL7_MASK 0x00000000
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/* Masks of interrupts at each range 1..n of interrupt levels: */
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#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00003FFF
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#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x00003FFF
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#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x00007FFF
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#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x00007FFF
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#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x00007FFF
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#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x00007FFF
|
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#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x00007FFF
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|
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/* Level of each interrupt: */
|
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#define XCHAL_INT0_LEVEL 1
|
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#define XCHAL_INT1_LEVEL 1
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#define XCHAL_INT2_LEVEL 1
|
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#define XCHAL_INT3_LEVEL 1
|
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#define XCHAL_INT4_LEVEL 1
|
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#define XCHAL_INT5_LEVEL 1
|
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#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 1
|
||||
#define XCHAL_INT9_LEVEL 1
|
||||
#define XCHAL_INT10_LEVEL 1
|
||||
#define XCHAL_INT11_LEVEL 1
|
||||
#define XCHAL_INT12_LEVEL 1
|
||||
#define XCHAL_INT13_LEVEL 1
|
||||
#define XCHAL_INT14_LEVEL 3
|
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#define XCHAL_DEBUGLEVEL 2 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 3 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFFF8000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000080
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00003F00
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000003F
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00000040
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL3_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt vectors/levels.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT9_NUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT10_NUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 14 /* (intlevel 3) */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (old)
|
||||
2 == XEA2 (new)
|
||||
0 == XEAX (extern) */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x40000080
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x40000080
|
||||
#define XCHAL_RESET_VECTOR_VADDR 0x50000000
|
||||
#define XCHAL_RESET_VECTOR_PADDR 0x50000000
|
||||
#define XCHAL_USER_VECOFS 0x00000050
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x40000050
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x40000050
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000030
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000030
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000030
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x00000070
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x40000070
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x40000070
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000010
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000010
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000010
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL2_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL2_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL2_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x00000020
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x40000020
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x40000020
|
||||
#define XCHAL_INTLEVEL3_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 1 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 1 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
/* If none of the above last 4 are set, it's a custom TLB configuration. */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* _XTENSA_CORE_CONFIGURATION_H */
|
||||
|
||||
80
libraries/GDBStub/src/xtensa/config/specreg.h
Normal file
80
libraries/GDBStub/src/xtensa/config/specreg.h
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Xtensa Special Register symbolic names
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Boreal/Xtensa/SWConfig/hal/specreg.h.tpp#2 $ */
|
||||
|
||||
/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 1998-2002 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
#ifndef XTENSA_SPECREG_H
|
||||
#define XTENSA_SPECREG_H
|
||||
|
||||
/* Include these special register bitfield definitions, for historical reasons: */
|
||||
#include <xtensa/corebits.h>
|
||||
|
||||
|
||||
/* Special registers: */
|
||||
#define SAR 3
|
||||
#define LITBASE 5
|
||||
#define IBREAKENABLE 96
|
||||
#define DDR 104
|
||||
#define IBREAKA_0 128
|
||||
#define DBREAKA_0 144
|
||||
#define DBREAKC_0 160
|
||||
#define EPC_1 177
|
||||
#define EPC_2 178
|
||||
#define EPC_3 179
|
||||
#define DEPC 192
|
||||
#define EPS_2 194
|
||||
#define EPS_3 195
|
||||
#define EXCSAVE_1 209
|
||||
#define EXCSAVE_2 210
|
||||
#define EXCSAVE_3 211
|
||||
#define INTERRUPT 226
|
||||
#define INTENABLE 228
|
||||
#define PS 230
|
||||
#define VECBASE 231
|
||||
#define EXCCAUSE 232
|
||||
#define DEBUGCAUSE 233
|
||||
#define CCOUNT 234
|
||||
#define PRID 235
|
||||
#define ICOUNT 236
|
||||
#define ICOUNTLEVEL 237
|
||||
#define EXCVADDR 238
|
||||
#define CCOMPARE_0 240
|
||||
|
||||
/* Special cases (bases of special register series): */
|
||||
#define IBREAKA 128
|
||||
#define DBREAKA 144
|
||||
#define DBREAKC 160
|
||||
#define EPC 176
|
||||
#define EPS 192
|
||||
#define EXCSAVE 208
|
||||
#define CCOMPARE 240
|
||||
|
||||
/* Special names for read-only and write-only interrupt registers: */
|
||||
#define INTREAD 226
|
||||
#define INTSET 226
|
||||
#define INTCLEAR 227
|
||||
|
||||
#endif /* XTENSA_SPECREG_H */
|
||||
|
||||
164
libraries/GDBStub/src/xtensa/corebits.h
Normal file
164
libraries/GDBStub/src/xtensa/corebits.h
Normal file
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
|
||||
*
|
||||
* (In previous releases, these were defined in specreg.h, a generated file.
|
||||
* This file is not generated, ie. it is processor configuration independent.)
|
||||
*/
|
||||
|
||||
/* $Id: //depot/rel/Boreal/Xtensa/OS/include/xtensa/corebits.h#2 $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2005-2007 Tensilica Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included
|
||||
* in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef XTENSA_COREBITS_H
|
||||
#define XTENSA_COREBITS_H
|
||||
|
||||
/* EXCCAUSE register fields: */
|
||||
#define EXCCAUSE_EXCCAUSE_SHIFT 0
|
||||
#define EXCCAUSE_EXCCAUSE_MASK 0x3F
|
||||
/* EXCCAUSE register values: */
|
||||
/*
|
||||
* General Exception Causes
|
||||
* (values of EXCCAUSE special register set by general exceptions,
|
||||
* which vector to the user, kernel, or double-exception vectors).
|
||||
*/
|
||||
#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
|
||||
#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
|
||||
#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
|
||||
# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
|
||||
#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
|
||||
# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
|
||||
#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
|
||||
# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
|
||||
#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
|
||||
#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
|
||||
#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
|
||||
#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
|
||||
#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
|
||||
/* Reserved 10..11 */
|
||||
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
|
||||
#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
|
||||
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
|
||||
#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
|
||||
#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
|
||||
#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
|
||||
#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
|
||||
/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
|
||||
#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
|
||||
/* Reserved 21..23 */
|
||||
#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
|
||||
#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
|
||||
#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
|
||||
/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
|
||||
#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
|
||||
#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
|
||||
/* Reserved 30..31 */
|
||||
#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
|
||||
#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
|
||||
#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
|
||||
#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
|
||||
#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
|
||||
#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
|
||||
#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
|
||||
#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
|
||||
#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
|
||||
/*#define EXCCAUSE_FLOATING_POINT 40*/ /* Floating Point Exception (not implemented) */
|
||||
/* Reserved 40..63 */
|
||||
|
||||
/* PS register fields: */
|
||||
#define PS_WOE_SHIFT 18
|
||||
#define PS_WOE_MASK 0x00040000
|
||||
#define PS_WOE PS_WOE_MASK
|
||||
#define PS_CALLINC_SHIFT 16
|
||||
#define PS_CALLINC_MASK 0x00030000
|
||||
#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
|
||||
#define PS_OWB_SHIFT 8
|
||||
#define PS_OWB_MASK 0x00000F00
|
||||
#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
|
||||
#define PS_RING_SHIFT 6
|
||||
#define PS_RING_MASK 0x000000C0
|
||||
#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
|
||||
#define PS_UM_SHIFT 5
|
||||
#define PS_UM_MASK 0x00000020
|
||||
#define PS_UM PS_UM_MASK
|
||||
#define PS_EXCM_SHIFT 4
|
||||
#define PS_EXCM_MASK 0x00000010
|
||||
#define PS_EXCM PS_EXCM_MASK
|
||||
#define PS_INTLEVEL_SHIFT 0
|
||||
#define PS_INTLEVEL_MASK 0x0000000F
|
||||
#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
|
||||
/* Backward compatibility (deprecated): */
|
||||
#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
|
||||
#define PS_PROGSTACK_MASK PS_UM_MASK
|
||||
#define PS_PROG_SHIFT PS_UM_SHIFT
|
||||
#define PS_PROG_MASK PS_UM_MASK
|
||||
#define PS_PROG PS_UM
|
||||
|
||||
/* DBREAKCn register fields: */
|
||||
#define DBREAKC_MASK_SHIFT 0
|
||||
#define DBREAKC_MASK_MASK 0x0000003F
|
||||
#define DBREAKC_LOADBREAK_SHIFT 30
|
||||
#define DBREAKC_LOADBREAK_MASK 0x40000000
|
||||
#define DBREAKC_STOREBREAK_SHIFT 31
|
||||
#define DBREAKC_STOREBREAK_MASK 0x80000000
|
||||
|
||||
/* DEBUGCAUSE register fields: */
|
||||
#define DEBUGCAUSE_DEBUGINT_SHIFT 5
|
||||
#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
|
||||
#define DEBUGCAUSE_BREAKN_SHIFT 4
|
||||
#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
|
||||
#define DEBUGCAUSE_BREAK_SHIFT 3
|
||||
#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
|
||||
#define DEBUGCAUSE_DBREAK_SHIFT 2
|
||||
#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
|
||||
#define DEBUGCAUSE_IBREAK_SHIFT 1
|
||||
#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
|
||||
#define DEBUGCAUSE_ICOUNT_SHIFT 0
|
||||
#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
|
||||
|
||||
/* MESR register fields: */
|
||||
#define MESR_MEME 0x00000001 /* memory error */
|
||||
#define MESR_MEME_SHIFT 0
|
||||
#define MESR_DME 0x00000002 /* double memory error */
|
||||
#define MESR_DME_SHIFT 1
|
||||
#define MESR_RCE 0x00000010 /* recorded memory error */
|
||||
#define MESR_RCE_SHIFT 4
|
||||
#define MESR_LCE
|
||||
#define MESR_LCE_SHIFT ?
|
||||
#define MESR_LCE_L
|
||||
#define MESR_ERRENAB 0x00000100
|
||||
#define MESR_ERRENAB_SHIFT 8
|
||||
#define MESR_ERRTEST 0x00000200
|
||||
#define MESR_ERRTEST_SHIFT 9
|
||||
#define MESR_DATEXC 0x00000400
|
||||
#define MESR_DATEXC_SHIFT 10
|
||||
#define MESR_INSEXC 0x00000800
|
||||
#define MESR_INSEXC_SHIFT 11
|
||||
#define MESR_WAYNUM_SHIFT 16
|
||||
#define MESR_ACCTYPE_SHIFT 20
|
||||
#define MESR_MEMTYPE_SHIFT 24
|
||||
#define MESR_ERRTYPE_SHIFT 30
|
||||
|
||||
|
||||
#endif /*XTENSA_COREBITS_H*/
|
||||
|
||||
Reference in New Issue
Block a user