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I2s input API and examples (#4539)
Enables I2S stereo input via DMA using new API calls: . i2s_rxtx_begin(bool rx, rool tx); . i2s_read_sample(uint32_t *l, uint32_t *r); Original API calls will only enable TX, so this is backwards compatible. Add simple I2S input example code using Arduino serial plotter. Add UDP transmit of I2S microphone data to a PC (remote microphone). Clean up and reorganize code to share RX and TX logic as much as possible. Fix a potential WDT error while in blocking sample read and write.
This commit is contained in:
Earle F. Philhower, III
committed by
GitHub
GitHub
parent
7ae8f98e57
commit
8ae553d99e
@ -24,104 +24,205 @@
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#include "osapi.h"
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#include "ets_sys.h"
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#include "i2s_reg.h"
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#include "i2s.h"
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#define SLC_BUF_CNT (8) // Number of buffers in the I2S circular buffer
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#define SLC_BUF_LEN (64) // Length of one buffer, in 32-bit words.
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// We use a queue to keep track of the DMA buffers that are empty. The ISR
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// will push buffers to the back of the queue, the I2S transmitter will pull
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// them from the front and fill them. For ease, the queue will contain
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// *pointers* to the DMA buffers, not the data itself. The queue depth is
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// one smaller than the amount of buffers we have, because there's always a
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// buffer that is being used by the DMA subsystem *right now* and we don't
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// want to be able to write to that simultaneously.
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// For RX, it's a little different. The buffers in i2s_slc_queue are
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// placed onto the list when they're filled by DMA
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typedef struct slc_queue_item {
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uint32_t blocksize : 12;
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uint32_t datalen : 12;
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uint32_t unused : 5;
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uint32_t sub_sof : 1;
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uint32_t eof : 1;
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volatile uint32_t owner : 1; // DMA can change this value
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uint32_t * buf_ptr;
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struct slc_queue_item * next_link_ptr;
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} slc_queue_item_t;
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typedef struct i2s_state {
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uint32_t * slc_queue[SLC_BUF_CNT];
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volatile uint8_t slc_queue_len;
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uint32_t * slc_buf_pntr[SLC_BUF_CNT]; // Pointer to the I2S DMA buffer data
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slc_queue_item_t slc_items[SLC_BUF_CNT]; // I2S DMA buffer descriptors
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uint32_t * curr_slc_buf; // Current buffer for writing
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uint32_t curr_slc_buf_pos; // Position in the current buffer
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void (*callback) (void);
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// Callback function should be defined as 'void ICACHE_RAM_ATTR function_name()',
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// and be placed in IRAM for faster execution. Avoid long computational tasks in this
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// function, use it to set flags and process later.
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} i2s_state_t;
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// RX = I2S receive (i.e. microphone), TX = I2S transmit (i.e. DAC)
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static i2s_state_t *rx = NULL;
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static i2s_state_t *tx = NULL;
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// Last I2S sample rate requested
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static uint32_t _i2s_sample_rate;
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// IOs used for I2S. Not defined in i2s.h, unfortunately.
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// Note these are internal IOs numbers and not pins on an
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// Note these are internal GPIO numbers and not pins on an
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// Arduino board. Users need to verify their particular wiring.
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#define I2SO_WS 2
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#define I2SO_DATA 3
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#define I2SO_BCK 15
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#define I2SO_BCK 15
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#define I2SO_WS 2
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#define I2SI_DATA 12
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#define I2SI_BCK 13
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#define I2SI_WS 14
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#define SLC_BUF_CNT (8) //Number of buffers in the I2S circular buffer
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#define SLC_BUF_LEN (64) //Length of one buffer, in 32-bit words.
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//We use a queue to keep track of the DMA buffers that are empty. The ISR will push buffers to the back of the queue,
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//the mp3 decode will pull them from the front and fill them. For ease, the queue will contain *pointers* to the DMA
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//buffers, not the data itself. The queue depth is one smaller than the amount of buffers we have, because there's
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//always a buffer that is being used by the DMA subsystem *right now* and we don't want to be able to write to that
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//simultaneously.
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struct slc_queue_item {
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uint32 blocksize:12;
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uint32 datalen:12;
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uint32 unused:5;
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uint32 sub_sof:1;
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uint32 eof:1;
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uint32 owner:1;
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uint32 buf_ptr;
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uint32 next_link_ptr;
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};
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static uint32_t i2s_slc_queue[SLC_BUF_CNT-1];
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static uint8_t i2s_slc_queue_len;
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static uint32_t *i2s_slc_buf_pntr[SLC_BUF_CNT]; //Pointer to the I2S DMA buffer data
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static struct slc_queue_item i2s_slc_items[SLC_BUF_CNT]; //I2S DMA buffer descriptors
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static uint32_t *i2s_curr_slc_buf=NULL;//current buffer for writing
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static int i2s_curr_slc_buf_pos=0; //position in the current buffer
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static void (*i2s_callback) (void)=0; //Callback function should be defined as 'void ICACHE_RAM_ATTR function_name()', placing the function in IRAM for faster execution. Avoid long computational tasks in this function, use it to set flags and process later.
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bool i2s_is_full(){
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return (i2s_curr_slc_buf_pos==SLC_BUF_LEN || i2s_curr_slc_buf==NULL) && (i2s_slc_queue_len == 0);
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static bool _i2s_is_full(const i2s_state_t *ch) {
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if (!ch) {
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return false;
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}
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return (ch->curr_slc_buf_pos==SLC_BUF_LEN || ch->curr_slc_buf==NULL) && (ch->slc_queue_len == 0);
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}
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bool i2s_is_empty(){
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return (i2s_slc_queue_len >= SLC_BUF_CNT-1);
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bool i2s_is_full() {
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return _i2s_is_full( tx );
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}
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bool i2s_rx_is_full() {
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return _i2s_is_full( rx );
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}
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static bool _i2s_is_empty(const i2s_state_t *ch) {
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if (!ch) {
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return false;
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}
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return (ch->slc_queue_len >= SLC_BUF_CNT-1);
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}
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bool i2s_is_empty() {
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return _i2s_is_empty( tx );
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}
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bool i2s_rx_is_empty() {
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return _i2s_is_empty( rx );
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}
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static int16_t _i2s_available(const i2s_state_t *ch) {
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if (!ch) {
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return 0;
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}
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return (SLC_BUF_CNT - ch->slc_queue_len) * SLC_BUF_LEN;
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}
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int16_t i2s_available(){
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return (SLC_BUF_CNT - i2s_slc_queue_len) * SLC_BUF_LEN;
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return _i2s_available( tx );
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}
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uint32_t ICACHE_RAM_ATTR i2s_slc_queue_next_item(){ //pop the top off the queue
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int16_t i2s_rx_available(){
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return _i2s_available( rx );
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}
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// Pop the top off of the queue and return it
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static uint32_t * ICACHE_RAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
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uint8_t i;
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uint32_t item = i2s_slc_queue[0];
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i2s_slc_queue_len--;
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for(i=0;i<i2s_slc_queue_len;i++)
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i2s_slc_queue[i] = i2s_slc_queue[i+1];
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uint32_t *item = ch->slc_queue[0];
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ch->slc_queue_len--;
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for ( i = 0; i < ch->slc_queue_len; i++) {
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ch->slc_queue[i] = ch->slc_queue[i+1];
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}
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return item;
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}
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//This routine is called as soon as the DMA routine has something to tell us. All we
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//handle here is the RX_EOF_INT status, which indicate the DMA has sent a buffer whose
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//descriptor has the 'EOF' field set to 1.
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void ICACHE_RAM_ATTR i2s_slc_isr(void) {
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uint32_t slc_intr_status = SLCIS;
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SLCIC = 0xFFFFFFFF;
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if (slc_intr_status & SLCIRXEOF) {
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ETS_SLC_INTR_DISABLE();
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struct slc_queue_item *finished_item = (struct slc_queue_item*)SLCRXEDA;
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ets_memset((void *)finished_item->buf_ptr, 0x00, SLC_BUF_LEN * 4);//zero the buffer so it is mute in case of underflow
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if (i2s_slc_queue_len >= SLC_BUF_CNT-1) { //All buffers are empty. This means we have an underflow
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i2s_slc_queue_next_item(); //free space for finished_item
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// Append an item to the end of the queue from receive
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static void ICACHE_RAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t *item) {
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// Shift everything up, except for the one corresponding to this item
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for (int i=0, dest=0; i < ch->slc_queue_len; i++) {
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if (ch->slc_queue[i] != item) {
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ch->slc_queue[dest++] = ch->slc_queue[i];
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}
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i2s_slc_queue[i2s_slc_queue_len++] = finished_item->buf_ptr;
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if (i2s_callback) i2s_callback();
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ETS_SLC_INTR_ENABLE();
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}
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if (ch->slc_queue_len < SLC_BUF_CNT - 1) {
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ch->slc_queue[ch->slc_queue_len++] = item;
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} else {
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ch->slc_queue[ch->slc_queue_len] = item;
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}
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}
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void i2s_set_callback(void (*callback) (void)){
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i2s_callback = callback;
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static void ICACHE_RAM_ATTR i2s_slc_isr(void) {
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ETS_SLC_INTR_DISABLE();
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uint32_t slc_intr_status = SLCIS;
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SLCIC = 0xFFFFFFFF;
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if (slc_intr_status & SLCIRXEOF) {
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slc_queue_item_t *finished_item = (slc_queue_item_t *)SLCRXEDA;
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// Zero the buffer so it is mute in case of underflow
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ets_memset((void *)finished_item->buf_ptr, 0x00, SLC_BUF_LEN * 4);
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if (tx->slc_queue_len >= SLC_BUF_CNT-1) {
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// All buffers are empty. This means we have an underflow
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i2s_slc_queue_next_item(tx); // Free space for finished_item
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}
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tx->slc_queue[tx->slc_queue_len++] = finished_item->buf_ptr;
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if (tx->callback) {
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tx->callback();
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}
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}
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if (slc_intr_status & SLCITXEOF) {
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slc_queue_item_t *finished_item = (slc_queue_item_t *)SLCTXEDA;
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// Set owner back to 1 (SW) or else RX stops. TX has no such restriction.
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finished_item->owner = 1;
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i2s_slc_queue_append_item(rx, finished_item->buf_ptr);
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if (rx->callback) {
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rx->callback();
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}
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}
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ETS_SLC_INTR_ENABLE();
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}
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void i2s_slc_begin(){
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i2s_slc_queue_len = 0;
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int x, y;
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for (x=0; x<SLC_BUF_CNT; x++) {
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i2s_slc_buf_pntr[x] = malloc(SLC_BUF_LEN*4);
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for (y=0; y<SLC_BUF_LEN; y++) i2s_slc_buf_pntr[x][y] = 0;
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void i2s_set_callback(void (*callback) (void)) {
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tx->callback = callback;
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}
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i2s_slc_items[x].unused = 0;
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i2s_slc_items[x].owner = 1;
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i2s_slc_items[x].eof = 1;
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i2s_slc_items[x].sub_sof = 0;
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i2s_slc_items[x].datalen = SLC_BUF_LEN*4;
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i2s_slc_items[x].blocksize = SLC_BUF_LEN*4;
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i2s_slc_items[x].buf_ptr = (uint32_t)&i2s_slc_buf_pntr[x][0];
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i2s_slc_items[x].next_link_ptr = (int)((x<(SLC_BUF_CNT-1))?(&i2s_slc_items[x+1]):(&i2s_slc_items[0]));
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void i2s_rx_set_callback(void (*callback) (void)) {
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rx->callback = callback;
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}
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static bool _alloc_channel(i2s_state_t *ch) {
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ch->slc_queue_len = 0;
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for (int x=0; x<SLC_BUF_CNT; x++) {
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ch->slc_buf_pntr[x] = (uint32_t *)malloc(SLC_BUF_LEN * sizeof(ch->slc_buf_pntr[0][0]));
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if (!ch->slc_buf_pntr[x]) {
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// OOM, the upper layer will free up any partially allocated channels.
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return false;
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}
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memset(ch->slc_buf_pntr[x], 0, SLC_BUF_LEN * sizeof(ch->slc_buf_pntr[x][0]));
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ch->slc_items[x].unused = 0;
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ch->slc_items[x].owner = 1;
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ch->slc_items[x].eof = 1;
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ch->slc_items[x].sub_sof = 0;
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ch->slc_items[x].datalen = SLC_BUF_LEN * 4;
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ch->slc_items[x].blocksize = SLC_BUF_LEN * 4;
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ch->slc_items[x].buf_ptr = (uint32_t*)&ch->slc_buf_pntr[x][0];
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ch->slc_items[x].next_link_ptr = (x<(SLC_BUF_CNT-1))?(&ch->slc_items[x+1]):(&ch->slc_items[0]);
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}
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return true;
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}
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static bool i2s_slc_begin() {
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if (tx) {
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if (!_alloc_channel(tx)) {
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return false;
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}
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}
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if (rx) {
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if (!_alloc_channel(rx)) {
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return false;
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}
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}
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ETS_SLC_INTR_DISABLE();
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@ -129,32 +230,44 @@ void i2s_slc_begin(){
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SLCC0 &= ~(SLCRXLR | SLCTXLR);
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SLCIC = 0xFFFFFFFF;
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//Configure DMA
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SLCC0 &= ~(SLCMM << SLCM); //clear DMA MODE
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SLCC0 |= (1 << SLCM); //set DMA MODE to 1
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SLCRXDC |= SLCBINR | SLCBTNR; //enable INFOR_NO_REPLACE and TOKEN_NO_REPLACE
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SLCRXDC &= ~(SLCBRXFE | SLCBRXEM | SLCBRXFM); //disable RX_FILL, RX_EOF_MODE and RX_FILL_MODE
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// Configure DMA
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SLCC0 &= ~(SLCMM << SLCM); // Clear DMA MODE
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SLCC0 |= (1 << SLCM); // Set DMA MODE to 1
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SLCRXDC |= SLCBINR | SLCBTNR; // Enable INFOR_NO_REPLACE and TOKEN_NO_REPLACE
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SLCRXDC &= ~(SLCBRXFE | SLCBRXEM | SLCBRXFM); // Disable RX_FILL, RX_EOF_MODE and RX_FILL_MODE
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//Feed DMA the 1st buffer desc addr
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//To send data to the I2S subsystem, counter-intuitively we use the RXLINK part, not the TXLINK as you might
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//expect. The TXLINK part still needs a valid DMA descriptor, even if it's unused: the DMA engine will throw
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//an error at us otherwise. Just feed it any random descriptor.
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SLCTXL &= ~(SLCTXLAM << SLCTXLA); // clear TX descriptor address
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SLCTXL |= (uint32)&i2s_slc_items[1] << SLCTXLA; //set TX descriptor address. any random desc is OK, we don't use TX but it needs to be valid
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SLCRXL &= ~(SLCRXLAM << SLCRXLA); // clear RX descriptor address
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SLCRXL |= (uint32)&i2s_slc_items[0] << SLCRXLA; //set RX descriptor address
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if (!rx) {
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SLCTXL |= (uint32)&tx->slc_items[1] << SLCTXLA; // Set fake (unused) RX descriptor address
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} else {
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SLCTXL |= (uint32)&rx->slc_items[0] << SLCTXLA; // Set real RX address
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}
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if (!tx) {
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SLCRXL |= (uint32)&rx->slc_items[1] << SLCRXLA; // Set fake (unused) TX descriptor address
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} else {
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SLCRXL |= (uint32)&tx->slc_items[0] << SLCRXLA; // Set real TX address
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}
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ETS_SLC_INTR_ATTACH(i2s_slc_isr, NULL);
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SLCIE = SLCIRXEOF; //Enable only for RX EOF interrupt
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SLCIE = (tx?SLCIRXEOF:0) | (rx?SLCITXEOF:0); // Enable appropriate EOF IRQ
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ETS_SLC_INTR_ENABLE();
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//Start transmission
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// Start transmission ("TX" DMA always needed to be enabled)
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SLCTXL |= SLCTXLS;
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SLCRXL |= SLCRXLS;
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if (tx) {
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SLCRXL |= SLCRXLS;
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}
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return true;
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}
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void i2s_slc_end(){
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static void i2s_slc_end(){
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ETS_SLC_INTR_DISABLE();
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SLCIC = 0xFFFFFFFF;
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SLCIE = 0;
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@ -162,19 +275,32 @@ void i2s_slc_end(){
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SLCRXL &= ~(SLCRXLAM << SLCRXLA); // clear RX descriptor address
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for (int x = 0; x<SLC_BUF_CNT; x++) {
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free(i2s_slc_buf_pntr[x]);
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if (tx) {
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free(tx->slc_buf_pntr[x]);
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tx->slc_buf_pntr[x] = NULL;
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}
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if (rx) {
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free(rx->slc_buf_pntr[x]);
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rx->slc_buf_pntr[x] = NULL;
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}
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}
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}
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//This routine pushes a single, 32-bit sample to the I2S buffers. Call this at (on average)
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//at least the current sample rate. You can also call it quicker: it will suspend the calling
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//thread if the buffer is full and resume when there's room again.
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// These routines push a single, 32-bit sample to the I2S buffers. Call at (on average)
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// at least the current sample rate.
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static bool _i2s_write_sample(uint32_t sample, bool nb) {
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if (!tx) {
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return false;
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}
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bool i2s_write_sample(uint32_t sample) {
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if (i2s_curr_slc_buf_pos==SLC_BUF_LEN || i2s_curr_slc_buf==NULL) {
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if(i2s_slc_queue_len == 0){
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while(1){
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if(i2s_slc_queue_len > 0){
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if (tx->curr_slc_buf_pos==SLC_BUF_LEN || tx->curr_slc_buf==NULL) {
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if (tx->slc_queue_len == 0) {
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if (nb) {
|
||||
// Don't wait if nonblocking, just notify upper levels
|
||||
return false;
|
||||
}
|
||||
while (1) {
|
||||
if (tx->slc_queue_len > 0) {
|
||||
break;
|
||||
} else {
|
||||
optimistic_yield(10000);
|
||||
@ -182,26 +308,20 @@ bool i2s_write_sample(uint32_t sample) {
|
||||
}
|
||||
}
|
||||
ETS_SLC_INTR_DISABLE();
|
||||
i2s_curr_slc_buf = (uint32_t *)i2s_slc_queue_next_item();
|
||||
tx->curr_slc_buf = (uint32_t *)i2s_slc_queue_next_item(tx);
|
||||
ETS_SLC_INTR_ENABLE();
|
||||
i2s_curr_slc_buf_pos=0;
|
||||
tx->curr_slc_buf_pos=0;
|
||||
}
|
||||
i2s_curr_slc_buf[i2s_curr_slc_buf_pos++]=sample;
|
||||
tx->curr_slc_buf[tx->curr_slc_buf_pos++]=sample;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool i2s_write_sample(uint32_t sample) {
|
||||
return _i2s_write_sample(sample, false);
|
||||
}
|
||||
|
||||
bool i2s_write_sample_nb(uint32_t sample) {
|
||||
if (i2s_curr_slc_buf_pos==SLC_BUF_LEN || i2s_curr_slc_buf==NULL) {
|
||||
if(i2s_slc_queue_len == 0){
|
||||
return false;
|
||||
}
|
||||
ETS_SLC_INTR_DISABLE();
|
||||
i2s_curr_slc_buf = (uint32_t *)i2s_slc_queue_next_item();
|
||||
ETS_SLC_INTR_ENABLE();
|
||||
i2s_curr_slc_buf_pos=0;
|
||||
}
|
||||
i2s_curr_slc_buf[i2s_curr_slc_buf_pos++]=sample;
|
||||
return true;
|
||||
return _i2s_write_sample(sample, true);
|
||||
}
|
||||
|
||||
bool i2s_write_lr(int16_t left, int16_t right){
|
||||
@ -211,15 +331,45 @@ bool i2s_write_lr(int16_t left, int16_t right){
|
||||
return i2s_write_sample(sample);
|
||||
}
|
||||
|
||||
// END DMA
|
||||
// =========
|
||||
// START I2S
|
||||
bool i2s_read_sample(int16_t *left, int16_t *right, bool blocking) {
|
||||
if (!rx) {
|
||||
return false;
|
||||
}
|
||||
if (rx->curr_slc_buf_pos==SLC_BUF_LEN || rx->curr_slc_buf==NULL) {
|
||||
if (rx->slc_queue_len == 0) {
|
||||
if (!blocking) {
|
||||
return false;
|
||||
}
|
||||
while (1) {
|
||||
if (rx->slc_queue_len > 0){
|
||||
break;
|
||||
} else {
|
||||
optimistic_yield(10000);
|
||||
}
|
||||
}
|
||||
}
|
||||
ETS_SLC_INTR_DISABLE();
|
||||
rx->curr_slc_buf = (uint32_t *)i2s_slc_queue_next_item(rx);
|
||||
ETS_SLC_INTR_ENABLE();
|
||||
rx->curr_slc_buf_pos=0;
|
||||
}
|
||||
|
||||
uint32_t sample = rx->curr_slc_buf[rx->curr_slc_buf_pos++];
|
||||
if (left) {
|
||||
*left = sample & 0xffff;
|
||||
}
|
||||
if (right) {
|
||||
*right = sample >> 16;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
static uint32_t _i2s_sample_rate;
|
||||
|
||||
void i2s_set_rate(uint32_t rate){ //Rate in HZ
|
||||
if(rate == _i2s_sample_rate) return;
|
||||
void i2s_set_rate(uint32_t rate) { //Rate in HZ
|
||||
if (rate == _i2s_sample_rate) {
|
||||
return;
|
||||
}
|
||||
_i2s_sample_rate = rate;
|
||||
|
||||
uint32_t scaled_base_freq = I2SBASEFREQ/32;
|
||||
@ -227,8 +377,8 @@ void i2s_set_rate(uint32_t rate){ //Rate in HZ
|
||||
|
||||
uint8_t sbd_div_best=1;
|
||||
uint8_t scd_div_best=1;
|
||||
for (uint8_t i=1; i<64; i++){
|
||||
for (uint8_t j=i; j<64; j++){
|
||||
for (uint8_t i=1; i<64; i++) {
|
||||
for (uint8_t j=i; j<64; j++) {
|
||||
float new_delta = fabs(((float)scaled_base_freq/i/j) - rate);
|
||||
if (new_delta < delta_best){
|
||||
delta_best = new_delta;
|
||||
@ -246,29 +396,55 @@ void i2s_set_dividers(uint8_t div1, uint8_t div2) {
|
||||
div1 &= I2SBDM;
|
||||
div2 &= I2SCDM;
|
||||
|
||||
// !trans master(?), !bits mod(==16 bits/chanel), clear clock dividers
|
||||
I2SC &= ~(I2STSM | (I2SBMM << I2SBM) | (I2SBDM << I2SBD) | (I2SCDM << I2SCD));
|
||||
// trans master(active low), recv master(active_low), !bits mod(==16 bits/chanel), clear clock dividers
|
||||
I2SC &= ~(I2STSM | I2SRSM | (I2SBMM << I2SBM) | (I2SBDM << I2SBD) | (I2SCDM << I2SCD));
|
||||
|
||||
// I2SRF = Send/recv right channel first (? may be swapped form I2S spec of WS=0 => left)
|
||||
// I2SMR = MSB recv/xmit first
|
||||
// I2SRSM = Receive slave mode (?)
|
||||
// I2SRMS, I2STMS = 1-bit delay from WS to MSB (I2S format)
|
||||
// div1, div2 = Set I2S WS clock frequency. BCLK seems to be generated from 32x this
|
||||
I2SC |= I2SRF | I2SMR | I2SRSM | I2SRMS | I2STMS | (div1 << I2SBD) | (div2 << I2SCD);
|
||||
I2SC |= I2SRF | I2SMR | I2SRMS | I2STMS | (div1 << I2SBD) | (div2 << I2SCD);
|
||||
}
|
||||
|
||||
float i2s_get_real_rate(){
|
||||
return (float)I2SBASEFREQ/32/((I2SC>>I2SBD) & I2SBDM)/((I2SC >> I2SCD) & I2SCDM);
|
||||
}
|
||||
|
||||
void i2s_begin() {
|
||||
_i2s_sample_rate = 0;
|
||||
i2s_slc_begin();
|
||||
bool i2s_rxtx_begin(bool enableRx, bool enableTx) {
|
||||
if (tx || rx) {
|
||||
i2s_end(); // Stop and free any ongoing stuff
|
||||
}
|
||||
|
||||
// Redirect control of IOs to the I2S block
|
||||
pinMode(I2SO_WS, FUNCTION_1);
|
||||
pinMode(I2SO_DATA, FUNCTION_1);
|
||||
pinMode(I2SO_BCK, FUNCTION_1);
|
||||
if (enableTx) {
|
||||
tx = (i2s_state_t*)calloc(1, sizeof(*tx));
|
||||
if (!tx) {
|
||||
// Nothing to clean up yet
|
||||
return false; // OOM Error!
|
||||
}
|
||||
pinMode(I2SO_WS, FUNCTION_1);
|
||||
pinMode(I2SO_DATA, FUNCTION_1);
|
||||
pinMode(I2SO_BCK, FUNCTION_1);
|
||||
}
|
||||
if (enableRx) {
|
||||
rx = (i2s_state_t*)calloc(1, sizeof(*rx));
|
||||
if (!rx) {
|
||||
i2s_end(); // Clean up any TX or pin changes
|
||||
return false; // OOM error!
|
||||
}
|
||||
pinMode(I2SI_WS, OUTPUT);
|
||||
pinMode(I2SI_BCK, OUTPUT);
|
||||
pinMode(I2SI_DATA, INPUT);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, FUNC_I2SI_DATA);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_I2SI_BCK);
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, FUNC_I2SI_WS);
|
||||
}
|
||||
|
||||
_i2s_sample_rate = 0;
|
||||
if (!i2s_slc_begin()) {
|
||||
// OOM in SLC memory allocations, tear it all down and abort!
|
||||
i2s_end();
|
||||
return false;
|
||||
}
|
||||
|
||||
I2S_CLK_ENABLE();
|
||||
I2SIC = 0x3F;
|
||||
@ -278,28 +454,54 @@ void i2s_begin() {
|
||||
I2SC &= ~(I2SRST);
|
||||
I2SC |= I2SRST;
|
||||
I2SC &= ~(I2SRST);
|
||||
|
||||
|
||||
// I2STXFMM, I2SRXFMM=0 => 16-bit, dual channel data shifted in/out
|
||||
I2SFC &= ~(I2SDE | (I2STXFMM << I2STXFM) | (I2SRXFMM << I2SRXFM)); //Set RX/TX FIFO_MOD=0 (16-bit) and disable DMA (FIFO only)
|
||||
I2SFC |= I2SDE; //Enable DMA
|
||||
I2SFC &= ~(I2SDE | (I2STXFMM << I2STXFM) | (I2SRXFMM << I2SRXFM)); // Set RX/TX FIFO_MOD=0 and disable DMA (FIFO only)
|
||||
I2SFC |= I2SDE; // Enable DMA
|
||||
|
||||
// I2STXCMM, I2SRXCMM=0 => Dual channel mode
|
||||
I2SCC &= ~((I2STXCMM << I2STXCM) | (I2SRXCMM << I2SRXCM)); //Set RX/TX CHAN_MOD=0
|
||||
I2SCC &= ~((I2STXCMM << I2STXCM) | (I2SRXCMM << I2SRXCM)); // Set RX/TX CHAN_MOD=0
|
||||
|
||||
i2s_set_rate(44100);
|
||||
I2SC |= I2STXS; //Start transmission
|
||||
|
||||
if (rx) {
|
||||
// Need to prime the # of samples to receive in the engine
|
||||
I2SRXEN = SLC_BUF_LEN;
|
||||
}
|
||||
|
||||
I2SC |= (rx?I2SRXS:0) | (tx?I2STXS:0); // Start transmission/reception
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void i2s_end(){
|
||||
I2SC &= ~I2STXS;
|
||||
void i2s_begin() {
|
||||
i2s_rxtx_begin(false, true);
|
||||
}
|
||||
|
||||
//Reset I2S
|
||||
void i2s_end() {
|
||||
// Disable any I2S send or receive
|
||||
// ? Maybe not needed since we're resetting on the next line...
|
||||
I2SC &= ~(I2STXS | I2SRXS);
|
||||
|
||||
// Reset I2S
|
||||
I2SC &= ~(I2SRST);
|
||||
I2SC |= I2SRST;
|
||||
I2SC &= ~(I2SRST);
|
||||
|
||||
// Redirect IOs to user control/GPIO
|
||||
pinMode(I2SO_WS, INPUT);
|
||||
pinMode(I2SO_DATA, INPUT);
|
||||
pinMode(I2SO_BCK, INPUT);
|
||||
|
||||
i2s_slc_end();
|
||||
|
||||
if (tx) {
|
||||
pinMode(I2SO_DATA, INPUT);
|
||||
pinMode(I2SO_BCK, INPUT);
|
||||
pinMode(I2SO_WS, INPUT);
|
||||
free(tx);
|
||||
tx = NULL;
|
||||
}
|
||||
if (rx) {
|
||||
pinMode(I2SI_DATA, INPUT);
|
||||
pinMode(I2SI_BCK, INPUT);
|
||||
pinMode(I2SI_WS, INPUT);
|
||||
free(rx);
|
||||
rx = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
@ -40,7 +40,8 @@ speed.
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void i2s_begin();
|
||||
void i2s_begin(); // Enable TX only, for compatibility
|
||||
bool i2s_rxtx_begin(bool enableRx, bool enableTx); // Allow TX and/or RX, returns false on OOM error
|
||||
void i2s_end();
|
||||
void i2s_set_rate(uint32_t rate);//Sample Rate in Hz (ex 44100, 48000)
|
||||
void i2s_set_dividers(uint8_t div1, uint8_t div2);//Direct control over output rate
|
||||
@ -48,10 +49,15 @@ float i2s_get_real_rate();//The actual Sample Rate on output
|
||||
bool i2s_write_sample(uint32_t sample);//32bit sample with channels being upper and lower 16 bits (blocking when DMA is full)
|
||||
bool i2s_write_sample_nb(uint32_t sample);//same as above but does not block when DMA is full and returns false instead
|
||||
bool i2s_write_lr(int16_t left, int16_t right);//combines both channels and calls i2s_write_sample with the result
|
||||
bool i2s_read_sample(int16_t *left, int16_t *right, bool blocking); // RX data returned in both 16-bit outputs.
|
||||
bool i2s_is_full();//returns true if DMA is full and can not take more bytes (overflow)
|
||||
bool i2s_is_empty();//returns true if DMA is empty (underflow)
|
||||
bool i2s_rx_is_full();
|
||||
bool i2s_rx_is_empty();
|
||||
int16_t i2s_available();// returns the number of samples than can be written before blocking
|
||||
int16_t i2s_rx_available();// returns the number of samples than can be written before blocking
|
||||
void i2s_set_callback(void (*callback) (void));
|
||||
void i2s_rx_set_callback(void (*callback) (void));
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user