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Make waveform generator a NMI to run always, increase accuracy (#5578)
* Make waveform generator a NMI to run always Make the waveform generator an NMI using the same code as in 2.4.0. Making it NMI will ensure it runs even when interrupts are disabled. Fixes #5568 * Move to a lockless waveform generator Make the waveform generator lockless by doing all dangerous structure updates in the interrupt handler. start/stopWaveform set a flag and cause an interrupt. They wait for the interrupt to complete and clear those flags before returning. Also rework the Waveform[] array to be lockless. * Optimize IRAM and CPU usage in IRQ Try and minimize the IRAM needed to run the IRQ while keeping performance at or better than before. * Avoid WDT errors, optimize pin scans Calculate first and last pins to scan for PWM, significantly increasing accuracy for pulses under 10us at 80MHz. Now if you are using a single PWM channel at 80MHz you can generate a 1.125us pulse (down from ~4us). Rework the IRQ logic to avoid potential WDT errors. When at 80MHz it appears that interrupts occuring faster than 10us apart on the timer cause WDT errors. Avoid it by increasing the minimum delay between IRQs on the timer accordingly. * Clean up format/comment, remove delay() in stop stopWaveform may be called from an interrupt (it's called by digitalWrite) so we can't call delay(). Make it a busy wait for the IRQ to clear the waveform. Only set a new timeout of 10us when starting a new waveform when there is no other event coming sooner than that. Update formatting and comments per @devyte's requests. Replace MicrosecondsToCycles() with standard Arduino call.
This commit is contained in:
Earle F. Philhower, III
GitHub
parent
9515f46684
commit
8a64a1236f
@ -38,84 +38,37 @@
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*/
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#include <Arduino.h>
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#include "ets_sys.h"
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#include "core_esp8266_waveform.h"
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// Need speed, not size, here
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#pragma GCC optimize ("O2")
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// Maximum delay between IRQs
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#define MAXIRQUS (10000)
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// If the cycles from now to an event are below this value, perform it anyway since IRQs take longer than this
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#define CYCLES_FLUFF (100)
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// Macro to get count of predefined array elements
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#define countof(a) ((size_t)(sizeof(a)/sizeof(a[0])))
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// Set/clear *any* GPIO
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#define SetGPIOPin(a) do { if (a < 16) { GPOS |= (1<<a); } else { GP16O |= 1; } } while (0)
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#define ClearGPIOPin(a) do { if (a < 16) { GPOC |= (1<<a); } else { GP16O &= ~1; } } while (0)
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// Set/clear GPIO 0-15
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// Set/clear GPIO 0-15 by bitmask
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#define SetGPIO(a) do { GPOS = a; } while (0)
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#define ClearGPIO(a) do { GPOC = a; } while (0)
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// Waveform generator can create tones, PWM, and servos
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typedef struct {
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uint32_t nextServiceCycle; // ESP cycle timer when a transition required
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uint32_t timeLeftCycles; // For time-limited waveform, how many ESP cycles left
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const uint16_t gpioMask; // Mask instead of value to speed IRQ loop
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const uint16_t gpio16Mask; // Mask instead of value to speed IRQ loop
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unsigned state : 1; // Current state of this pin
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unsigned nextTimeHighCycles : 31; // Copy over low->high to keep smooth waveform
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unsigned enabled : 1; // Is this GPIO generating a waveform?
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unsigned nextTimeLowCycles : 31; // Copy over high->low to keep smooth waveform
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uint32_t expiryCycle; // For time-limited waveform, the cycle when this waveform must stop
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uint32_t nextTimeHighCycles; // Copy over low->high to keep smooth waveform
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uint32_t nextTimeLowCycles; // Copy over high->low to keep smooth waveform
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} Waveform;
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// These can be accessed in interrupts, so ensure to bracket access with SEI/CLI
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static Waveform waveform[] = {
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{0, 0, 1<<0, 0, 0, 0, 0, 0}, // GPIO0
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{0, 0, 1<<1, 0, 0, 0, 0, 0}, // GPIO1
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{0, 0, 1<<2, 0, 0, 0, 0, 0},
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{0, 0, 1<<3, 0, 0, 0, 0, 0},
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{0, 0, 1<<4, 0, 0, 0, 0, 0},
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{0, 0, 1<<5, 0, 0, 0, 0, 0},
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// GPIOS 6-8 not allowed, used for flash
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// GPIO 9 and 10 only allowed in 2-bit flash mode
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#if !isFlashInterfacePin(9)
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{0, 0, 1<<9, 0, 0, 0, 0, 0},
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{0, 0, 1<<10, 0, 0, 0, 0, 0},
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#endif
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// GPIO 11 not allowed, used for flash
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{0, 0, 1<<12, 0, 0, 0, 0, 0},
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{0, 0, 1<<13, 0, 0, 0, 0, 0},
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{0, 0, 1<<14, 0, 0, 0, 0, 0},
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{0, 0, 1<<15, 0, 0, 0, 0, 0},
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{0, 0, 0, 1, 0, 0, 0, 0} // GPIO16
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};
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static Waveform waveform[17]; // State of all possible pins
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static volatile uint32_t waveformState = 0; // Is the pin high or low, updated in NMI so no access outside the NMI code
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static volatile uint32_t waveformEnabled = 0; // Is it actively running, updated in NMI so no access outside the NMI code
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static uint32_t (*timer1CB)() = NULL;;
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// Enable lock-free by only allowing updates to waveformState and waveformEnabled from IRQ service routine
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static volatile uint32_t waveformToEnable = 0; // Message to the NMI handler to start a waveform on a inactive pin
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static volatile uint32_t waveformToDisable = 0; // Message to the NMI handler to disable a pin from waveform generation
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static uint32_t (*timer1CB)() = NULL;
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// Helper functions
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static inline ICACHE_RAM_ATTR uint32_t MicrosecondsToCycles(uint32_t microseconds) {
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return clockCyclesPerMicrosecond() * microseconds;
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}
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static inline ICACHE_RAM_ATTR uint32_t min_u32(uint32_t a, uint32_t b) {
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if (a < b) {
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return a;
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}
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return b;
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}
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static inline ICACHE_RAM_ATTR void ReloadTimer(uint32_t a) {
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// Below a threshold you actually miss the edge IRQ, so ensure enough time
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if (a > 32) {
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timer1_write(a);
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} else {
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timer1_write(32);
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}
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}
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// Non-speed critical bits
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#pragma GCC optimize ("Os")
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static inline ICACHE_RAM_ATTR uint32_t GetCycleCount() {
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uint32_t ccount;
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@ -125,20 +78,18 @@ static inline ICACHE_RAM_ATTR uint32_t GetCycleCount() {
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// Interrupt on/off control
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static ICACHE_RAM_ATTR void timer1Interrupt();
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static uint8_t timerRunning = false;
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static uint32_t lastCycleCount = 0; // Last ESP cycle counter on running the interrupt routine
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static bool timerRunning = false;
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static void initTimer() {
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timer1_disable();
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timer1_isr_init();
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timer1_attachInterrupt(timer1Interrupt);
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lastCycleCount = GetCycleCount();
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ETS_FRC_TIMER1_INTR_ATTACH(NULL, NULL);
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ETS_FRC_TIMER1_NMI_INTR_ATTACH(timer1Interrupt);
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timer1_enable(TIM_DIV1, TIM_EDGE, TIM_SINGLE);
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timerRunning = true;
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}
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static void ICACHE_RAM_ATTR deinitTimer() {
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timer1_attachInterrupt(NULL);
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ETS_FRC_TIMER1_NMI_INTR_ATTACH(NULL);
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timer1_disable();
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timer1_isr_init();
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timerRunning = false;
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@ -149,121 +100,174 @@ void setTimer1Callback(uint32_t (*fn)()) {
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timer1CB = fn;
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if (!timerRunning && fn) {
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initTimer();
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} else if (timerRunning && !fn) {
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int cnt = 0;
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for (size_t i = 0; i < countof(waveform); i++) {
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cnt += waveform[i].enabled ? 1 : 0;
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}
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if (!cnt) {
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timer1_write(microsecondsToClockCycles(1)); // Cause an interrupt post-haste
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} else if (timerRunning && !fn && !waveformEnabled) {
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deinitTimer();
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}
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}
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ReloadTimer(MicrosecondsToCycles(1)); // Cause an interrupt post-haste
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}
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// Start up a waveform on a pin, or change the current one. Will change to the new
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// waveform smoothly on next low->high transition. For immediate change, stopWaveform()
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// first, then it will immediately begin.
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int startWaveform(uint8_t pin, uint32_t timeHighUS, uint32_t timeLowUS, uint32_t runTimeUS) {
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Waveform *wave = NULL;
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for (size_t i = 0; i < countof(waveform); i++) {
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if (((pin == 16) && waveform[i].gpio16Mask==1) || ((pin != 16) && (waveform[i].gpioMask == 1<<pin))) {
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wave = (Waveform*) & (waveform[i]);
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break;
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}
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}
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if (!wave) {
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if ((pin > 16) || isFlashInterfacePin(pin)) {
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return false;
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}
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Waveform *wave = &waveform[pin];
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// Adjust to shave off some of the IRQ time, approximately
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wave->nextTimeHighCycles = microsecondsToClockCycles(timeHighUS);
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wave->nextTimeLowCycles = microsecondsToClockCycles(timeLowUS);
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wave->expiryCycle = runTimeUS ? GetCycleCount() + microsecondsToClockCycles(runTimeUS) : 0;
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if (runTimeUS && !wave->expiryCycle) {
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wave->expiryCycle = 1; // expiryCycle==0 means no timeout, so avoid setting it
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}
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// To safely update the packed bitfields we need to stop interrupts while setting them as we could
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// get an IRQ in the middle of a multi-instruction mask-and-set required to change them which would
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// then cause an IRQ update of these values (.enabled only, for now) to be lost.
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ets_intr_lock();
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wave->nextTimeHighCycles = MicrosecondsToCycles(timeHighUS) - 70; // Take out some time for IRQ codepath
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wave->nextTimeLowCycles = MicrosecondsToCycles(timeLowUS) - 70; // Take out some time for IRQ codepath
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wave->timeLeftCycles = MicrosecondsToCycles(runTimeUS);
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if (!wave->enabled) {
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wave->state = 0;
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uint32_t mask = 1<<pin;
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if (!(waveformEnabled & mask)) {
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// Actually set the pin high or low in the IRQ service to guarantee times
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wave->nextServiceCycle = GetCycleCount() + MicrosecondsToCycles(1);
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wave->enabled = 1;
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wave->nextServiceCycle = GetCycleCount() + microsecondsToClockCycles(1);
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waveformToEnable |= mask;
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if (!timerRunning) {
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initTimer();
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timer1_write(microsecondsToClockCycles(10));
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} else {
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// Ensure timely service....
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if (T1L > microsecondsToClockCycles(10)) {
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timer1_write(microsecondsToClockCycles(10));
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}
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}
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while (waveformToEnable) {
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delay(0); // Wait for waveform to update
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}
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ReloadTimer(MicrosecondsToCycles(1)); // Cause an interrupt post-haste
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}
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// Re-enable interrupts here since we're done with the update
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ets_intr_unlock();
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return true;
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}
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// Speed critical bits
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#pragma GCC optimize ("O2")
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// Normally would not want two copies like this, but due to different
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// optimization levels the inline attribute gets lost if we try the
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// other version.
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static inline ICACHE_RAM_ATTR uint32_t GetCycleCountIRQ() {
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uint32_t ccount;
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__asm__ __volatile__("rsr %0,ccount":"=a"(ccount));
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return ccount;
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}
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static inline ICACHE_RAM_ATTR uint32_t min_u32(uint32_t a, uint32_t b) {
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if (a < b) {
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return a;
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}
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return b;
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}
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// Stops a waveform on a pin
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int ICACHE_RAM_ATTR stopWaveform(uint8_t pin) {
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// Can't possibly need to stop anything if there is no timer active
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if (!timerRunning) {
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return false;
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}
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for (size_t i = 0; i < countof(waveform); i++) {
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if (!waveform[i].enabled) {
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continue; // Skip fast to next one, can't need to stop this one since it's not running
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// If user sends in a pin >16 but <32, this will always point to a 0 bit
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// If they send >=32, then the shift will result in 0 and it will also return false
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uint32_t mask = 1<<pin;
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if (!(waveformEnabled & mask)) {
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return false; // It's not running, nothing to do here
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}
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if (((pin == 16) && waveform[i].gpio16Mask) || ((pin != 16) && (waveform[i].gpioMask == 1<<pin))) {
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// Note that there is no interrupt unsafety here. The IRQ can only ever change .enabled from 1->0
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// We're also doing that, so even if an IRQ occurred it would still stay as 0.
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waveform[i].enabled = 0;
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int cnt = timer1CB ? 1 : 0;
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for (size_t i = 0; (cnt == 0) && (i < countof(waveform)); i++) {
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cnt += waveform[i].enabled ? 1 : 0;
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waveformToDisable |= mask;
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// Ensure timely service....
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if (T1L > microsecondsToClockCycles(10)) {
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timer1_write(microsecondsToClockCycles(10));
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}
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if (!cnt) {
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while (waveformToDisable) {
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/* no-op */ // Can't delay() since stopWaveform may be called from an IRQ
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}
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if (!waveformEnabled && !timer1CB) {
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deinitTimer();
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}
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return true;
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}
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}
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return false;
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}
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static ICACHE_RAM_ATTR void timer1Interrupt() {
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uint32_t nextEventCycles;
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#if F_CPU == 160000000
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uint8_t cnt = 20;
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// The SDK and hardware take some time to actually get to our NMI code, so
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// decrement the next IRQ's timer value by a bit so we can actually catch the
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// real CPU cycle counter we want for the waveforms.
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#if F_CPU == 80000000
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#define DELTAIRQ (microsecondsToClockCycles(3))
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#else
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uint8_t cnt = 10;
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#define DELTAIRQ (microsecondsToClockCycles(2))
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#endif
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static ICACHE_RAM_ATTR void timer1Interrupt() {
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// Optimize the NMI inner loop by keeping track of the min and max GPIO that we
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// are generating. In the common case (1 PWM) these may be the same pin and
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// we can avoid looking at the other pins.
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static int startPin = 0;
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static int endPin = 0;
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uint32_t nextEventCycles = microsecondsToClockCycles(MAXIRQUS);
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uint32_t timeoutCycle = GetCycleCountIRQ() + microsecondsToClockCycles(14);
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if (waveformToEnable || waveformToDisable) {
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// Handle enable/disable requests from main app.
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waveformEnabled = (waveformEnabled & ~waveformToDisable) | waveformToEnable; // Set the requested waveforms on/off
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waveformState &= ~waveformToEnable; // And clear the state of any just started
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waveformToEnable = 0;
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waveformToDisable = 0;
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// Find the first GPIO being generated by checking GCC's find-first-set (returns 1 + the bit of the first 1 in an int32_t)
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startPin = __builtin_ffs(waveformEnabled) - 1;
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// Find the last bit by subtracting off GCC's count-leading-zeros (no offset in this one)
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endPin = 32 - __builtin_clz(waveformEnabled);
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}
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bool done = false;
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if (waveformEnabled) {
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do {
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nextEventCycles = MicrosecondsToCycles(MAXIRQUS);
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for (size_t i = 0; i < countof(waveform); i++) {
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Waveform *wave = &waveform[i];
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uint32_t now;
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nextEventCycles = microsecondsToClockCycles(MAXIRQUS);
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for (int i = startPin; i <= endPin; i++) {
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uint32_t mask = 1<<i;
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// If it's not on, ignore!
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if (!wave->enabled) {
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if (!(waveformEnabled & mask)) {
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continue;
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}
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Waveform *wave = &waveform[i];
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uint32_t now = GetCycleCountIRQ();
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// Disable any waveforms that are done
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if (wave->expiryCycle) {
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int32_t expiryToGo = wave->expiryCycle - now;
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if (expiryToGo < 0) {
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// Done, remove!
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waveformEnabled &= ~mask;
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if (i == 16) {
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GP16O &= ~1;
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} else {
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ClearGPIO(mask);
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}
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continue;
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}
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}
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// Check for toggles
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now = GetCycleCount();
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int32_t cyclesToGo = wave->nextServiceCycle - now;
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if (cyclesToGo < 0) {
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wave->state = !wave->state;
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if (wave->state) {
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SetGPIO(wave->gpioMask);
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if (wave->gpio16Mask) {
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GP16O |= wave->gpio16Mask; // GPIO16 write slow as it's RMW
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waveformState ^= mask;
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if (waveformState & mask) {
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if (i == 16) {
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GP16O |= 1; // GPIO16 write slow as it's RMW
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} else {
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SetGPIO(mask);
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}
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wave->nextServiceCycle = now + wave->nextTimeHighCycles;
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nextEventCycles = min_u32(nextEventCycles, wave->nextTimeHighCycles);
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} else {
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ClearGPIO(wave->gpioMask);
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if (wave->gpio16Mask) {
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GP16O &= ~wave->gpio16Mask;
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if (i == 16) {
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GP16O &= ~1; // GPIO16 write slow as it's RMW
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} else {
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ClearGPIO(mask);
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}
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wave->nextServiceCycle = now + wave->nextTimeLowCycles;
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nextEventCycles = min_u32(nextEventCycles, wave->nextTimeLowCycles);
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@ -273,47 +277,29 @@ static ICACHE_RAM_ATTR void timer1Interrupt() {
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nextEventCycles = min_u32(nextEventCycles, deltaCycles);
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}
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}
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} while (--cnt && (nextEventCycles < MicrosecondsToCycles(4)));
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uint32_t curCycleCount = GetCycleCount();
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uint32_t deltaCycles = curCycleCount - lastCycleCount;
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lastCycleCount = curCycleCount;
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// Check for timed-out waveforms out of the high-frequency toggle loop
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for (size_t i = 0; i < countof(waveform); i++) {
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Waveform *wave = &waveform[i];
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if (wave->enabled && wave->timeLeftCycles) {
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// Check for unsigned underflow with new > old
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if (deltaCycles >= wave->timeLeftCycles) {
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// Done, remove!
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wave->enabled = false;
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ClearGPIO(wave->gpioMask);
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GP16O &= ~wave->gpio16Mask;
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} else {
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uint32_t newTimeLeftCycles = wave->timeLeftCycles - deltaCycles;
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wave->timeLeftCycles = newTimeLeftCycles;
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}
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}
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}
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// Exit the loop if we've hit the fixed runtime limit or the next event is known to be after that timeout would occur
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uint32_t now = GetCycleCountIRQ();
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int32_t cycleDeltaNextEvent = timeoutCycle - (now + nextEventCycles);
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int32_t cyclesLeftTimeout = timeoutCycle - now;
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done = (cycleDeltaNextEvent < 0) || (cyclesLeftTimeout < 0);
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} while (!done);
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} // if (waveformEnabled)
|
||||
|
||||
if (timer1CB) {
|
||||
nextEventCycles = min_u32(nextEventCycles, timer1CB());
|
||||
}
|
||||
|
||||
#if F_CPU == 160000000
|
||||
if (nextEventCycles <= 5 * MicrosecondsToCycles(1)) {
|
||||
nextEventCycles = MicrosecondsToCycles(1) / 2;
|
||||
} else {
|
||||
nextEventCycles -= 5 * MicrosecondsToCycles(1);
|
||||
if (nextEventCycles < microsecondsToClockCycles(10)) {
|
||||
nextEventCycles = microsecondsToClockCycles(10);
|
||||
}
|
||||
nextEventCycles = nextEventCycles >> 1;
|
||||
#else
|
||||
if (nextEventCycles <= 6 * MicrosecondsToCycles(1)) {
|
||||
nextEventCycles = MicrosecondsToCycles(1) / 2;
|
||||
} else {
|
||||
nextEventCycles -= 6 * MicrosecondsToCycles(1);
|
||||
}
|
||||
#endif
|
||||
nextEventCycles -= DELTAIRQ;
|
||||
|
||||
ReloadTimer(nextEventCycles);
|
||||
// Do it here instead of global function to save time and because we know it's edge-IRQ
|
||||
#if F_CPU == 160000000
|
||||
T1L = nextEventCycles >> 1; // Already know we're in range by MAXIRQUS
|
||||
#else
|
||||
T1L = nextEventCycles; // Already know we're in range by MAXIRQUS
|
||||
#endif
|
||||
TEIE |= TEIE1; // Edge int enable
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user