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Correct an issue where write could send data out of order.
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@ -141,7 +141,7 @@ void UARTClass::flush( void )
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size_t UARTClass::write( const uint8_t uc_data )
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size_t UARTClass::write( const uint8_t uc_data )
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{
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{
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if ((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) //is the hardware currently busy?
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if (((_pUart->UART_SR & UART_SR_TXRDY) != UART_SR_TXRDY) | (_tx_buffer->_iTail != _tx_buffer->_iHead)) //is the hardware currently busy?
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{
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{
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//if busy we buffer
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//if busy we buffer
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unsigned int l = (_tx_buffer->_iHead + 1) % SERIAL_BUFFER_SIZE;
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unsigned int l = (_tx_buffer->_iHead + 1) % SERIAL_BUFFER_SIZE;
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