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BREAKING - Use IRAM_ATTR in place of ICACHE_RAM_ATTR (#7921)

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Update the core to use the define that the ESP32 uses, IRAM_ATTR, for
placing code in DRAM.
This commit is contained in:
Earle F. Philhower, III
2021-03-14 16:56:47 -07:00
committed by GitHub
parent 6743a65987
commit 656a33e6f8
26 changed files with 126 additions and 126 deletions
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8
cores/esp8266/uart.cpp
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@ -115,7 +115,7 @@ struct uart_
// called by ISR
inline size_t ICACHE_RAM_ATTR
inline size_t IRAM_ATTR
uart_rx_fifo_available(const int uart_nr)
{
return (USS(uart_nr) >> USRXC) & 0xFF;
@ -144,7 +144,7 @@ uart_rx_available_unsafe(uart_t* uart)
// Copy all the rx fifo bytes that fit into the rx buffer
// called by ISR
inline void ICACHE_RAM_ATTR
inline void IRAM_ATTR
uart_rx_copy_fifo_to_buffer_unsafe(uart_t* uart)
{
struct uart_rx_buffer_ *rx_buffer = uart->rx_buffer;
@ -289,7 +289,7 @@ uart_read(uart_t* uart, char* userbuffer, size_t usersize)
// instead of the uart_isr...uart_rx_copy_fifo_to_buffer_unsafe()
// Since we've already read the bytes from the FIFO, can't use that
// function directly and need to implement it bytewise here
static void ICACHE_RAM_ATTR uart_isr_handle_data(void* arg, uint8_t data)
static void IRAM_ATTR uart_isr_handle_data(void* arg, uint8_t data)
{
uart_t* uart = (uart_t*)arg;
if(uart == NULL || !uart->rx_enabled) {
@ -370,7 +370,7 @@ uart_get_rx_buffer_size(uart_t* uart)
}
// The default ISR handler called when GDB is not enabled
void ICACHE_RAM_ATTR
void IRAM_ATTR
uart_isr(void * arg, void * frame)
{
(void) frame;