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[sam] removing useless peripheral drivers and modifying validation build

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This commit is contained in:
Thibaut VIARD
2011-08-31 10:24:00 +02:00
parent 2260c6875d
commit 5479b611ac
27 changed files with 0 additions and 10217 deletions
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162
hardware/sam/system/libsam/source/acc.c
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@@ -1,162 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup acc_module Working with ACC
* The ACC driver provides the interface to configure and use the ACC peripheral.\n
*
* It applies comparison on two inputs and gives a compare output.
*
* To Enable a ACC Comparison,the user has to follow these few steps:
* <ul>
* <li> Enable ACC peripheral clock by setting the corresponding bit in PMC_PCER1
* (PMC Peripheral Clock Enable Register 1)
* </li>
* <li> Reset the controller by asserting ACC_CR_SWRST in ACC_CR(ACC Control Register)
</li>
* <li> Configure the mode as following steps: </li>
* -# Select inputs for SELMINUS and SELPLUS in ACC_MR (ACC Mode Register).
* -# Enable Analog Comparator by setting ACEN in ACC_MR.
* -# Configure Edge Type to detect different compare output.
* </li>
* <li> Wait until the automatic mask period expires by polling MASK bit in
* ACC_ISR.
* </ul>
*
* For more accurate information, please look at the ACC section of the
* Datasheet.
*
* Related files :\n
* \ref acc.c\n
* \ref acc.h\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of Analog Comparator Controller (ACC).
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Initialize the ACC controller
*
* \param pAcc Pointer to an Acc instance.
* \param idAcc ACC identifier
* \param ucSelplus input connected to inp, 0~7
* \param ucSelminus input connected to inm,0~7
* \param wAc_en Analog comprator enabled/disabled
* \param wEdge CF flag triggering mode
* \param wInvert INVert comparator output,use pattern defined in the device header file
*/
extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, uint8_t ucSelminus,
uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert )
{
/* Enable peripheral clock*/
PMC->PMC_PCER1 = 1 << (idAcc - 32) ;
/* Reset the controller */
pAcc->ACC_CR |= ACC_CR_SWRST ;
/* Write to the MR register */
ACC_CfgModeReg( pAcc,
( (ucSelplus<<ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk ) |
( (ucSelminus<<ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk ) |
( (wAc_en<<8) & ACC_MR_ACEN ) |
( (wEdge<<ACC_MR_EDGETYP_Pos) & ACC_MR_EDGETYP_Msk ) |
( (wInvert<<12) & ACC_MR_INV ) ) ;
/* set hysteresis and current option*/
pAcc->ACC_ACR = (ACC_ACR_ISEL_HISP | ((0x01 << ACC_ACR_HYST_Pos) & ACC_ACR_HYST_Msk));
/* Automatic Output Masking Period*/
while ( pAcc->ACC_ISR & (uint32_t)ACC_ISR_MASK ) ;
}
/**
* Return the Channel Converted Data
* \param pAcc Pointer to an Acc instance.
* \param selplus input applied on ACC SELPLUS
* \param selminus input applied on ACC SELMINUS
*/
extern void ACC_SetComparisionPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus )
{
uint32_t dwTemp ;
assert( ucSelplus < 8 && ucSelminus < 8 ) ;
dwTemp = pAcc->ACC_MR ;
pAcc->ACC_MR = dwTemp & (uint32_t) ((~ACC_MR_SELMINUS_Msk) & (~ACC_MR_SELPLUS_Msk));
pAcc->ACC_MR |= ( ((ucSelplus << ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk) |
((ucSelminus << ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk) ) ;
}
/**
* Return Comparison Result
* \param pAcc Pointer to an Acc instance.
* \param status value of ACC_ISR
*/
extern uint32_t ACC_GetComparisionResult( Acc *pAcc, uint32_t dwStatus )
{
uint32_t dwTemp = pAcc->ACC_MR ;
if ( (dwTemp & ACC_MR_INV) == ACC_MR_INV )
{
if ( dwStatus & ACC_ISR_SCO )
{
return 0 ; /* inn>inp*/
}
else
{
return 1 ;/* inp>inn*/
}
}
else
{
if ( dwStatus & ACC_ISR_SCO )
{
return 1 ; /* inp>inn*/
}
else
{
return 0 ;/* inn>inp*/
}
}
}

53
hardware/sam/system/libsam/source/async.c
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@@ -1,53 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/**
* \file
*
* Provide a routine for asynchronos transfer.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* \brief Returns 1 if the given transfer has ended; otherwise returns 0.
* \param pAsync Pointer to an Async instance.
*/
uint32_t ASYNC_IsFinished( Async* pAsync )
{
return (pAsync->status != ASYNC_STATUS_PENDING) ;
}

112
hardware/sam/system/libsam/source/crccu.c
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@@ -1,112 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup crccu_module Working with CRCCU
* The CRCCU driver provides the interface to configure and use the CRCCU
* peripheral.
*
* It performs a CRC computation on a Memory Area. CRC computation is performed
* from the LSB to MSB bit. Three different polynomials are available:
* CCIT802.3, CASTAGNOLI and CCIT16.
*
* To computes CRC of a buffer, the user has to follow these few steps:
* <ul>
* <li>Reset initial CRC by setting RESET bit in CRCCU_CRC_CR,</li>
* <li>Configure CRC descriptor and working mode,</li>
* <li>Start to compute CRC by setting DMAEN in CRCCU_DMA_EN,</li>
* <li>Get CRC value in CRCCU_CRC_SR.</li>
* </ul>
*
* For more accurate information, please look at the CRCCU section of the
* Datasheet.
*
* Related files :\n
* \ref crccu.c\n
* \ref crccu.h.\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of Cyclic Redundancy Check Calculation Unit (CRCCU).
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/*----------------------------------------------------------------------------
* Definitions
*----------------------------------------------------------------------------*/
#define CRCCU_TIMEOUT 0xFFFFFFFF
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Reset initial CRC to 0xFFFFFFFF.
*/
extern void CRCCU_ResetCrcValue( Crccu* pCrccu )
{
pCrccu->CRCCU_CR = CRCCU_CR_RESET;
}
/**
* \brief Configure the CRCCU.
*
* \param dscrAddr CRC decscriptor address.
* \param mode CRC work mode
*/
extern void CRCCU_Configure( Crccu* pCrccu, uint32_t dwDscrAddr, uint32_t dwMode )
{
pCrccu->CRCCU_DSCR = dwDscrAddr ;
pCrccu->CRCCU_MR = dwMode ;
}
/**
* \brief Start to compute the CRC of a buffer.
*
* \return The CRC of the buffer.
*/
extern uint32_t CRCCU_ComputeCrc( Crccu* pCrccu )
{
uint32_t dwTimeout = 0 ;
pCrccu->CRCCU_DMA_EN = CRCCU_DMA_EN_DMAEN ;
while ( ((pCrccu->CRCCU_DMA_SR & CRCCU_DMA_SR_DMASR) == CRCCU_DMA_SR_DMASR) &&
(dwTimeout++ < CRCCU_TIMEOUT) ) ;
return (pCrccu->CRCCU_SR) ;
}

183
hardware/sam/system/libsam/source/dacc.c
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@@ -1,183 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup dacc_module Working with DACC
* The DACC driver provides the interface to configure and use the DACC peripheral.\n
*
* The DACC(Digital-to-Analog Converter Controller) converts digital code to analog output.
* The data to be converted are sent in a common register for all channels. It offers up to 2
* analog outputs.The output voltage ranges from (1/6)ADVREF to (5/6)ADVREF.
*
* To Enable a DACC conversion,the user has to follow these few steps:
* <ul>
* <li> Select an appropriate reference voltage on ADVREF </li>
* <li> Configure the DACC according to its requirements and special needs,which could be
broken down into several parts:
* -# Enable DACC in free running mode by clearing TRGEN in DACC_MR;
* -# Configure Startup Time and Refresh Period through setting STARTUP and REFRESH fields
* in DACC_MR; The refresh mechanism is used to protect the output analog value from
* decreasing.
* -# Enable channels and write digital code to DACC_CDR,in free running mode, the conversion
* is started right after at least one channel is enabled and data is written .
</li>
* </ul>
*
* For more accurate information, please look at the DACC section of the
* Datasheet.
*
* Related files :\n
* \ref DACC.c\n
* \ref DACC.h\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of Digital-to-Analog Converter Controller (DACC).
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdint.h>
#include <assert.h>
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Initialize the DACC controller
* \param pDACC Pointer to an DACC instance.
* \param idDACC identifier of DAC peripheral
* \param trgEn trigger mode, free running mode or external Hardware trigger
* \param word transfer size,word or half word
* \param trgSel hardware trigger selection
* \param sleepMode sleep mode selection
* \param mck value of MCK in Hz
* \param refresh refresh period
* \param user_sel user channel selection ,0 or 1
* \param tag_mode tag for channel number
* \param startup value of the start up time (in DACCClock) (see datasheet)
*/
extern void DACC_Initialize( Dacc* pDACC,
uint8_t idDACC,
uint8_t trgEn,
uint8_t trgSel,
uint8_t word,
uint8_t sleepMode,
uint32_t mck,
uint8_t refresh, /* refresh period */
uint8_t user_sel, /* user channel selection */
uint32_t tag_mode, /* using tag for channel number */
uint32_t startup
)
{
assert( 1024*refresh*1000/(mck>>1) < 20 ) ;
/* Enable peripheral clock*/
PMC->PMC_PCER0 = 1 << idDACC;
/* Reset the controller */
DACC_SoftReset(pDACC);
/* Write to the MR register */
DACC_CfgModeReg( pDACC,
( (trgEn<<0) & DACC_MR_TRGEN)
| DACC_MR_TRGSEL(trgSel)
| ( (word<<4) & DACC_MR_WORD)
| ( (sleepMode<<5) & DACC_MR_SLEEP)
| DACC_MR_REFRESH(refresh)
| ( (user_sel<<DACC_MR_USER_SEL_Pos)& DACC_MR_USER_SEL_Msk)
| ( (tag_mode<<20) & DACC_MR_TAG)
| ( (startup<<DACC_MR_STARTUP_Pos) & DACC_MR_STARTUP_Msk));
}
/**
* Set the Conversion Data
* \param pDACC Pointer to an Dacc instance.
* \param data date to be converted.
*/
extern void DACC_SetConversionData( Dacc* pDACC, uint32_t dwData )
{
uint32_t dwMR = pDACC->DACC_MR ;
if ( dwMR & DACC_MR_WORD )
{
pDACC->DACC_CDR = dwData ;
}
else
{
pDACC->DACC_CDR = (dwData&0xFFFF) ;
}
}
/**
* \brief Write converted data through PDC channel
* \param pDACC the pointer of DACC peripheral
* \param pBuffer the destination buffer
* \param size the size of the buffer
*/
extern uint32_t DACC_WriteBuffer( Dacc* pDACC, uint16_t *pwBuffer, uint32_t dwSize )
{
/* Check if the first PDC bank is free*/
if ( (pDACC->DACC_TCR == 0) && (pDACC->DACC_TNCR == 0) )
{
pDACC->DACC_TPR = (uint32_t)pwBuffer ;
pDACC->DACC_TCR = dwSize ;
pDACC->DACC_PTCR = DACC_PTCR_TXTEN ;
return 1 ;
}
/* Check if the second PDC bank is free*/
else
{
if (pDACC->DACC_TNCR == 0)
{
pDACC->DACC_TNPR = (uint32_t)pwBuffer ;
pDACC->DACC_TNCR = dwSize ;
return 1 ;
}
else
{
return 0 ;
}
}
}

284
hardware/sam/system/libsam/source/pio_capture.c
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@@ -1,284 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2010, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup pio_capture_module Working with PIO Parallel Capture Mode
* The PIO Parallel Capture Mode driver provides the interface to configure and use the
* PIO Parallel Capture Mode peripheral.\n
*
* The PIO Controller integrates an interface able to read data from a CMOS digital
* image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous
* mode, etc.... For better understanding and to ease reading, the following
* description uses an example with a CMOS digital image sensor
*
* To use the PIO Parallel Capture, the user has to follow these few steps:
* <ul>
* <li> Enable PIOA peripheral clock </li>
* <li> Configure the PDC </li>
* <li> Configure the PIO Capture interrupt </li>
* <li> Enable the PDC </li>
* <li> Enable the PIO Capture </li>
* <li> Wait for interrupt </li>
* <li> Disable the interrupt </li>
* <li> Read the DATA </li>
* </ul>
*
* For more accurate information, please look at the PIO Parallel Capture Mode section of the
* Datasheet.
*
* Related files :\n
* \ref pio_capture.c\n
* \ref pio_capture.h\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of PIO Parallel Capture.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdlib.h>
#include <assert.h>
/*----------------------------------------------------------------------------
* Local Functions
*----------------------------------------------------------------------------*/
/** Copy the API structure for interrupt handler */
static SPioCaptureInit* _PioCaptureCopy ;
/*----------------------------------------------------------------------------
* Global Functions
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/**
* \brief The PIO_CaptureHandler must be called by the PIO Capture Interrupt
* Service Routine with the corresponding PIO Capture instance.
*/
/*----------------------------------------------------------------------------*/
extern void PIO_CaptureHandler( void )
{
volatile uint32_t pio_captureSr;
/* Read the status register*/
pio_captureSr = PIOA->PIO_PCISR ;
pio_captureSr &= PIOA->PIO_PCIMR ;
if (pio_captureSr & PIO_PCISR_DRDY)
{
/* Parallel Capture Mode Data Ready */
if ( _PioCaptureCopy->CbkDataReady != NULL )
{
_PioCaptureCopy->CbkDataReady( _PioCaptureCopy );
}
else
{
// TRACE_DEBUG("IT PIO Capture Data Ready received (no callback)\n\r");
}
}
if (pio_captureSr & PIO_PCISR_OVRE)
{
/* Parallel Capture Mode Overrun Error */
if ( _PioCaptureCopy->CbkOverrun != NULL )
{
_PioCaptureCopy->CbkOverrun( _PioCaptureCopy );
}
else
{
// TRACE_DEBUG("IT PIO Capture Overrun Error received (no callback)\n\r");
}
}
if (pio_captureSr & PIO_PCISR_RXBUFF)
{
/* Reception Buffer Full */
if ( _PioCaptureCopy->CbkBuffFull != NULL )
{
_PioCaptureCopy->CbkBuffFull( _PioCaptureCopy );
}
else
{
// TRACE_DEBUG("IT PIO Capture Reception Buffer Full received (no callback)\n\r");
}
}
if (pio_captureSr & PIO_PCISR_ENDRX)
{
/* End of Reception Transfer */
if ( _PioCaptureCopy->CbkEndReception != NULL )
{
_PioCaptureCopy->CbkEndReception( _PioCaptureCopy );
}
else
{
// TRACE_DEBUG("IT PIO Capture End of Reception Transfer received (no callback)\n\r");
}
}
}
/*----------------------------------------------------------------------------*/
/**
* \brief Disable Interupt of the PIO Capture
* \param itToDisable : Interrupt to disable
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureDisableIt( uint32_t itToDisable )
{
/* Parallel capture mode is enabled */
PIOA->PIO_PCIDR = itToDisable;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Enable Interupt of the PIO Capture
* \param itToEnable : Interrupt to enable
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureEnableIt( uint32_t itToEnable )
{
/* Parallel capture mode is enabled */
PIOA->PIO_PCIER = itToEnable;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Enable the PIO Capture
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureEnable( void )
{
/* PDC: Receive Pointer Register */
PIOA->PIO_RPR = (uint32_t)_PioCaptureCopy->pData ;
/* PDC: Receive Counter Register */
/* Starts peripheral data transfer if corresponding channel is active */
PIOA->PIO_RCR = PIO_RCR_RXCTR(_PioCaptureCopy->dPDCsize) ;
/* Parallel capture mode is enabled */
PIOA->PIO_PCMR |= PIO_PCMR_PCEN ;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Disable the PIO Capture
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureDisable( void )
{
/* Parallel capture mode is disabled */
PIOA->PIO_PCMR &= (uint32_t)(~PIO_PCMR_PCEN) ;
}
/*----------------------------------------------------------------------------*/
/**
* \brief Initialize the PIO Capture
* Be careful to configure the PDC before enable interrupt on pio capture.
* Otherway, the pdc will go in interrupt handler continuously.
* \param dsize :
* 0 = The reception data in the PIO_PCRHR register is a BYTE (8-bit).
* 1 = The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit).
* 2/3 = The reception data in the PIO_PCRHR register is a WORD (32-bit).
* \param alwaysSampling: ALWYS: Parallel Capture Mode Always Sampling
* 0 = The parallel capture mode samples the data when both data enables are active.
* 1 = The parallel capture mode samples the data whatever the data enables are.
* \param halfSampling: HALFS: Parallel Capture Mode Half Sampling
* 0 = The parallel capture mode samples all the data.
* 1 = The parallel capture mode samples the data only one time out of two.
* \param modeFirstSample: FRSTS: Parallel Capture Mode First Sample
* This bit is useful only if the HALFS bit is set to 1. If data are numbered
* in the order that they are received with an index from 0 to n:
* 0 = Only data with an even index are sampled.
* 1 = Only data with an odd index are sampled.
*/
/*----------------------------------------------------------------------------*/
void PIO_CaptureInit( SPioCaptureInit *pInit )
{
PMC_EnablePeripheral( ID_PIOA );
assert( (pInit->dsize < 0x4) ) ;
assert( (pInit->dPDCsize <= PIO_RPR_RXPTR_Msk) ) ;
assert( (pInit->alwaysSampling < 2) );
assert( (pInit->halfSampling < 2) );
assert( (pInit->modeFirstSample < 2) );
/* PDC: Transfer Control Register */
/* Disables the PDC transmitter channel requests */
PIOA->PIO_PTCR = PIO_PTCR_RXTDIS;
/* PDC: Receive Pointer Register */
PIOA->PIO_RPR = (uint32_t)pInit->pData;
/* PDC: Receive Counter Register */
/* Starts peripheral data transfer if corresponding channel is active */
PIOA->PIO_RCR = PIO_RCR_RXCTR(pInit->dPDCsize);
/* PDC: Transfer Control Register */
/* Enables PDC receiver channel requests if RXTDIS is not set */
PIOA->PIO_PTCR = PIO_PTCR_RXTEN ;
/* Copy the API structure for interrupt handler */
_PioCaptureCopy = pInit;
/* PIO Parallel Capture Mode */
PIOA->PIO_PCMR = PIO_PCMR_DSIZE(pInit->dsize)
| ((pInit->alwaysSampling<<9) & PIO_PCMR_ALWYS)
| ((pInit->halfSampling<<10) & PIO_PCMR_HALFS)
| ((pInit->modeFirstSample<<11) & PIO_PCMR_FRSTS);
if ( pInit->CbkDataReady != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_DRDY;
}
if ( pInit->CbkOverrun != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_OVRE;
}
if ( pInit->CbkEndReception != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_ENDRX;
}
if ( pInit->CbkBuffFull != NULL )
{
PIOA->PIO_PCIER = PIO_PCISR_RXBUFF;
}
// else
// {
// TRACE_INFO("No interruption, no callback\n\r");
// }
}

251
hardware/sam/system/libsam/source/spi_pdc.c
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@@ -1,251 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup spi_pdc_module SPI PDC driver
* \ingroup spi_at45_module
* The Spi driver is a low level spi driver which performs SPI device Initializes,
* spi transfer and receive. It can be used by upper SPI driver such as AT45
* driver and AT26 driver.
*
* \section Usage
* <ul>
* <li> Initializes a SPI instance and the corresponding SPI hardware,
* Configure SPI in Master Mode using SPID_Configure().</li>
* <li> Configures the SPI characteristics (such as Clock Polarity, Phase,
* transfers delay and Baud Rate) for the device corresponding to the
* chip select using SPID_ConfigureCS().</li>
* <li> Starts a SPI master transfer using SPID_SendCommand().
* The transfer is performed using the PDC channels. </li>
* <li> It enable the SPI clock.</li>
* <li> Set the corresponding peripheral chip select.</li>
* <li> Initialize the two SPI PDC buffers.</li>
* <li> Initialize SPI_TPR and SPI_TCR with SPI command data and size
* to send command data first.</li>
* <li> Initialize SPI_RPR and SPI_RCR with SPI command data and size
* as dummy value.</li>
* <li> Initialize SPI_TNPR and SPI_TNCR with rest of the data to be
* transfered.(if the data specified in cmd structure)</li>
* <li> Initialize SPI_RNPR and SPI_RNCR with rest of the data to be
* received.(if the data specified in cmd structure)</li>
* <li> Initialize the callback function if specified.</li>
* <li> Enable transmitter and receiver.</li>
* <li> Example for sending a command to the dataflash through the SPI.</li>
* \code
* /// Build command to be sent.
* ...
* // Send Command and data through the SPI
* if (SPID_SendCommand(pAt45->pSpid, pCommand)) {
* return AT45_ERROR_SPI;
* }
* \endcode
* <li> The SPI_Handler() must be called by the SPI Interrupt Service Routine
* with the corresponding Spi instance. It is invokes to check for pending
* interrupts. </li>
* <li> Example for initializing SPI interrupt handler in upper application.</li>
* \code
* AIC_ConfigureIT(AT91C_ID_SPI, 0, SPI_Handler);
* \endcode
* </ul>
* Related files :\n
* \ref spi_pdc.c\n
* \ref spi_pdc.h.\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of SPI PDC driver.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Initializes the Spid structure and the corresponding SPI hardware.
*
* \param pSpid Pointer to a Spid instance.
* \param pSpiHw Associated SPI peripheral.
* \param spiId SPI peripheral identifier.
* \return 0.
*/
extern uint32_t SPID_Configure( Spid* pSpid, Spi* pSpiHw, uint8_t spiId )
{
/* Initialize the SPI structure*/
pSpid->pSpiHw = pSpiHw ;
pSpid->spiId = spiId ;
pSpid->semaphore = 1 ;
pSpid->pCurrentCommand = 0 ;
/* Enable the SPI clock*/
PMC_EnablePeripheral( pSpid->spiId ) ;
/* Configure SPI in Master Mode with No CS selected !!! */
SPI_Configure( pSpiHw, pSpid->spiId, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS_Msk ) ;
/* Enable the SPI */
SPI_Enable( pSpiHw ) ;
/* Disable the SPI clock */
PMC_DisablePeripheral( pSpid->spiId ) ;
return 0 ;
}
/**
* \brief Configures the parameters for the device corresponding to the cs.
*
* \param pSpid Pointer to a Spid instance.
* \param cs number corresponding to the SPI chip select.
* \param csr SPI_CSR value to setup.
*/
extern void SPID_ConfigureCS( Spid* pSpid, uint32_t dwCS, uint32_t dwCSR )
{
SPI_ConfigureNPCS( pSpid->pSpiHw, dwCS, dwCSR ) ;
}
/**
* \brief Starts a SPI master transfer. This is a non blocking function. It will
* return as soon as the transfer is started.
*
* \param pSpid Pointer to a Spid instance.
* \param pCommand Pointer to the SPI command to execute.
* \return 0 if the transfer has been started successfully; otherwise returns
* SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not
* valid.
*/
extern uint32_t SPID_SendCommand( Spid* pSpid, SpidCmd* pCommand )
{
Spi* pSpiHw = pSpid->pSpiHw ;
uint32_t dwSpiMr ;
/* Try to get the dataflash semaphore */
if ( pSpid->semaphore == 0 )
{
return SPID_ERROR_LOCK ;
}
pSpid->semaphore-- ;
/* Enable the SPI clock */
PMC_EnablePeripheral( pSpid->spiId ) ;
/* Disable transmitter and receiver*/
SPI_PdcDisableRx( pSpiHw ) ;
SPI_PdcDisableTx( pSpiHw ) ;
/* Write to the MR register*/
dwSpiMr = pSpiHw->SPI_MR ;
dwSpiMr |= SPI_MR_PCS_Msk ;
dwSpiMr &= ~((1 << pCommand->spiCs) << 16 ) ;
pSpiHw->SPI_MR=dwSpiMr ;
/* Initialize the two SPI PDC buffer*/
SPI_PdcSetRx( pSpiHw, pCommand->pCmd, pCommand->cmdSize, pCommand->pData, pCommand->dataSize ) ;
SPI_PdcSetTx( pSpiHw, pCommand->pCmd, pCommand->cmdSize, pCommand->pData, pCommand->dataSize ) ;
/* Initialize the callback*/
pSpid->pCurrentCommand = pCommand ;
/* Enable transmitter and receiver*/
SPI_PdcEnableRx( pSpiHw ) ;
SPI_PdcEnableTx( pSpiHw ) ;
/* Enable buffer complete interrupt*/
SPI_EnableIt( pSpiHw, SPI_IER_RXBUFF ) ;
return 0 ;
}
/**
* \brief The SPI_Handler must be called by the SPI Interrupt Service Routine with the
* corresponding Spi instance.
*
* \note The SPI_Handler will unlock the Spi semaphore and invoke the upper application
* callback.
* \param pSpid Pointer to a Spid instance.
*/
extern void SPID_Handler( Spid* pSpid )
{
SpidCmd *pSpidCmd = pSpid->pCurrentCommand ;
Spi *pSpiHw = pSpid->pSpiHw ;
volatile uint32_t spiSr ;
/* Read the status register*/
spiSr = pSpiHw->SPI_SR ;
if ( spiSr & SPI_SR_RXBUFF )
{
/* Disable transmitter and receiver */
SPI_PdcDisableRx( pSpiHw ) ;
SPI_PdcDisableTx( pSpiHw ) ;
/* Disable the SPI clock*/
PMC_DisablePeripheral( pSpid->spiId ) ;
/* Disable buffer complete interrupt */
SPI_DisableIt( pSpiHw, SPI_IDR_RXBUFF ) ;
/* Release the dataflash semaphore*/
pSpid->semaphore++ ;
/* Invoke the callback associated with the current command*/
if ( pSpidCmd && pSpidCmd->callback )
{
pSpidCmd->callback( 0, pSpidCmd->pArgument ) ;
}
/* Nothing must be done after. A new DF operation may have been started
in the callback function.*/
}
}
/**
* \brief Returns 1 if the SPI driver is currently busy executing a command; otherwise
* returns 0.
* \param pSpid Pointer to a Spid instance.
*/
extern uint32_t SPID_IsBusy( const Spid* pSpid )
{
if ( pSpid->semaphore == 0 )
{
return 1 ;
}
else
{
return 0 ;
}
}

247
hardware/sam/system/libsam/source/ssc.c
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@@ -1,247 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/** \addtogroup ssc_module Working with SSC
* The SSC driver provides the interface to configure and use the SSC
* peripheral.
*
* !Usage
*
* -# Enable the SSC interface pins.
* -# Configure the SSC to operate at a specific frequency by calling
* SSC_Configure(). This function enables the peripheral clock of the SSC,
* but not its PIOs.
* -# Configure the transmitter and/or the receiver using the
* SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions.
* -# Enable the PIOs or the transmitter and/or the received.
* -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter()
* and SSC_EnableReceiver()
* -# Send data through the transmitter using SSC_Write() and SSC_WriteBuffer()
* -# Receive data from the receiver using SSC_Read() and SSC_ReadBuffer()
* -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter()
* and SSC_DisableReceiver()
*
* For more accurate information, please look at the RTC section of the
* Datasheet.
*
* Related files :\n
* \ref ssc.c\n
* \ref ssc.h.\n
*/
/*@{*/
/*@}*/
/**
* \file
*
* Implementation of Synchronous Serial (SSC) controller.
*
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
/*----------------------------------------------------------------------------
* Exported functions
*----------------------------------------------------------------------------*/
/**
* \brief Configures a SSC peripheral.If the divided clock is not used, the master
* clock frequency can be set to 0.
* \note The emitter and transmitter are disabled by this function.
* \param bitRate bit rate.
* \param masterClock master clock.
*/
void SSC_Configure(uint32_t bitRate, uint32_t masterClock)
{
/* Enable SSC peripheral clock */
PMC->PMC_PCER0 = 1 << ID_SSC;
/* Reset, disable receiver & transmitter */
SSC->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST;
SSC->SSC_PTCR = SSC_PTCR_RXTDIS | SSC_PTCR_TXTDIS;
/* Configure clock frequency */
if (bitRate != 0) {
SSC->SSC_CMR = masterClock / (2 * bitRate);
}
else {
SSC->SSC_CMR = 0;
}
}
/**
* \brief Configures the transmitter of a SSC peripheral.
* \param tcmr Transmit Clock Mode Register value.
* \param tfmr Transmit Frame Mode Register value.
*/
void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr)
{
SSC->SSC_TCMR = tcmr;
SSC->SSC_TFMR = tfmr;
}
/**
* \brief Configures the receiver of a SSC peripheral.
* \param rcmr Receive Clock Mode Register value.
* \param rfmr Receive Frame Mode Register value.
*/
void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr)
{
SSC->SSC_RCMR = rcmr;
SSC->SSC_RFMR = rfmr;
}
/**
* \brief Enables the transmitter of a SSC peripheral.
*/
void SSC_EnableTransmitter(void)
{
SSC->SSC_CR = SSC_CR_TXEN;
}
/**
* \brief Disables the transmitter of a SSC peripheral.
*/
void SSC_DisableTransmitter(void)
{
SSC->SSC_CR = SSC_CR_TXDIS;
}
/**
* \brief Enables the receiver of a SSC peripheral.
*/
void SSC_EnableReceiver(void)
{
SSC->SSC_CR = SSC_CR_RXEN;
}
/**
* \brief Disables the receiver of a SSC peripheral.
*/
void SSC_DisableReceiver(void)
{
SSC->SSC_CR = SSC_CR_RXDIS;
}
/**
* \brief Enables one or more interrupt sources of a SSC peripheral.
* \param sources Bitwise OR of selected interrupt sources.
*/
void SSC_EnableInterrupts(uint32_t sources)
{
SSC->SSC_IER = sources;
}
/**
* \brief Disables one or more interrupt sources of a SSC peripheral.
* \param sources Bitwise OR of selected interrupt sources.
*/
void SSC_DisableInterrupts(uint32_t sources)
{
SSC->SSC_IDR = sources;
}
/**
* \brief Sends one data frame through a SSC peripheral. If another frame is currently
* being sent, this function waits for the previous transfer to complete.
* \param frame Data frame to send.
*/
void SSC_Write(uint32_t frame)
{
while ((SSC->SSC_SR & SSC_SR_TXRDY) == 0);
SSC->SSC_THR = frame;
}
/**
* \brief Waits until one frame is received on a SSC peripheral, and returns it.
*/
uint32_t SSC_Read(void)
{
while ((SSC->SSC_SR & SSC_SR_RXRDY) == 0);
return SSC->SSC_RHR;
}
/**
* \brief Sends the contents of a data buffer a SSC peripheral, using the PDC.
* \param buffer Data buffer to send.
* \param length Size of the data buffer.
* \return 1 if the buffer has been queued for transmission; otherwise returns 0.
*/
uint8_t SSC_WriteBuffer(void *buffer, uint32_t length)
{
/* Check if first bank is free*/
if (SSC->SSC_TCR == 0) {
SSC->SSC_TPR = (uint32_t) buffer;
SSC->SSC_TCR = length;
SSC->SSC_PTCR = SSC_PTCR_TXTEN;
return 1;
}
/* Check if second bank is free*/
else if (SSC->SSC_TNCR == 0) {
SSC->SSC_TNPR = (uint32_t) buffer;
SSC->SSC_TNCR = length;
return 1;
}
return 0;
}
/**
* \brief Reads data coming from a SSC peripheral receiver and stores it into the
* giving buffer with PDC.
* \param buffer ata buffer used for reception.
* \param length Size of the data buffer.
* \return 1 if the buffer has been queued for reception; otherwise returns 0.
*/
uint8_t SSC_ReadBuffer(void *buffer, uint32_t length)
{
/* Check if the first bank is free*/
if (SSC->SSC_RCR == 0) {
SSC->SSC_RPR = (uint32_t) buffer;
SSC->SSC_RCR = length;
SSC->SSC_PTCR = SSC_PTCR_RXTEN;
return 1;
}
/* Check if second bank is free*/
else if (SSC->SSC_RNCR == 0) {
SSC->SSC_RNPR = (uint32_t) buffer;
SSC->SSC_RNCR = length;
return 1;
}
return 0;
}

341
hardware/sam/system/libsam/source/twid.c
View File

@@ -1,341 +0,0 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2009, Atmel Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* Headers
*----------------------------------------------------------------------------*/
#include "chip.h"
#include <stdlib.h>
#include <assert.h>
/*----------------------------------------------------------------------------
* Definition
*----------------------------------------------------------------------------*/
#define TWITIMEOUTMAX 50000
/*----------------------------------------------------------------------------
* Types
*----------------------------------------------------------------------------*/
/** TWI driver callback function.*/
typedef void (*TwiCallback)(Async *);
/** \brief TWI asynchronous transfer descriptor.*/
typedef struct _AsyncTwi {
/** Asynchronous transfer status. */
volatile uint8_t status;
// Callback function to invoke when transfer completes or fails.*/
TwiCallback callback;
/** Pointer to the data buffer.*/
uint8_t *pData;
/** Total number of bytes to transfer.*/
uint32_t num;
/** Number of already transferred bytes.*/
uint32_t transferred;
} AsyncTwi;
/*----------------------------------------------------------------------------
* Global functions
*----------------------------------------------------------------------------*/
/**
* \brief Initializes a TWI driver instance, using the given TWI peripheral.
* \note The peripheral must have been initialized properly before calling this function.
* \param pTwid Pointer to the Twid instance to initialize.
* \param pTwi Pointer to the TWI peripheral to use.
*/
void TWID_Initialize(Twid *pTwid, Twi *pTwi)
{
assert( pTwid != NULL ) ;
assert( pTwi != NULL ) ;
/* Initialize driver. */
pTwid->pTwi = pTwi;
pTwid->pTransfer = 0;
}
/**
* \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer
* occuring on the bus. This function MUST be called by the interrupt service
* routine of the TWI peripheral if asynchronous read/write are needed.
* \param pTwid Pointer to a Twid instance.
*/
void TWID_Handler( Twid *pTwid )
{
uint8_t status;
AsyncTwi *pTransfer ;
Twi *pTwi ;
assert( pTwid != NULL ) ;
pTransfer = (AsyncTwi*)pTwid->pTransfer ;
assert( pTransfer != NULL ) ;
pTwi = pTwid->pTwi ;
assert( pTwi != NULL ) ;
/* Retrieve interrupt status */
status = TWI_GetMaskedStatus(pTwi);
/* Byte received */
if (TWI_STATUS_RXRDY(status)) {
pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi);
pTransfer->transferred++;
/* check for transfer finish */
if (pTransfer->transferred == pTransfer->num) {
TWI_DisableIt(pTwi, TWI_IDR_RXRDY);
TWI_EnableIt(pTwi, TWI_IER_TXCOMP);
}
/* Last byte? */
else if (pTransfer->transferred == (pTransfer->num - 1)) {
TWI_Stop(pTwi);
}
}
/* Byte sent*/
else if (TWI_STATUS_TXRDY(status)) {
/* Transfer finished ? */
if (pTransfer->transferred == pTransfer->num) {
TWI_DisableIt(pTwi, TWI_IDR_TXRDY);
TWI_EnableIt(pTwi, TWI_IER_TXCOMP);
TWI_SendSTOPCondition(pTwi);
}
/* Bytes remaining */
else {
TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]);
pTransfer->transferred++;
}
}
/* Transfer complete*/
else if (TWI_STATUS_TXCOMP(status)) {
TWI_DisableIt(pTwi, TWI_IDR_TXCOMP);
pTransfer->status = 0;
if (pTransfer->callback) {
pTransfer->callback((Async *) pTransfer);
}
pTwid->pTransfer = 0;
}
}
/**
* \brief Asynchronously reads data from a slave on the TWI bus. An optional
* callback function is triggered when the transfer is complete.
* \param pTwid Pointer to a Twid instance.
* \param address TWI slave address.
* \param iaddress Optional slave internal address.
* \param isize Internal address size in bytes.
* \param pData Data buffer for storing received bytes.
* \param num Number of bytes to read.
* \param pAsync Asynchronous transfer descriptor.
* \return 0 if the transfer has been started; otherwise returns a TWI error code.
*/
uint8_t TWID_Read(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync)
{
Twi *pTwi;
AsyncTwi *pTransfer;
uint32_t timeout;
assert( pTwid != NULL ) ;
pTwi = pTwid->pTwi;
pTransfer = (AsyncTwi *) pTwid->pTransfer;
assert( (address & 0x80) == 0 ) ;
assert( (iaddress & 0xFF000000) == 0 ) ;
assert( isize < 4 ) ;
/* Check that no transfer is already pending*/
if (pTransfer) {
return TWID_ERROR_BUSY;
}
/* Set STOP signal if only one byte is sent*/
if (num == 1) {
TWI_Stop(pTwi);
}
/* Asynchronous transfer*/
if (pAsync) {
/* Update the transfer descriptor */
pTwid->pTransfer = pAsync;
pTransfer = (AsyncTwi *) pAsync;
pTransfer->status = ASYNC_STATUS_PENDING;
pTransfer->pData = pData;
pTransfer->num = num;
pTransfer->transferred = 0;
/* Enable read interrupt and start the transfer */
TWI_EnableIt(pTwi, TWI_IER_RXRDY);
TWI_StartRead(pTwi, address, iaddress, isize);
}
/* Synchronous transfer*/
else {
/* Start read*/
TWI_StartRead(pTwi, address, iaddress, isize);
/* Read all bytes, setting STOP before the last byte*/
while (num > 0) {
/* Last byte ?*/
if (num == 1) {
TWI_Stop(pTwi);
}
/* Wait for byte then read and store it*/
timeout = 0;
while( !TWI_ByteReceived(pTwi) && (++timeout<TWITIMEOUTMAX) );
if (timeout == TWITIMEOUTMAX) {
// TRACE_ERROR("TWID Timeout BR\n\r");
}
*pData++ = TWI_ReadByte(pTwi);
num--;
}
/* Wait for transfer to be complete */
timeout = 0;
while( !TWI_TransferComplete(pTwi) && (++timeout<TWITIMEOUTMAX) );
if (timeout == TWITIMEOUTMAX) {
// TRACE_ERROR("TWID Timeout TC\n\r");
}
}
return 0;
}
/**
* \brief Asynchronously sends data to a slave on the TWI bus. An optional callback
* function is invoked whenever the transfer is complete.
* \param pTwid Pointer to a Twid instance.
* \param address TWI slave address.
* \param iaddress Optional slave internal address.
* \param isize Number of internal address bytes.
* \param pData Data buffer for storing received bytes.
* \param num Data buffer to send.
* \param pAsync Asynchronous transfer descriptor.
* \return 0 if the transfer has been started; otherwise returns a TWI error code.
*/
uint8_t TWID_Write(
Twid *pTwid,
uint8_t address,
uint32_t iaddress,
uint8_t isize,
uint8_t *pData,
uint32_t num,
Async *pAsync)
{
Twi *pTwi = pTwid->pTwi;
AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer;
uint32_t timeout;
assert( pTwi != NULL ) ;
assert( (address & 0x80) == 0 ) ;
assert( (iaddress & 0xFF000000) == 0 ) ;
assert( isize < 4 ) ;
/* Check that no transfer is already pending */
if (pTransfer) {
// TRACE_ERROR("TWI_Write: A transfer is already pending\n\r");
return TWID_ERROR_BUSY;
}
/* Asynchronous transfer */
if (pAsync) {
/* Update the transfer descriptor */
pTwid->pTransfer = pAsync;
pTransfer = (AsyncTwi *) pAsync;
pTransfer->status = ASYNC_STATUS_PENDING;
pTransfer->pData = pData;
pTransfer->num = num;
pTransfer->transferred = 1;
/* Enable write interrupt and start the transfer */
TWI_StartWrite(pTwi, address, iaddress, isize, *pData);
TWI_EnableIt(pTwi, TWI_IER_TXRDY);
}
/* Synchronous transfer*/
else {
// Start write
TWI_StartWrite(pTwi, address, iaddress, isize, *pData++);
num--;
/* Send all bytes */
while (num > 0) {
/* Wait before sending the next byte */
timeout = 0;
while( !TWI_ByteSent(pTwi) && (++timeout<TWITIMEOUTMAX) );
if (timeout == TWITIMEOUTMAX) {
// TRACE_ERROR("TWID Timeout BS\n\r");
}
TWI_WriteByte(pTwi, *pData++);
num--;
}
/* Wait for actual end of transfer */
timeout = 0;
/* Send a STOP condition */
TWI_SendSTOPCondition(pTwi);
while( !TWI_TransferComplete(pTwi) && (++timeout<TWITIMEOUTMAX) );
if (timeout == TWITIMEOUTMAX) {
// TRACE_ERROR("TWID Timeout TC2\n\r");
}
}
return 0;
}