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[sam] merging with state-of-the-art cmsis sam3 package

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This commit is contained in:
Thibaut VIARD
2011-10-26 19:48:57 +02:00
parent bb09067262
commit 538f548ec1
36 changed files with 1948 additions and 1711 deletions
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91
hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.c
View File

@@ -6,7 +6,7 @@
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \note
@@ -31,50 +31,50 @@ extern "C" {
#ifdef __GNUC__
/* Cortex-M3 core handlers */
extern void Reset_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void NMI_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void HardFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void MemManage_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void BusFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void UsageFault_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void SVC_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void DebugMon_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void PendSV_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void SysTick_Handler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
void Reset_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void NMI_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void MemManage_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void BusFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void UsageFault_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void DebugMon_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler(void) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
extern void ACC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void ADC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void CRCCU_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void DAC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void EEFC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void MCI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void PIOA_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void PIOB_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void PIOC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void PMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void PWM_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void RSTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void RTC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void RTT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void SMC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void SPI_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void SSC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void SUPC_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TC0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TC1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TC2_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TC3_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TC4_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TC5_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TWI0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void TWI1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void UART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void UART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void USART0_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void USART1_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void USBD_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler"))) ;
void ACC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void CRCCU_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void EEFC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void MCI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void PIOA_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void PIOB_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void PIOC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void PMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void PWM_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void RSTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void RTT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void SMC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void SPI_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void SSC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void SUPC_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TWI0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void TWI1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void UART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void UART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void USART0_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void USART1_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void USBD_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_IrqHandler(void) __attribute__ ((weak, alias("Dummy_Handler")));
#endif /* __GNUC__ */
#ifdef __ICCARM__
@@ -128,9 +128,10 @@ extern void WDT_IrqHandler( void ) __attribute__ ((weak, alias ("Dummy_Handler")
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler( void )
void Dummy_Handler(void)
{
while ( 1 ) {}
while (1) {
}
}
/* @cond 0 */

91
hardware/sam/system/libsam/cmsis/sam3s8/source/templates/exceptions.h
View File

@@ -6,7 +6,7 @@
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \author Atmel Corporation: http://www.atmel.com \n
@@ -26,56 +26,56 @@ extern "C" {
/* @endcond */
/* Function prototype for exception table items (interrupt handler). */
typedef void( *IntFunc )( void ) ;
typedef void (*IntFunc) (void);
/* Default empty handler */
extern void Dummy_Handler( void ) ;
void Dummy_Handler(void);
/* Cortex-M3 core handlers */
extern void Reset_Handler( void ) ;
extern void NMI_Handler( void ) ;
extern void HardFault_Handler( void ) ;
extern void MemManage_Handler( void ) ;
extern void BusFault_Handler( void ) ;
extern void UsageFault_Handler( void ) ;
extern void SVC_Handler( void ) ;
extern void DebugMon_Handler( void ) ;
extern void PendSV_Handler( void ) ;
extern void SysTick_Handler( void ) ;
void Reset_Handler(void);
void NMI_Handler(void);
void HardFault_Handler(void);
void MemManage_Handler(void);
void BusFault_Handler(void);
void UsageFault_Handler(void);
void SVC_Handler(void);
void DebugMon_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
/* Peripherals handlers */
extern void ACC_IrqHandler( void ) ;
extern void ADC_IrqHandler( void ) ;
extern void CRCCU_IrqHandler( void ) ;
extern void DAC_IrqHandler( void ) ;
extern void EEFC_IrqHandler( void ) ;
extern void MCI_IrqHandler( void ) ;
extern void PIOA_IrqHandler( void ) ;
extern void PIOB_IrqHandler( void ) ;
extern void PIOC_IrqHandler( void ) ;
extern void PMC_IrqHandler( void ) ;
extern void PWM_IrqHandler( void ) ;
extern void RSTC_IrqHandler( void ) ;
extern void RTC_IrqHandler( void ) ;
extern void RTT_IrqHandler( void ) ;
extern void SMC_IrqHandler( void ) ;
extern void SPI_IrqHandler( void ) ;
extern void SSC_IrqHandler( void ) ;
extern void SUPC_IrqHandler( void ) ;
extern void TC0_IrqHandler( void ) ;
extern void TC1_IrqHandler( void ) ;
extern void TC2_IrqHandler( void ) ;
extern void TC3_IrqHandler( void ) ;
extern void TC4_IrqHandler( void ) ;
extern void TC5_IrqHandler( void ) ;
extern void TWI0_IrqHandler( void ) ;
extern void TWI1_IrqHandler( void ) ;
extern void UART0_IrqHandler( void ) ;
extern void UART1_IrqHandler( void ) ;
extern void USART0_IrqHandler( void ) ;
extern void USART1_IrqHandler( void ) ;
extern void USBD_IrqHandler( void ) ;
extern void WDT_IrqHandler( void ) ;
void ACC_IrqHandler(void);
void ADC_IrqHandler(void);
void CRCCU_IrqHandler(void);
void DAC_IrqHandler(void);
void EEFC_IrqHandler(void);
void MCI_IrqHandler(void);
void PIOA_IrqHandler(void);
void PIOB_IrqHandler(void);
void PIOC_IrqHandler(void);
void PMC_IrqHandler(void);
void PWM_IrqHandler(void);
void RSTC_IrqHandler(void);
void RTC_IrqHandler(void);
void RTT_IrqHandler(void);
void SMC_IrqHandler(void);
void SPI_IrqHandler(void);
void SSC_IrqHandler(void);
void SUPC_IrqHandler(void);
void TC0_IrqHandler(void);
void TC1_IrqHandler(void);
void TC2_IrqHandler(void);
void TC3_IrqHandler(void);
void TC4_IrqHandler(void);
void TC5_IrqHandler(void);
void TWI0_IrqHandler(void);
void TWI1_IrqHandler(void);
void UART0_IrqHandler(void);
void UART1_IrqHandler(void);
void USART0_IrqHandler(void);
void USART1_IrqHandler(void);
void USBD_IrqHandler(void);
void WDT_IrqHandler(void);
/* @cond 0 */
/**INDENT-OFF**/
@@ -86,4 +86,3 @@ extern void WDT_IrqHandler( void ) ;
/* @endcond */
#endif /* EXCEPTIONS_H_INCLUDED */

181
hardware/sam/system/libsam/cmsis/sam3s8/source/templates/gcc/startup_sam3sd8.c
View File

@@ -12,14 +12,13 @@
*
******************************************************************************/
#include "exceptions.h"
#include "sam3s8.h"
#include "system_sam3sd8.h"
#include "../exceptions.h"
#include "sam3.h"
/* Stack Configuration */
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
__attribute__ ((aligned(8),section(".stack")))
uint32_t pdwStack[STACK_SIZE] ;
#define STACK_SIZE 0x900 /** Stack size (in DWords) */
__attribute__ ((aligned(8), section(".stack")))
uint32_t pdwStack[STACK_SIZE];
/* Initialize segments */
extern uint32_t _sfixed;
@@ -31,115 +30,111 @@ extern uint32_t _szero;
extern uint32_t _ezero;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
extern int main( void ) ;
int main(void);
/** \endcond */
extern void __libc_init_array( void ) ;
void __libc_init_array(void);
/* Exception Table */
__attribute__((section(".vectors")))
__attribute__ ((section(".vectors")))
IntFunc exception_table[] = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(IntFunc)(&pdwStack[STACK_SIZE-1]),
Reset_Handler,
/* Configure Initial Stack Pointer, using linker-generated symbols */
(IntFunc) (&pdwStack[STACK_SIZE - 1]),
Reset_Handler,
NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
0, 0, 0, 0, /* Reserved */
SVC_Handler,
DebugMon_Handler,
0, /* Reserved */
PendSV_Handler,
SysTick_Handler,
NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
0, 0, 0, 0, /* Reserved */
SVC_Handler,
DebugMon_Handler,
0, /* Reserved */
PendSV_Handler,
SysTick_Handler,
/* Configurable interrupts */
SUPC_IrqHandler, /* 0 Supply Controller */
RSTC_IrqHandler, /* 1 Reset Controller */
RTC_IrqHandler, /* 2 Real Time Clock */
RTT_IrqHandler, /* 3 Real Time Timer */
WDT_IrqHandler, /* 4 Watchdog Timer */
PMC_IrqHandler, /* 5 PMC */
EEFC_IrqHandler, /* 6 EEFC */
Dummy_Handler, /* 7 Reserved */
UART0_IrqHandler, /* 8 UART0 */
UART1_IrqHandler, /* 9 UART1 */
SMC_IrqHandler, /* 10 SMC */
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
USART0_IrqHandler, /* 14 USART 0 */
USART1_IrqHandler, /* 15 USART 1 */
Dummy_Handler, /* 16 Reserved */
Dummy_Handler, /* 17 Reserved */
MCI_IrqHandler, /* 18 MCI */
TWI0_IrqHandler, /* 19 TWI 0 */
TWI1_IrqHandler, /* 20 TWI 1 */
SPI_IrqHandler, /* 21 SPI */
SSC_IrqHandler, /* 22 SSC */
TC0_IrqHandler, /* 23 Timer Counter 0 */
TC1_IrqHandler, /* 24 Timer Counter 1 */
TC2_IrqHandler, /* 25 Timer Counter 2 */
TC3_IrqHandler, /* 26 Timer Counter 3 */
TC4_IrqHandler, /* 27 Timer Counter 4 */
TC5_IrqHandler, /* 28 Timer Counter 5 */
ADC_IrqHandler, /* 29 ADC controller */
DAC_IrqHandler, /* 30 DAC controller */
PWM_IrqHandler, /* 31 PWM */
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
ACC_IrqHandler, /* 33 Analog Comparator */
USBD_IrqHandler, /* 34 USB Device Port */
Dummy_Handler /* 35 not used */
/* Configurable interrupts */
SUPC_IrqHandler, /* 0 Supply Controller */
RSTC_IrqHandler, /* 1 Reset Controller */
RTC_IrqHandler, /* 2 Real Time Clock */
RTT_IrqHandler, /* 3 Real Time Timer */
WDT_IrqHandler, /* 4 Watchdog Timer */
PMC_IrqHandler, /* 5 PMC */
EEFC_IrqHandler, /* 6 EEFC */
Dummy_Handler, /* 7 Reserved */
UART0_IrqHandler, /* 8 UART0 */
UART1_IrqHandler, /* 9 UART1 */
SMC_IrqHandler, /* 10 SMC */
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
USART0_IrqHandler, /* 14 USART 0 */
USART1_IrqHandler, /* 15 USART 1 */
Dummy_Handler, /* 16 Reserved */
Dummy_Handler, /* 17 Reserved */
MCI_IrqHandler, /* 18 MCI */
TWI0_IrqHandler, /* 19 TWI 0 */
TWI1_IrqHandler, /* 20 TWI 1 */
SPI_IrqHandler, /* 21 SPI */
SSC_IrqHandler, /* 22 SSC */
TC0_IrqHandler, /* 23 Timer Counter 0 */
TC1_IrqHandler, /* 24 Timer Counter 1 */
TC2_IrqHandler, /* 25 Timer Counter 2 */
TC3_IrqHandler, /* 26 Timer Counter 3 */
TC4_IrqHandler, /* 27 Timer Counter 4 */
TC5_IrqHandler, /* 28 Timer Counter 5 */
ADC_IrqHandler, /* 29 ADC controller */
DAC_IrqHandler, /* 30 DAC controller */
PWM_IrqHandler, /* 31 PWM */
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
ACC_IrqHandler, /* 33 Analog Comparator */
USBD_IrqHandler, /* 34 USB Device Port */
Dummy_Handler /* 35 not used */
};
/* TEMPORARY PATCH FOR SCB */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler( void )
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest ;
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext ;
pDest = &_srelocate ;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if ( pSrc != pDest )
{
for ( ; pDest < &_erelocate ; )
{
*pDest++ = *pSrc++ ;
}
}
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for ( pDest = &_szero ; pDest < &_ezero ; )
{
*pDest++ = 0;
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *)&_sfixed;
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
{
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
}
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
}
/* Initialize the C library */
__libc_init_array() ;
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main() ;
/* Branch to main function */
main();
/* Infinite loop */
while ( 1 ) ;
/* Infinite loop */
while (1);
}

140
hardware/sam/system/libsam/cmsis/sam3s8/source/templates/iar/startup_sam3sd8.c
View File

@@ -12,106 +12,102 @@
*
******************************************************************************/
#include "exceptions.h"
#include "sam3s8.h"
#include "system_sam3sd8.h"
#include "../exceptions.h"
#include "sam3.h"
typedef void( *intfunc )( void );
typedef void (*intfunc) (void);
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
extern void __iar_program_start( void ) ;
extern int __low_level_init( void ) ;
void __iar_program_start(void);
int __low_level_init(void);
/* Exception Table */
#pragma language=extended
#pragma segment="CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0. */
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
const intvec_elem __vector_table[] =
{
{ .__ptr = __sfe( "CSTACK" ) },
Reset_Handler,
const intvec_elem __vector_table[] = {
{.__ptr = __sfe("CSTACK")},
Reset_Handler,
NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
0, 0, 0, 0, /* Reserved */
SVC_Handler,
DebugMon_Handler,
0, /* Reserved */
PendSV_Handler,
SysTick_Handler,
NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
0, 0, 0, 0, /* Reserved */
SVC_Handler,
DebugMon_Handler,
0, /* Reserved */
PendSV_Handler,
SysTick_Handler,
/* Configurable interrupts */
SUPC_IrqHandler, /* 0 Supply Controller */
RSTC_IrqHandler, /* 1 Reset Controller */
RTC_IrqHandler, /* 2 Real Time Clock */
RTT_IrqHandler, /* 3 Real Time Timer */
WDT_IrqHandler, /* 4 Watchdog Timer */
PMC_IrqHandler, /* 5 PMC */
EEFC_IrqHandler, /* 6 EEFC */
Dummy_Handler, /* 7 Reserved */
UART0_IrqHandler, /* 8 UART0 */
UART1_IrqHandler, /* 9 UART1 */
SMC_IrqHandler, /* 10 SMC */
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
USART0_IrqHandler, /* 14 USART 0 */
USART1_IrqHandler, /* 15 USART 1 */
Dummy_Handler, /* 16 Reserved */
Dummy_Handler, /* 17 Reserved */
MCI_IrqHandler, /* 18 MCI */
TWI0_IrqHandler, /* 19 TWI 0 */
TWI1_IrqHandler, /* 20 TWI 1 */
SPI_IrqHandler, /* 21 SPI */
SSC_IrqHandler, /* 22 SSC */
TC0_IrqHandler, /* 23 Timer Counter 0 */
TC1_IrqHandler, /* 24 Timer Counter 1 */
TC2_IrqHandler, /* 25 Timer Counter 2 */
TC3_IrqHandler, /* 26 Timer Counter 3 */
TC4_IrqHandler, /* 27 Timer Counter 4 */
TC5_IrqHandler, /* 28 Timer Counter 5 */
ADC_IrqHandler, /* 29 ADC controller */
DAC_IrqHandler, /* 30 DAC controller */
PWM_IrqHandler, /* 31 PWM */
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
ACC_IrqHandler, /* 33 Analog Comparator */
USBD_IrqHandler, /* 34 USB Device Port */
Dummy_Handler /* 35 not used */
/* Configurable interrupts */
SUPC_IrqHandler, /* 0 Supply Controller */
RSTC_IrqHandler, /* 1 Reset Controller */
RTC_IrqHandler, /* 2 Real Time Clock */
RTT_IrqHandler, /* 3 Real Time Timer */
WDT_IrqHandler, /* 4 Watchdog Timer */
PMC_IrqHandler, /* 5 PMC */
EEFC_IrqHandler, /* 6 EEFC */
Dummy_Handler, /* 7 Reserved */
UART0_IrqHandler, /* 8 UART0 */
UART1_IrqHandler, /* 9 UART1 */
SMC_IrqHandler, /* 10 SMC */
PIOA_IrqHandler, /* 11 Parallel IO Controller A */
PIOB_IrqHandler, /* 12 Parallel IO Controller B */
PIOC_IrqHandler, /* 13 Parallel IO Controller C */
USART0_IrqHandler, /* 14 USART 0 */
USART1_IrqHandler, /* 15 USART 1 */
Dummy_Handler, /* 16 Reserved */
Dummy_Handler, /* 17 Reserved */
MCI_IrqHandler, /* 18 MCI */
TWI0_IrqHandler, /* 19 TWI 0 */
TWI1_IrqHandler, /* 20 TWI 1 */
SPI_IrqHandler, /* 21 SPI */
SSC_IrqHandler, /* 22 SSC */
TC0_IrqHandler, /* 23 Timer Counter 0 */
TC1_IrqHandler, /* 24 Timer Counter 1 */
TC2_IrqHandler, /* 25 Timer Counter 2 */
TC3_IrqHandler, /* 26 Timer Counter 3 */
TC4_IrqHandler, /* 27 Timer Counter 4 */
TC5_IrqHandler, /* 28 Timer Counter 5 */
ADC_IrqHandler, /* 29 ADC controller */
DAC_IrqHandler, /* 30 DAC controller */
PWM_IrqHandler, /* 31 PWM */
CRCCU_IrqHandler, /* 32 CRC Calculation Unit */
ACC_IrqHandler, /* 33 Analog Comparator */
USBD_IrqHandler, /* 34 USB Device Port */
Dummy_Handler /* 35 not used */
};
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
extern int __low_level_init( void )
int __low_level_init(void)
{
uint32_t* pSrc = __section_begin( ".intvec" ) ;
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ( (uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk ) ;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
if ( ((uint32_t)pSrc >= IRAM_ADDR) && ((uint32_t)pSrc < IRAM_ADDR+IRAM_SIZE) )
{
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos ;
}
if (((uint32_t) pSrc >= IRAM_ADDR) && ((uint32_t) pSrc < IRAM_ADDR + IRAM_SIZE)) {
SCB->VTOR |= 1 << SCB_VTOR_TBLBASE_Pos;
}
return 1 ; /* if return 0, the data sections will not be initialized. */
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
extern void Reset_Handler( void )
void Reset_Handler(void)
{
__iar_program_start();
__iar_program_start();
}

179
hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.c
View File

@@ -1,13 +1,13 @@
/*! \file *********************************************************************
*
* \brief Provides the low-level initialization functions that called
* \brief Provides the low-level initialization functions that called
* on chip startup.
*
* $asf_license$
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \author Atmel Corporation: http://www.atmel.com \n
@@ -27,133 +27,164 @@ extern "C" {
/* @endcond */
/* Clock settings (64MHz) */
#define BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
#define BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
| CKGR_PLLAR_MULA(0xf) \
| CKGR_PLLAR_PLLACOUNT(0x3f) \
| CKGR_PLLAR_DIVA(0x3))
#define BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8))
#define SYS_BOARD_PLLAR (CKGR_PLLAR_STUCKTO1 \
| CKGR_PLLAR_MULA(0xf) \
| CKGR_PLLAR_PLLACOUNT(0x3f) \
| CKGR_PLLAR_DIVA(0x3))
#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK | PMC_MCKR_CSS_PLLA_CLK)
/* Clock Definitions */
#define XTAL32 ( 32768UL) /* 32k crystal frequency */
#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */
#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */
#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */
#define MAINCK_XTAL_HZ (12000000UL) /* External crystal frequency */
#define MCK_HZ (64000000UL) /* Processor frequency */
#define SYS_FREQ_XTAL_32K (32768UL) /* External 32K crystal frequency */
#define SYS_FREQ_XTAL_XTAL12M (12000000UL) /* External 12M crystal frequency */
#define SYS_FREQ_FWS_0 (21000000UL) /* Maximum operating frequency when FWS is 0 */
#define SYS_FREQ_FWS_1 (35000000UL) /* Maximum operating frequency when FWS is 1 */
#define SYS_FREQ_FWS_2 (60000000UL) /* Maximum operating frequency when FWS is 2 */
#define SYS_CKGR_MOR_KEY_VALUE CKGR_MOR_KEY(0x37) /* Key to unlock MOR register */
/* FIXME: should be generated by sock */
uint32_t SystemCoreClock = EFRC_OSC;
uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
/**
* \brief Setup the microcontroller system.
* Initialize the System and update the SystemFrequency variable.
*/
extern void SystemInit( void )
void SystemInit(void)
{
/* Set 3 FWS for Embedded Flash Access */
EFC->EEFC_FMR = EEFC_FMR_FWS(3);
/* Set 3 FWS for Embedded Flash Access */
EFC->EEFC_FMR = EEFC_FMR_FWS(CHIP_FLASH_WAIT_STATE);
/* Initialize main oscillator */
if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
{
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS));
}
/* Initialize main oscillator */
if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL)) {
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT |
CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
}
}
/* Switch to 3-20MHz Xtal oscillator */
PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
/* Switch to 3-20MHz Xtal oscillator */
PMC->CKGR_MOR = SYS_CKGR_MOR_KEY_VALUE | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN |
CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS));
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
}
PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
/* Initialize PLLA */
PMC->CKGR_PLLAR = BOARD_PLLAR;
while (!(PMC->PMC_SR & PMC_SR_LOCKA));
/* Initialize PLLA */
PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
}
/* Switch to main clock */
PMC->PMC_MCKR = (BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
/* Switch to main clock */
PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
/* Switch to PLLA */
PMC->PMC_MCKR = BOARD_MCKR ;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY));
/* Switch to PLLA */
PMC->PMC_MCKR = SYS_BOARD_MCKR;
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
}
SystemCoreClock = MCK_HZ;
SystemCoreClock = CHIP_FREQ_CPU_MAX;
}
extern void SystemCoreClockUpdate( void )
/**
* Initialize the flash and watchdog setting .
*/
void set_flash_and_watchdog(void)
{
/* Set FWS for Embedded Flash Access according operating frequency*/
if(SystemCoreClock < SYS_FREQ_FWS_0){
EFC->EEFC_FMR = EEFC_FMR_FWS(0);
}else if(SystemCoreClock < SYS_FREQ_FWS_1){
EFC->EEFC_FMR = EEFC_FMR_FWS(1);
}else if(SystemCoreClock < SYS_FREQ_FWS_2){
EFC->EEFC_FMR = EEFC_FMR_FWS(2);
}else{
EFC->EEFC_FMR = EEFC_FMR_FWS(3);
}
#ifndef CONFIG_KEEP_WATCHDOG_AFTER_INIT
/*Disable the watchdog */
WDT->WDT_MR = WDT_MR_WDDIS;
#endif
}
void SystemCoreClockUpdate(void)
{
/* Determine clock frequency according to clock register values */
switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */
if (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
SystemCoreClock = OSC32_CLK;
}
else {
SystemCoreClock = ERC_OSC;
}
SystemCoreClock = SYS_FREQ_XTAL_32K;
} else {
SystemCoreClock = CHIP_FREQ_SLCK_RC;
}
break;
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = MAINCK_XTAL_HZ;
}
else {
SystemCoreClock = EFRC_OSC;
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
} else {
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
case CKGR_MOR_MOSCRCF_4MHz:
break;
case CKGR_MOR_MOSCRCF_8MHz:
SystemCoreClock *= 2;
SystemCoreClock *= 2U;
break;
case CKGR_MOR_MOSCRCF_12MHz:
SystemCoreClock *= 3;
SystemCoreClock *= 3U;
break;
case 3:
default:
break;
}
}
break;
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */
case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */
if (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
SystemCoreClock = MAINCK_XTAL_HZ;
}
else {
SystemCoreClock = EFRC_OSC;
SystemCoreClock = SYS_FREQ_XTAL_XTAL12M;
} else {
SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
case CKGR_MOR_MOSCRCF_4MHz:
break;
case CKGR_MOR_MOSCRCF_8MHz:
SystemCoreClock *= 2;
SystemCoreClock *= 2U;
break;
case CKGR_MOR_MOSCRCF_12MHz:
SystemCoreClock *= 3;
SystemCoreClock *= 3U;
break;
case 3:
default:
break;
}
}
if ((PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK) {
SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_MULA_Pos) & 0x7FF) + 1);
SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> CKGR_PLLAR_DIVA_Pos) & 0x0FF));
}
else {
SystemCoreClock *= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_MULB_Pos) & 0x7FF) + 1);
SystemCoreClock /= ((((PMC->CKGR_PLLBR) >> CKGR_PLLBR_DIVB_Pos) & 0x0FF));
SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >>
CKGR_PLLAR_MULA_Pos) + 1U);
SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >>
CKGR_PLLAR_DIVA_Pos));
} else {
SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >>
CKGR_PLLBR_MULB_Pos) + 1U);
SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >>
CKGR_PLLBR_DIVB_Pos));
}
break;
}
if ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3) {
SystemCoreClock /= 3;
}
else {
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos);
}
SystemCoreClock /= 3U;
} else {
SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >>
PMC_MCKR_PRES_Pos);
}
}
/* @cond 0 */

14
hardware/sam/system/libsam/cmsis/sam3s8/source/templates/system_sam3sd8.h
View File

@@ -7,7 +7,7 @@
*
* \par Purpose
*
* This file provides basic support for Cortex-M processor based
* This file provides basic support for Cortex-M processor based
* microcontrollers.
*
* \author Atmel Corporation: http://www.atmel.com \n
@@ -34,13 +34,18 @@ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
void SystemInit(void);
/**
* Initialize the flash and watchdog setting .
*/
void set_flash_and_watchdog(void);
/**
* @brief Updates the SystemCoreClock with current core Clock
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
void SystemCoreClockUpdate(void);
/* @cond 0 */
/**INDENT-OFF**/
@@ -51,4 +56,3 @@ extern void SystemCoreClockUpdate(void);
/* @endcond */
#endif /* SYSTEM_SAM3SD8_H_INCLUDED */